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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Ruchika Gupta8ca8d822010-12-15 17:02:08 +00002/*
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
Ruchika Gupta8ca8d822010-12-15 17:02:08 +00004 */
5
6#ifndef __FSL_SECURE_BOOT_H
7#define __FSL_SECURE_BOOT_H
gaurav rana8b5ea652015-02-27 09:46:17 +05308#include <asm/config_mpc85xx.h>
Ruchika Gupta8ca8d822010-12-15 17:02:08 +00009
Udit Agarwald2dd2f72019-11-07 16:11:39 +000010#ifdef CONFIG_NXP_ESBC
Ruchika Gupta8ca8d822010-12-15 17:02:08 +000011#if defined(CONFIG_FSL_CORENET)
12#define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000
York Sun4620e1f2016-11-15 18:32:50 -080013#elif defined(CONFIG_TARGET_BSC9132QDS)
Aneesh Bansalbf955b22014-03-12 00:07:27 +053014#define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000
York Sunc6c51ae2016-11-16 11:51:24 -080015#elif defined(CONFIG_TARGET_C29XPCIE)
Aneesh Bansal11421b42014-12-12 15:35:04 +053016#define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000
Ruchika Gupta8ca8d822010-12-15 17:02:08 +000017#else
18#define CONFIG_SYS_PBI_FLASH_BASE 0xce000000
19#endif
20#define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000
21
York Sun2dfafc62016-11-18 11:47:35 -080022#if defined(CONFIG_TARGET_B4860QDS) || \
23 defined(CONFIG_TARGET_B4420QDS) || \
York Suna74e9232016-11-21 13:19:14 -080024 defined(CONFIG_TARGET_T4160QDS) || \
York Sunba04cb42016-11-21 13:22:08 -080025 defined(CONFIG_TARGET_T4240QDS) || \
York Sunc68b12d2016-12-28 08:43:36 -080026 defined(CONFIG_TARGET_T2080QDS) || \
York Suna05baa42016-12-28 08:43:37 -080027 defined(CONFIG_TARGET_T2080RDB) || \
York Sun097aa602016-11-21 11:25:26 -080028 defined(CONFIG_TARGET_T1042RDB) || \
29 defined(CONFIG_TARGET_T1042D4RDB) || \
30 defined(CONFIG_TARGET_T1042RDB_PI) || \
York Sun7d29dd62016-11-18 13:01:34 -080031 defined(CONFIG_ARCH_T1024)
Sumit Gargafaca2a2016-07-14 12:27:52 -040032#ifndef CONFIG_SYS_RAMBOOT
Aneesh Bansal8bcbc272014-03-18 23:40:26 +053033#define CONFIG_SYS_CPC_REINIT_F
Sumit Gargafaca2a2016-07-14 12:27:52 -040034#endif
gaurav rana8b5ea652015-02-27 09:46:17 +053035#define CONFIG_KEY_REVOCATION
Aneesh Bansal8bcbc272014-03-18 23:40:26 +053036#undef CONFIG_SYS_INIT_L3_ADDR
37#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
38#endif
39
Aneesh Bansale0f50152015-06-16 10:36:00 +053040#if defined(CONFIG_RAMBOOT_PBL)
41#undef CONFIG_SYS_INIT_L3_ADDR
Sumit Gargafaca2a2016-07-14 12:27:52 -040042#ifdef CONFIG_SYS_INIT_L3_VADDR
43#define CONFIG_SYS_INIT_L3_ADDR \
44 (CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \
45 0xbff00000
46#else
47#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
48#endif
Aneesh Bansale0f50152015-06-16 10:36:00 +053049#endif
50
York Sunc6c51ae2016-11-16 11:51:24 -080051#if defined(CONFIG_TARGET_C29XPCIE)
gaurav rana8b5ea652015-02-27 09:46:17 +053052#define CONFIG_KEY_REVOCATION
53#endif
54
York Sundf70d062016-11-18 11:20:40 -080055#if defined(CONFIG_ARCH_P3041) || \
York Sun84be8a92016-11-18 11:24:40 -080056 defined(CONFIG_ARCH_P4080) || \
York Suna3c5b662016-11-18 11:39:36 -080057 defined(CONFIG_ARCH_P5040) || \
York Sun5786fca2016-11-18 11:15:21 -080058 defined(CONFIG_ARCH_P2041)
gaurav rana8b5ea652015-02-27 09:46:17 +053059 #define CONFIG_FSL_TRUST_ARCH_v1
60#endif
61
Aneesh Bansald31bb3e2015-07-31 14:10:03 +053062#if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT)
gaurav rana8b5ea652015-02-27 09:46:17 +053063/* The key used for verification of next level images
64 * is picked up from an Extension Table which has
65 * been verified by the ISBC (Internal Secure boot Code)
Aneesh Bansald31bb3e2015-07-31 14:10:03 +053066 * in boot ROM of the SoC.
67 * The feature is only applicable in case of NOR boot and is
68 * not applicable in case of RAMBOOT (NAND, SD, SPI).
gaurav rana8b5ea652015-02-27 09:46:17 +053069 */
70#define CONFIG_FSL_ISBC_KEY_EXT
71#endif
Udit Agarwald2dd2f72019-11-07 16:11:39 +000072#endif /* #ifdef CONFIG_NXP_ESBC */
gaurav rana8b5ea652015-02-27 09:46:17 +053073
Aneesh Bansal43104702016-01-22 16:37:24 +053074#ifdef CONFIG_CHAIN_OF_TRUST
Simon Glass3aa66122016-09-12 23:18:23 -060075#ifdef CONFIG_SPL_BUILD
Sumit Gargf6d96cb2016-07-14 12:27:51 -040076/*
77 * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init
78 * due to space crunch on CPC and thus malloc will not work.
79 */
80#define CONFIG_SPL_PPAACT_ADDR 0x2e000000
81#define CONFIG_SPL_SPAACT_ADDR 0x2f000000
82#define CONFIG_SPL_JR0_LIODN_S 454
83#define CONFIG_SPL_JR0_LIODN_NS 458
84/*
85 * Define the key hash for U-Boot here if public/private key pair used to
86 * sign U-boot are different from the SRK hash put in the fuse
87 * Example of defining KEY_HASH is
88 * #define CONFIG_SPL_UBOOT_KEY_HASH \
89 * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
90 * else leave it defined as NULL
91 */
92
93#define CONFIG_SPL_UBOOT_KEY_HASH NULL
94#endif /* ifdef CONFIG_SPL_BUILD */
95
Aneesh Bansal43104702016-01-22 16:37:24 +053096#define CONFIG_FSL_SEC_MON
Aneesh Bansal43104702016-01-22 16:37:24 +053097
Sumit Gargf6d96cb2016-07-14 12:27:51 -040098#ifndef CONFIG_SPL_BUILD
99/*
100 * fsl_setenv_chain_of_trust() must be called from
Aneesh Bansalc6249092016-01-22 16:37:27 +0530101 * board_late_init()
102 */
Aneesh Bansalc6249092016-01-22 16:37:27 +0530103
Aneesh Bansalb69061d2015-06-16 10:36:43 +0530104/* If Boot Script is not on NOR and is required to be copied on RAM */
105#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
106#define CONFIG_BS_HDR_ADDR_RAM 0x00010000
Sumit Garg45642832016-06-14 13:52:39 -0400107#define CONFIG_BS_HDR_ADDR_DEVICE 0x00800000
Aneesh Bansalb69061d2015-06-16 10:36:43 +0530108#define CONFIG_BS_HDR_SIZE 0x00002000
109#define CONFIG_BS_ADDR_RAM 0x00012000
Sumit Garg45642832016-06-14 13:52:39 -0400110#define CONFIG_BS_ADDR_DEVICE 0x00802000
Aneesh Bansalb69061d2015-06-16 10:36:43 +0530111#define CONFIG_BS_SIZE 0x00001000
112
113#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
114#else
115
gaurav ranaf79323c2015-03-10 14:08:50 +0530116/* The bootscript header address is different for B4860 because the NOR
117 * mapping is different on B4 due to reduced NOR size.
118 */
York Sun2dfafc62016-11-18 11:47:35 -0800119#if defined(CONFIG_TARGET_B4860QDS) || defined(CONFIG_TARGET_B4420QDS)
gaurav ranaf79323c2015-03-10 14:08:50 +0530120#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xecc00000
121#elif defined(CONFIG_FSL_CORENET)
122#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xe8e00000
York Sun4620e1f2016-11-15 18:32:50 -0800123#elif defined(CONFIG_TARGET_BSC9132QDS)
gaurav ranaf79323c2015-03-10 14:08:50 +0530124#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x88020000
York Sunc6c51ae2016-11-16 11:51:24 -0800125#elif defined(CONFIG_TARGET_C29XPCIE)
gaurav ranaf79323c2015-03-10 14:08:50 +0530126#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xec020000
127#else
128#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000
129#endif
130
Aneesh Bansal43104702016-01-22 16:37:24 +0530131#endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */
gaurav ranaf79323c2015-03-10 14:08:50 +0530132
Aneesh Bansal43104702016-01-22 16:37:24 +0530133#include <config_fsl_chain_trust.h>
Sumit Gargf6d96cb2016-07-14 12:27:51 -0400134#endif /* #ifndef CONFIG_SPL_BUILD */
Aneesh Bansal43104702016-01-22 16:37:24 +0530135#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
Po Liud1030092013-08-21 14:20:21 +0800136#endif