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git01.mediatek.com / filogic / uboot / 559f1a8a3a1ec1920156892729dd92877161efca / . / arch / arm / include / asm / arch-rockchip / cru_rk3368.h
blob: 714cea85b4b9e4731e20bfc91b383743bc73b795 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Andy Yanb9909aa2017-05-15 17:49:56 +0800[diff] [blame]2/*
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4 * Author: Andy Yan <andy.yan@rock-chips.com>
Andy Yanb9909aa2017-05-15 17:49:56 +0800[diff] [blame]5 */
6#ifndef _ASM_ARCH_CRU_RK3368_H
7#define _ASM_ARCH_CRU_RK3368_H
8
Andy Yanb9909aa2017-05-15 17:49:56 +0800[diff] [blame]9/* RK3368 clock numbers */
10enum rk3368_pll_id {
11 APLLB,
12 APLLL,
13 DPLL,
14 CPLL,
15 GPLL,
16 NPLL,
17 PLL_COUNT,
18};
19
20struct rk3368_cru {
21 struct rk3368_pll {
22 unsigned int con0;
23 unsigned int con1;
24 unsigned int con2;
25 unsigned int con3;
26 } pll[6];
27 unsigned int reserved[0x28];
28 unsigned int clksel_con[56];
29 unsigned int reserved1[8];
30 unsigned int clkgate_con[25];
31 unsigned int reserved2[7];
32 unsigned int glb_srst_fst_val;
33 unsigned int glb_srst_snd_val;
34 unsigned int reserved3[0x1e];
35 unsigned int softrst_con[15];
36 unsigned int reserved4[0x11];
37 unsigned int misc_con;
38 unsigned int glb_cnt_th;
39 unsigned int glb_rst_con;
40 unsigned int glb_rst_st;
41 unsigned int reserved5[0x1c];
42 unsigned int sdmmc_con[2];
43 unsigned int sdio0_con[2];
44 unsigned int sdio1_con[2];
45 unsigned int emmc_con[2];
46};
47check_member(rk3368_cru, emmc_con[1], 0x41c);
48
49struct rk3368_clk_priv {
50 struct rk3368_cru *cru;
Andy Yanb9909aa2017-05-15 17:49:56 +0800[diff] [blame]51};
52
53enum {
54 /* PLL CON0 */
55 PLL_NR_SHIFT = 8,
56 PLL_NR_MASK = GENMASK(13, 8),
57 PLL_OD_SHIFT = 0,
58 PLL_OD_MASK = GENMASK(3, 0),
59
60 /* PLL CON1 */
61 PLL_LOCK_STA = BIT(31),
62 PLL_NF_SHIFT = 0,
63 PLL_NF_MASK = GENMASK(12, 0),
64
65 /* PLL CON2 */
66 PLL_BWADJ_SHIFT = 0,
67 PLL_BWADJ_MASK = GENMASK(11, 0),
68
69 /* PLL CON3 */
70 PLL_MODE_SHIFT = 8,
71 PLL_MODE_MASK = GENMASK(9, 8),
72 PLL_MODE_SLOW = 0,
73 PLL_MODE_NORMAL = 1,
74 PLL_MODE_DEEP_SLOW = 3,
75 PLL_RESET_SHIFT = 5,
76 PLL_RESET = 1,
77 PLL_RESET_MASK = GENMASK(5, 5),
78
79 /* CLKSEL12_CON */
80 MCU_STCLK_DIV_SHIFT = 8,
81 MCU_STCLK_DIV_MASK = GENMASK(10, 8),
82 MCU_PLL_SEL_SHIFT = 7,
83 MCU_PLL_SEL_MASK = BIT(7),
84 MCU_PLL_SEL_CPLL = 0,
85 MCU_PLL_SEL_GPLL = 1,
86 MCU_CLK_DIV_SHIFT = 0,
87 MCU_CLK_DIV_MASK = GENMASK(4, 0),
88
David Wu4771ba62017-09-20 14:37:50 +0800[diff] [blame]89 /* CLKSEL_CON25 */
90 CLK_SARADC_DIV_CON_SHIFT = 8,
91 CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8),
92 CLK_SARADC_DIV_CON_WIDTH = 8,
93
Philipp Tomsicha249f102017-07-14 19:57:39 +0200[diff] [blame]94 /* CLKSEL43_CON */
David Wue72793d2018-01-13 14:07:04 +0800[diff] [blame]95 GMAC_DIV_CON_SHIFT = 0x0,
96 GMAC_DIV_CON_MASK = GENMASK(4, 0),
97 GMAC_PLL_SHIFT = 6,
98 GMAC_PLL_MASK = GENMASK(7, 6),
99 GMAC_PLL_SELECT_NEW = (0x0 << GMAC_PLL_SHIFT),
100 GMAC_PLL_SELECT_CODEC = (0x1 << GMAC_PLL_SHIFT),
101 GMAC_PLL_SELECT_GENERAL = (0x2 << GMAC_PLL_SHIFT),
Philipp Tomsicha249f102017-07-14 19:57:39 +0200[diff] [blame]102 GMAC_MUX_SEL_EXTCLK = BIT(8),
103
Andy Yanb9909aa2017-05-15 17:49:56 +0800[diff] [blame]104 /* CLKSEL51_CON */
105 MMC_PLL_SEL_SHIFT = 8,
106 MMC_PLL_SEL_MASK = GENMASK(9, 8),
Philipp Tomsichfbf07a52017-07-04 14:49:38 +0200[diff] [blame]107 MMC_PLL_SEL_CPLL = (0 << MMC_PLL_SEL_SHIFT),
108 MMC_PLL_SEL_GPLL = (1 << MMC_PLL_SEL_SHIFT),
109 MMC_PLL_SEL_USBPHY_480M = (2 << MMC_PLL_SEL_SHIFT),
110 MMC_PLL_SEL_24M = (3 << MMC_PLL_SEL_SHIFT),
Andy Yanb9909aa2017-05-15 17:49:56 +0800[diff] [blame]111 MMC_CLK_DIV_SHIFT = 0,
112 MMC_CLK_DIV_MASK = GENMASK(6, 0),
113
114 /* SOFTRST1_CON */
115 MCU_PO_SRST_MASK = BIT(13),
116 MCU_SYS_SRST_MASK = BIT(12),
Philipp Tomsichd4d9c802017-07-04 14:50:11 +0200[diff] [blame]117 DMA1_SRST_REQ = BIT(2),
118
119 /* SOFTRST4_CON */
120 DMA2_SRST_REQ = BIT(0),
Andy Yanb9909aa2017-05-15 17:49:56 +0800[diff] [blame]121
122 /* GLB_RST_CON */
123 PMU_GLB_SRST_CTRL_SHIFT = 2,
124 PMU_GLB_SRST_CTRL_MASK = GENMASK(3, 2),
125 PMU_RST_BY_FST_GLB_SRST = 0,
126 PMU_RST_BY_SND_GLB_SRST = 1,
127 PMU_RST_DISABLE = 2,
128 WDT_GLB_SRST_CTRL_SHIFT = 1,
129 WDT_GLB_SRST_CTRL_MASK = BIT(1),
130 WDT_TRIGGER_SND_GLB_SRST = 0,
131 WDT_TRIGGER_FST_GLB_SRST = 1,
132 TSADC_GLB_SRST_CTRL_SHIFT = 0,
133 TSADC_GLB_SRST_CTRL_MASK = BIT(0),
134 TSADC_TRIGGER_SND_GLB_SRST = 0,
135 TSADC_TRIGGER_FST_GLB_SRST = 1,
136
137};
138#endif