Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 2 | /* |
Marek Behún | d63726e | 2022-06-01 17:17:06 +0200 | [diff] [blame] | 3 | * Copyright (C) 2017 Marek Behún <kabel@kernel.org> |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 4 | * Copyright (C) 2016 Tomas Hlavacek <tomas.hlavacek@nic.cz> |
| 5 | * |
| 6 | * Derived from the code for |
| 7 | * Marvell/db-88f6820-gp by Stefan Roese <sr@denx.de> |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #include <common.h> |
Simon Glass | 07dc93c | 2019-08-01 09:46:47 -0600 | [diff] [blame] | 11 | #include <env.h> |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 12 | #include <i2c.h> |
Simon Glass | a7b5130 | 2019-11-14 12:57:46 -0700 | [diff] [blame] | 13 | #include <init.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 14 | #include <log.h> |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 15 | #include <miiphy.h> |
Marek Behún | 91ef59c | 2021-07-15 19:21:02 +0200 | [diff] [blame] | 16 | #include <mtd.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 17 | #include <asm/global_data.h> |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 18 | #include <asm/io.h> |
| 19 | #include <asm/arch/cpu.h> |
| 20 | #include <asm/arch/soc.h> |
| 21 | #include <dm/uclass.h> |
Pali Rohár | 1e0a975 | 2022-07-29 13:29:07 +0200 | [diff] [blame] | 22 | #include <dt-bindings/gpio/gpio.h> |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 23 | #include <fdt_support.h> |
| 24 | #include <time.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 25 | #include <linux/bitops.h> |
Pali Rohár | 1e0a975 | 2022-07-29 13:29:07 +0200 | [diff] [blame] | 26 | #include <linux/delay.h> |
Simon Glass | 48b6c6b | 2019-11-14 12:57:16 -0700 | [diff] [blame] | 27 | #include <u-boot/crc.h> |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 28 | |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 29 | #include "../drivers/ddr/marvell/a38x/ddr3_init.h" |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 30 | #include <../serdes/a38x/high_speed_env_spec.h> |
Pali Rohár | 0387f7f | 2022-04-08 16:30:12 +0200 | [diff] [blame] | 31 | #include "../turris_atsha_otp.h" |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 32 | |
| 33 | DECLARE_GLOBAL_DATA_PTR; |
| 34 | |
Marek Behún | ba53b6b | 2019-05-02 16:53:30 +0200 | [diff] [blame] | 35 | #define OMNIA_I2C_BUS_NAME "i2c@11000->i2cmux@70->i2c@0" |
| 36 | |
| 37 | #define OMNIA_I2C_MCU_CHIP_ADDR 0x2a |
| 38 | #define OMNIA_I2C_MCU_CHIP_LEN 1 |
| 39 | |
| 40 | #define OMNIA_I2C_EEPROM_CHIP_ADDR 0x54 |
| 41 | #define OMNIA_I2C_EEPROM_CHIP_LEN 2 |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 42 | #define OMNIA_I2C_EEPROM_MAGIC 0x0341a034 |
| 43 | |
Pali Rohár | 30e398d | 2022-04-29 13:53:25 +0200 | [diff] [blame] | 44 | #define A385_SYS_RSTOUT_MASK MVEBU_REGISTER(0x18260) |
| 45 | #define A385_SYS_RSTOUT_MASK_WD BIT(10) |
Pali Rohár | 7fcda0c | 2021-11-09 17:14:02 +0100 | [diff] [blame] | 46 | |
| 47 | #define A385_WDT_GLOBAL_CTRL MVEBU_REGISTER(0x20300) |
| 48 | #define A385_WDT_GLOBAL_RATIO_MASK GENMASK(18, 16) |
| 49 | #define A385_WDT_GLOBAL_RATIO_SHIFT 16 |
| 50 | #define A385_WDT_GLOBAL_25MHZ BIT(10) |
| 51 | #define A385_WDT_GLOBAL_ENABLE BIT(8) |
| 52 | |
| 53 | #define A385_WDT_GLOBAL_STATUS MVEBU_REGISTER(0x20304) |
| 54 | #define A385_WDT_GLOBAL_EXPIRED BIT(31) |
| 55 | |
| 56 | #define A385_WDT_DURATION MVEBU_REGISTER(0x20334) |
| 57 | |
| 58 | #define A385_WD_RSTOUT_UNMASK MVEBU_REGISTER(0x20704) |
| 59 | #define A385_WD_RSTOUT_UNMASK_GLOBAL BIT(8) |
| 60 | |
Marek Behún | ba53b6b | 2019-05-02 16:53:30 +0200 | [diff] [blame] | 61 | enum mcu_commands { |
| 62 | CMD_GET_STATUS_WORD = 0x01, |
| 63 | CMD_GET_RESET = 0x09, |
| 64 | CMD_WATCHDOG_STATE = 0x0b, |
Pali Rohár | 4798ba9 | 2022-07-29 13:29:06 +0200 | [diff] [blame] | 65 | |
| 66 | /* available if STS_FEATURES_SUPPORTED bit set in status word */ |
| 67 | CMD_GET_FEATURES = 0x10, |
Pali Rohár | 1e0a975 | 2022-07-29 13:29:07 +0200 | [diff] [blame] | 68 | |
| 69 | /* available if EXT_CMD bit set in features */ |
| 70 | CMD_EXT_CONTROL = 0x12, |
Marek Behún | ba53b6b | 2019-05-02 16:53:30 +0200 | [diff] [blame] | 71 | }; |
| 72 | |
| 73 | enum status_word_bits { |
Pali Rohár | 4798ba9 | 2022-07-29 13:29:06 +0200 | [diff] [blame] | 74 | STS_MCU_TYPE_MASK = GENMASK(1, 0), |
| 75 | STS_MCU_TYPE_STM32 = 0, |
| 76 | STS_MCU_TYPE_GD32 = 1, |
| 77 | STS_MCU_TYPE_MKL = 2, |
| 78 | STS_MCU_TYPE_UNKN = 3, |
| 79 | STS_FEATURES_SUPPORTED = BIT(2), |
Marek Behún | ba53b6b | 2019-05-02 16:53:30 +0200 | [diff] [blame] | 80 | CARD_DET_STSBIT = 0x0010, |
| 81 | MSATA_IND_STSBIT = 0x0020, |
| 82 | }; |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 83 | |
Pali Rohár | 4798ba9 | 2022-07-29 13:29:06 +0200 | [diff] [blame] | 84 | /* CMD_GET_FEATURES */ |
| 85 | enum features_e { |
| 86 | FEAT_PERIPH_MCU = BIT(0), |
Pali Rohár | 1e0a975 | 2022-07-29 13:29:07 +0200 | [diff] [blame] | 87 | FEAT_EXT_CMDS = BIT(1), |
| 88 | }; |
| 89 | |
| 90 | /* CMD_EXT_CONTROL */ |
| 91 | enum ext_ctl_e { |
| 92 | EXT_CTL_nRES_LAN = BIT(1), |
| 93 | EXT_CTL_nRES_PHY = BIT(2), |
| 94 | EXT_CTL_nPERST0 = BIT(3), |
| 95 | EXT_CTL_nPERST1 = BIT(4), |
| 96 | EXT_CTL_nPERST2 = BIT(5), |
Pali Rohár | 4798ba9 | 2022-07-29 13:29:06 +0200 | [diff] [blame] | 97 | }; |
| 98 | |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 99 | /* |
| 100 | * Those values and defines are taken from the Marvell U-Boot version |
| 101 | * "u-boot-2013.01-2014_T3.0" |
| 102 | */ |
| 103 | #define OMNIA_GPP_OUT_ENA_LOW \ |
| 104 | (~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \ |
| 105 | BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \ |
| 106 | BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31))) |
| 107 | #define OMNIA_GPP_OUT_ENA_MID \ |
| 108 | (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \ |
| 109 | BIT(16) | BIT(17) | BIT(18))) |
| 110 | |
| 111 | #define OMNIA_GPP_OUT_VAL_LOW 0x0 |
| 112 | #define OMNIA_GPP_OUT_VAL_MID 0x0 |
| 113 | #define OMNIA_GPP_POL_LOW 0x0 |
| 114 | #define OMNIA_GPP_POL_MID 0x0 |
| 115 | |
Pali Rohár | 3c4dd98 | 2022-03-02 12:47:54 +0100 | [diff] [blame] | 116 | static struct serdes_map board_serdes_map[] = { |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 117 | {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, |
| 118 | {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, |
| 119 | {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, |
| 120 | {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, |
| 121 | {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, |
| 122 | {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0} |
| 123 | }; |
| 124 | |
Marek Behún | ba53b6b | 2019-05-02 16:53:30 +0200 | [diff] [blame] | 125 | static struct udevice *omnia_get_i2c_chip(const char *name, uint addr, |
| 126 | uint offset_len) |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 127 | { |
| 128 | struct udevice *bus, *dev; |
Marek Behún | ba53b6b | 2019-05-02 16:53:30 +0200 | [diff] [blame] | 129 | int ret; |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 130 | |
Marek Behún | ba53b6b | 2019-05-02 16:53:30 +0200 | [diff] [blame] | 131 | ret = uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_BUS_NAME, &bus); |
| 132 | if (ret) { |
| 133 | printf("Cannot get I2C bus %s: uclass_get_device_by_name failed: %i\n", |
| 134 | OMNIA_I2C_BUS_NAME, ret); |
| 135 | return NULL; |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 136 | } |
| 137 | |
Marek Behún | ba53b6b | 2019-05-02 16:53:30 +0200 | [diff] [blame] | 138 | ret = i2c_get_chip(bus, addr, offset_len, &dev); |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 139 | if (ret) { |
Marek Behún | ba53b6b | 2019-05-02 16:53:30 +0200 | [diff] [blame] | 140 | printf("Cannot get %s I2C chip: i2c_get_chip failed: %i\n", |
| 141 | name, ret); |
| 142 | return NULL; |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 143 | } |
| 144 | |
Marek Behún | ba53b6b | 2019-05-02 16:53:30 +0200 | [diff] [blame] | 145 | return dev; |
| 146 | } |
Marek Behún | d0b374d | 2017-08-04 15:28:25 +0200 | [diff] [blame] | 147 | |
Marek Behún | ba53b6b | 2019-05-02 16:53:30 +0200 | [diff] [blame] | 148 | static int omnia_mcu_read(u8 cmd, void *buf, int len) |
| 149 | { |
| 150 | struct udevice *chip; |
| 151 | |
| 152 | chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR, |
| 153 | OMNIA_I2C_MCU_CHIP_LEN); |
| 154 | if (!chip) |
| 155 | return -ENODEV; |
| 156 | |
| 157 | return dm_i2c_read(chip, cmd, buf, len); |
| 158 | } |
| 159 | |
Marek Behún | ba53b6b | 2019-05-02 16:53:30 +0200 | [diff] [blame] | 160 | static int omnia_mcu_write(u8 cmd, const void *buf, int len) |
| 161 | { |
| 162 | struct udevice *chip; |
| 163 | |
| 164 | chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR, |
| 165 | OMNIA_I2C_MCU_CHIP_LEN); |
| 166 | if (!chip) |
| 167 | return -ENODEV; |
| 168 | |
| 169 | return dm_i2c_write(chip, cmd, buf, len); |
| 170 | } |
| 171 | |
Pali Rohár | 7fcda0c | 2021-11-09 17:14:02 +0100 | [diff] [blame] | 172 | static void enable_a385_watchdog(unsigned int timeout_minutes) |
| 173 | { |
| 174 | struct sar_freq_modes sar_freq; |
| 175 | u32 watchdog_freq; |
| 176 | |
| 177 | printf("Enabling A385 watchdog with %u minutes timeout...\n", |
| 178 | timeout_minutes); |
| 179 | |
| 180 | /* |
| 181 | * Use NBCLK clock (a.k.a. L2 clock) as watchdog input clock with |
| 182 | * its maximal ratio 7 instead of default fixed 25 MHz clock. |
| 183 | * It allows to set watchdog duration up to the 22 minutes. |
| 184 | */ |
| 185 | clrsetbits_32(A385_WDT_GLOBAL_CTRL, |
| 186 | A385_WDT_GLOBAL_25MHZ | A385_WDT_GLOBAL_RATIO_MASK, |
| 187 | 7 << A385_WDT_GLOBAL_RATIO_SHIFT); |
| 188 | |
| 189 | /* |
| 190 | * Calculate watchdog clock frequency. It is defined by formula: |
| 191 | * freq = NBCLK / 2 / (2 ^ ratio) |
| 192 | * We set ratio to the maximal possible value 7. |
| 193 | */ |
| 194 | get_sar_freq(&sar_freq); |
| 195 | watchdog_freq = sar_freq.nb_clk * 1000000 / 2 / (1 << 7); |
| 196 | |
| 197 | /* Set watchdog duration */ |
| 198 | writel(timeout_minutes * 60 * watchdog_freq, A385_WDT_DURATION); |
| 199 | |
| 200 | /* Clear the watchdog expiration bit */ |
| 201 | clrbits_32(A385_WDT_GLOBAL_STATUS, A385_WDT_GLOBAL_EXPIRED); |
| 202 | |
| 203 | /* Enable watchdog timer */ |
| 204 | setbits_32(A385_WDT_GLOBAL_CTRL, A385_WDT_GLOBAL_ENABLE); |
| 205 | |
| 206 | /* Enable reset on watchdog */ |
| 207 | setbits_32(A385_WD_RSTOUT_UNMASK, A385_WD_RSTOUT_UNMASK_GLOBAL); |
| 208 | |
| 209 | /* Unmask reset for watchdog */ |
Pali Rohár | 30e398d | 2022-04-29 13:53:25 +0200 | [diff] [blame] | 210 | clrbits_32(A385_SYS_RSTOUT_MASK, A385_SYS_RSTOUT_MASK_WD); |
Pali Rohár | 7fcda0c | 2021-11-09 17:14:02 +0100 | [diff] [blame] | 211 | } |
| 212 | |
Marek Behún | ba53b6b | 2019-05-02 16:53:30 +0200 | [diff] [blame] | 213 | static bool disable_mcu_watchdog(void) |
| 214 | { |
| 215 | int ret; |
| 216 | |
| 217 | puts("Disabling MCU watchdog... "); |
| 218 | |
| 219 | ret = omnia_mcu_write(CMD_WATCHDOG_STATE, "\x00", 1); |
| 220 | if (ret) { |
| 221 | printf("omnia_mcu_write failed: %i\n", ret); |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 222 | return false; |
| 223 | } |
| 224 | |
Marek Behún | ba53b6b | 2019-05-02 16:53:30 +0200 | [diff] [blame] | 225 | puts("disabled\n"); |
| 226 | |
| 227 | return true; |
| 228 | } |
Marek Behún | ba53b6b | 2019-05-02 16:53:30 +0200 | [diff] [blame] | 229 | |
Pali Rohár | f8f305b | 2022-03-02 12:47:55 +0100 | [diff] [blame] | 230 | static bool omnia_detect_sata(const char *msata_slot) |
Marek Behún | ba53b6b | 2019-05-02 16:53:30 +0200 | [diff] [blame] | 231 | { |
| 232 | int ret; |
| 233 | u16 stsword; |
| 234 | |
| 235 | puts("MiniPCIe/mSATA card detection... "); |
| 236 | |
Pali Rohár | f8f305b | 2022-03-02 12:47:55 +0100 | [diff] [blame] | 237 | if (msata_slot) { |
| 238 | if (strcmp(msata_slot, "pcie") == 0) { |
| 239 | puts("forced to MiniPCIe via env\n"); |
| 240 | return false; |
| 241 | } else if (strcmp(msata_slot, "sata") == 0) { |
| 242 | puts("forced to mSATA via env\n"); |
| 243 | return true; |
| 244 | } else if (strcmp(msata_slot, "auto") != 0) { |
| 245 | printf("unsupported env value '%s', fallback to... ", msata_slot); |
| 246 | } |
| 247 | } |
| 248 | |
Marek Behún | ba53b6b | 2019-05-02 16:53:30 +0200 | [diff] [blame] | 249 | ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &stsword, sizeof(stsword)); |
| 250 | if (ret) { |
| 251 | printf("omnia_mcu_read failed: %i, defaulting to MiniPCIe card\n", |
| 252 | ret); |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 253 | return false; |
| 254 | } |
| 255 | |
Marek Behún | ba53b6b | 2019-05-02 16:53:30 +0200 | [diff] [blame] | 256 | if (!(stsword & CARD_DET_STSBIT)) { |
| 257 | puts("none\n"); |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 258 | return false; |
| 259 | } |
Marek Behún | ba53b6b | 2019-05-02 16:53:30 +0200 | [diff] [blame] | 260 | |
| 261 | if (stsword & MSATA_IND_STSBIT) |
| 262 | puts("mSATA\n"); |
| 263 | else |
| 264 | puts("MiniPCIe\n"); |
| 265 | |
| 266 | return stsword & MSATA_IND_STSBIT ? true : false; |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 267 | } |
| 268 | |
Pali Rohár | 93a89c5 | 2022-03-02 12:47:58 +0100 | [diff] [blame] | 269 | static bool omnia_detect_wwan_usb3(const char *wwan_slot) |
| 270 | { |
| 271 | puts("WWAN slot configuration... "); |
| 272 | |
| 273 | if (wwan_slot && strcmp(wwan_slot, "usb3") == 0) { |
| 274 | puts("USB3.0\n"); |
| 275 | return true; |
| 276 | } |
| 277 | |
| 278 | if (wwan_slot && strcmp(wwan_slot, "pcie") != 0) |
| 279 | printf("unsupported env value '%s', fallback to... ", wwan_slot); |
| 280 | |
| 281 | puts("PCIe+USB2.0\n"); |
| 282 | return false; |
| 283 | } |
| 284 | |
Pali Rohár | c13401b | 2022-03-02 12:47:52 +0100 | [diff] [blame] | 285 | void *env_sf_get_env_addr(void) |
| 286 | { |
| 287 | /* SPI Flash is mapped to address 0xD4000000 only in SPL */ |
| 288 | #ifdef CONFIG_SPL_BUILD |
| 289 | return (void *)0xD4000000 + CONFIG_ENV_OFFSET; |
| 290 | #else |
| 291 | return NULL; |
| 292 | #endif |
| 293 | } |
| 294 | |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 295 | int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count) |
| 296 | { |
Pali Rohár | f8f305b | 2022-03-02 12:47:55 +0100 | [diff] [blame] | 297 | #ifdef CONFIG_SPL_ENV_SUPPORT |
| 298 | /* Do not use env_load() as malloc() pool is too small at this stage */ |
| 299 | bool has_env = (env_init() == 0); |
| 300 | #endif |
| 301 | const char *env_value = NULL; |
| 302 | |
| 303 | #ifdef CONFIG_SPL_ENV_SUPPORT |
| 304 | /* beware that env_get() returns static allocated memory */ |
| 305 | env_value = has_env ? env_get("omnia_msata_slot") : NULL; |
| 306 | #endif |
| 307 | |
| 308 | if (omnia_detect_sata(env_value)) { |
Pali Rohár | 3c4dd98 | 2022-03-02 12:47:54 +0100 | [diff] [blame] | 309 | /* Change SerDes for first mPCIe port (mSATA) from PCIe to SATA */ |
| 310 | board_serdes_map[0].serdes_type = SATA0; |
| 311 | board_serdes_map[0].serdes_speed = SERDES_SPEED_6_GBPS; |
| 312 | board_serdes_map[0].serdes_mode = SERDES_DEFAULT_MODE; |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 313 | } |
| 314 | |
Pali Rohár | 93a89c5 | 2022-03-02 12:47:58 +0100 | [diff] [blame] | 315 | #ifdef CONFIG_SPL_ENV_SUPPORT |
| 316 | /* beware that env_get() returns static allocated memory */ |
| 317 | env_value = has_env ? env_get("omnia_wwan_slot") : NULL; |
| 318 | #endif |
| 319 | |
| 320 | if (omnia_detect_wwan_usb3(env_value)) { |
| 321 | /* Disable SerDes for USB 3.0 pins on the front USB-A port */ |
| 322 | board_serdes_map[1].serdes_type = DEFAULT_SERDES; |
| 323 | /* Change SerDes for third mPCIe port (WWAN) from PCIe to USB 3.0 */ |
| 324 | board_serdes_map[4].serdes_type = USB3_HOST0; |
| 325 | board_serdes_map[4].serdes_speed = SERDES_SPEED_5_GBPS; |
| 326 | board_serdes_map[4].serdes_mode = SERDES_DEFAULT_MODE; |
| 327 | } |
| 328 | |
Pali Rohár | 3c4dd98 | 2022-03-02 12:47:54 +0100 | [diff] [blame] | 329 | *serdes_map_array = board_serdes_map; |
| 330 | *count = ARRAY_SIZE(board_serdes_map); |
| 331 | |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 332 | return 0; |
| 333 | } |
| 334 | |
| 335 | struct omnia_eeprom { |
| 336 | u32 magic; |
| 337 | u32 ramsize; |
| 338 | char region[4]; |
| 339 | u32 crc; |
| 340 | }; |
| 341 | |
| 342 | static bool omnia_read_eeprom(struct omnia_eeprom *oep) |
| 343 | { |
Marek Behún | ba53b6b | 2019-05-02 16:53:30 +0200 | [diff] [blame] | 344 | struct udevice *chip; |
| 345 | u32 crc; |
| 346 | int ret; |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 347 | |
Marek Behún | ba53b6b | 2019-05-02 16:53:30 +0200 | [diff] [blame] | 348 | chip = omnia_get_i2c_chip("EEPROM", OMNIA_I2C_EEPROM_CHIP_ADDR, |
| 349 | OMNIA_I2C_EEPROM_CHIP_LEN); |
| 350 | |
| 351 | if (!chip) |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 352 | return false; |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 353 | |
Marek Behún | ba53b6b | 2019-05-02 16:53:30 +0200 | [diff] [blame] | 354 | ret = dm_i2c_read(chip, 0, (void *)oep, sizeof(*oep)); |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 355 | if (ret) { |
Marek Behún | ba53b6b | 2019-05-02 16:53:30 +0200 | [diff] [blame] | 356 | printf("dm_i2c_read failed: %i, cannot read EEPROM\n", ret); |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 357 | return false; |
| 358 | } |
| 359 | |
Marek Behún | ba53b6b | 2019-05-02 16:53:30 +0200 | [diff] [blame] | 360 | if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) { |
| 361 | printf("bad EEPROM magic number (%08x, should be %08x)\n", |
| 362 | oep->magic, OMNIA_I2C_EEPROM_MAGIC); |
| 363 | return false; |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 364 | } |
| 365 | |
Marek Behún | ba53b6b | 2019-05-02 16:53:30 +0200 | [diff] [blame] | 366 | crc = crc32(0, (void *)oep, sizeof(*oep) - 4); |
| 367 | if (crc != oep->crc) { |
| 368 | printf("bad EEPROM CRC (stored %08x, computed %08x)\n", |
| 369 | oep->crc, crc); |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 370 | return false; |
| 371 | } |
| 372 | |
| 373 | return true; |
| 374 | } |
| 375 | |
Marek Behún | 77652c7 | 2019-05-02 16:53:33 +0200 | [diff] [blame] | 376 | static int omnia_get_ram_size_gb(void) |
| 377 | { |
| 378 | static int ram_size; |
| 379 | struct omnia_eeprom oep; |
| 380 | |
| 381 | if (!ram_size) { |
| 382 | /* Get the board config from EEPROM */ |
| 383 | if (omnia_read_eeprom(&oep)) { |
| 384 | debug("Memory config in EEPROM: 0x%02x\n", oep.ramsize); |
| 385 | |
| 386 | if (oep.ramsize == 0x2) |
| 387 | ram_size = 2; |
| 388 | else |
| 389 | ram_size = 1; |
| 390 | } else { |
| 391 | /* Hardcoded fallback */ |
| 392 | puts("Memory config from EEPROM read failed!\n"); |
| 393 | puts("Falling back to default 1 GiB!\n"); |
| 394 | ram_size = 1; |
| 395 | } |
| 396 | } |
| 397 | |
| 398 | return ram_size; |
| 399 | } |
| 400 | |
Pali Rohár | 4798ba9 | 2022-07-29 13:29:06 +0200 | [diff] [blame] | 401 | static const char * const omnia_get_mcu_type(void) |
| 402 | { |
| 403 | static const char * const mcu_types[] = { |
| 404 | [STS_MCU_TYPE_STM32] = "STM32", |
| 405 | [STS_MCU_TYPE_GD32] = "GD32", |
| 406 | [STS_MCU_TYPE_MKL] = "MKL", |
| 407 | [STS_MCU_TYPE_UNKN] = "unknown", |
| 408 | }; |
| 409 | static const char * const mcu_types_with_perip_resets[] = { |
| 410 | [STS_MCU_TYPE_STM32] = "STM32 (with peripheral resets)", |
| 411 | [STS_MCU_TYPE_GD32] = "GD32 (with peripheral resets)", |
| 412 | [STS_MCU_TYPE_MKL] = "MKL (with peripheral resets)", |
| 413 | [STS_MCU_TYPE_UNKN] = "unknown (with peripheral resets)", |
| 414 | }; |
| 415 | u16 stsword, features; |
| 416 | int ret; |
| 417 | |
| 418 | ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &stsword, sizeof(stsword)); |
| 419 | if (ret) |
| 420 | return "unknown"; |
| 421 | |
| 422 | if (stsword & STS_FEATURES_SUPPORTED) { |
| 423 | ret = omnia_mcu_read(CMD_GET_FEATURES, &features, sizeof(features)); |
| 424 | if (ret == 0 && (features & FEAT_PERIPH_MCU)) |
| 425 | return mcu_types_with_perip_resets[stsword & STS_MCU_TYPE_MASK]; |
| 426 | } |
| 427 | |
| 428 | return mcu_types[stsword & STS_MCU_TYPE_MASK]; |
| 429 | } |
| 430 | |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 431 | /* |
| 432 | * Define the DDR layout / topology here in the board file. This will |
| 433 | * be used by the DDR3 init code in the SPL U-Boot version to configure |
| 434 | * the DDR3 controller. |
| 435 | */ |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 436 | static struct mv_ddr_topology_map board_topology_map_1g = { |
| 437 | DEBUG_LEVEL_ERROR, |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 438 | 0x1, /* active interfaces */ |
| 439 | /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ |
| 440 | { { { {0x1, 0, 0, 0}, |
| 441 | {0x1, 0, 0, 0}, |
| 442 | {0x1, 0, 0, 0}, |
| 443 | {0x1, 0, 0, 0}, |
| 444 | {0x1, 0, 0, 0} }, |
| 445 | SPEED_BIN_DDR_1600K, /* speed_bin */ |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 446 | MV_DDR_DEV_WIDTH_16BIT, /* memory_width */ |
| 447 | MV_DDR_DIE_CAP_4GBIT, /* mem_size */ |
Chris Packham | 4bf81db | 2018-12-03 14:26:49 +1300 | [diff] [blame] | 448 | MV_DDR_FREQ_800, /* frequency */ |
Chris Packham | dd092bd | 2017-11-29 10:38:34 +1300 | [diff] [blame] | 449 | 0, 0, /* cas_wl cas_l */ |
Chris Packham | 3a09e13 | 2018-05-10 13:28:30 +1200 | [diff] [blame] | 450 | MV_DDR_TEMP_NORMAL, /* temperature */ |
| 451 | MV_DDR_TIM_2T} }, /* timing */ |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 452 | BUS_MASK_32BIT, /* Busses mask */ |
| 453 | MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ |
Moti Buskila | 498475e | 2021-02-19 17:11:19 +0100 | [diff] [blame] | 454 | NOT_COMBINED, /* ddr twin-die combined */ |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 455 | { {0} }, /* raw spd data */ |
| 456 | {0} /* timing parameters */ |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 457 | }; |
| 458 | |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 459 | static struct mv_ddr_topology_map board_topology_map_2g = { |
| 460 | DEBUG_LEVEL_ERROR, |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 461 | 0x1, /* active interfaces */ |
| 462 | /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ |
| 463 | { { { {0x1, 0, 0, 0}, |
| 464 | {0x1, 0, 0, 0}, |
| 465 | {0x1, 0, 0, 0}, |
| 466 | {0x1, 0, 0, 0}, |
| 467 | {0x1, 0, 0, 0} }, |
| 468 | SPEED_BIN_DDR_1600K, /* speed_bin */ |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 469 | MV_DDR_DEV_WIDTH_16BIT, /* memory_width */ |
| 470 | MV_DDR_DIE_CAP_8GBIT, /* mem_size */ |
Chris Packham | 4bf81db | 2018-12-03 14:26:49 +1300 | [diff] [blame] | 471 | MV_DDR_FREQ_800, /* frequency */ |
Chris Packham | dd092bd | 2017-11-29 10:38:34 +1300 | [diff] [blame] | 472 | 0, 0, /* cas_wl cas_l */ |
Chris Packham | 3a09e13 | 2018-05-10 13:28:30 +1200 | [diff] [blame] | 473 | MV_DDR_TEMP_NORMAL, /* temperature */ |
| 474 | MV_DDR_TIM_2T} }, /* timing */ |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 475 | BUS_MASK_32BIT, /* Busses mask */ |
| 476 | MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ |
Moti Buskila | 498475e | 2021-02-19 17:11:19 +0100 | [diff] [blame] | 477 | NOT_COMBINED, /* ddr twin-die combined */ |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 478 | { {0} }, /* raw spd data */ |
| 479 | {0} /* timing parameters */ |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 480 | }; |
| 481 | |
Chris Packham | 1a07d21 | 2018-05-10 13:28:29 +1200 | [diff] [blame] | 482 | struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 483 | { |
Marek Behún | 77652c7 | 2019-05-02 16:53:33 +0200 | [diff] [blame] | 484 | if (omnia_get_ram_size_gb() == 2) |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 485 | return &board_topology_map_2g; |
Marek Behún | 77652c7 | 2019-05-02 16:53:33 +0200 | [diff] [blame] | 486 | else |
| 487 | return &board_topology_map_1g; |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 488 | } |
| 489 | |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 490 | static int set_regdomain(void) |
| 491 | { |
| 492 | struct omnia_eeprom oep; |
| 493 | char rd[3] = {' ', ' ', 0}; |
| 494 | |
| 495 | if (omnia_read_eeprom(&oep)) |
| 496 | memcpy(rd, &oep.region, 2); |
| 497 | else |
| 498 | puts("EEPROM regdomain read failed.\n"); |
| 499 | |
| 500 | printf("Regdomain set to %s\n", rd); |
Simon Glass | 6a38e41 | 2017-08-03 12:22:09 -0600 | [diff] [blame] | 501 | return env_set("regdomain", rd); |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 502 | } |
Marek Behún | 0f2e66a | 2019-05-02 16:53:37 +0200 | [diff] [blame] | 503 | |
Marek Behún | 0f2e66a | 2019-05-02 16:53:37 +0200 | [diff] [blame] | 504 | static void handle_reset_button(void) |
| 505 | { |
Pali Rohár | 905c3bf | 2021-06-14 16:45:58 +0200 | [diff] [blame] | 506 | const char * const vars[1] = { "bootcmd_rescue", }; |
Marek Behún | 0f2e66a | 2019-05-02 16:53:37 +0200 | [diff] [blame] | 507 | int ret; |
| 508 | u8 reset_status; |
| 509 | |
Pali Rohár | 905c3bf | 2021-06-14 16:45:58 +0200 | [diff] [blame] | 510 | /* |
| 511 | * Ensure that bootcmd_rescue has always stock value, so that running |
| 512 | * run bootcmd_rescue |
| 513 | * always works correctly. |
| 514 | */ |
| 515 | env_set_default_vars(1, (char * const *)vars, 0); |
| 516 | |
Marek Behún | 0f2e66a | 2019-05-02 16:53:37 +0200 | [diff] [blame] | 517 | ret = omnia_mcu_read(CMD_GET_RESET, &reset_status, 1); |
| 518 | if (ret) { |
| 519 | printf("omnia_mcu_read failed: %i, reset status unknown!\n", |
| 520 | ret); |
| 521 | return; |
| 522 | } |
| 523 | |
| 524 | env_set_ulong("omnia_reset", reset_status); |
| 525 | |
| 526 | if (reset_status) { |
Pali Rohár | 905c3bf | 2021-06-14 16:45:58 +0200 | [diff] [blame] | 527 | const char * const vars[2] = { |
Marek Behún | 09f8de2 | 2021-05-28 10:00:49 +0200 | [diff] [blame] | 528 | "bootcmd", |
Marek Behún | 09f8de2 | 2021-05-28 10:00:49 +0200 | [diff] [blame] | 529 | "distro_bootcmd", |
| 530 | }; |
| 531 | |
| 532 | /* |
| 533 | * Set the above envs to their default values, in case the user |
| 534 | * managed to break them. |
| 535 | */ |
Pali Rohár | 905c3bf | 2021-06-14 16:45:58 +0200 | [diff] [blame] | 536 | env_set_default_vars(2, (char * const *)vars, 0); |
Marek Behún | 09f8de2 | 2021-05-28 10:00:49 +0200 | [diff] [blame] | 537 | |
| 538 | /* Ensure bootcmd_rescue is used by distroboot */ |
| 539 | env_set("boot_targets", "rescue"); |
| 540 | |
Pali Rohár | 4f9e6fb | 2022-04-06 11:39:32 +0200 | [diff] [blame] | 541 | printf("RESET button was pressed, overwriting boot_targets!\n"); |
Marek Behún | 09f8de2 | 2021-05-28 10:00:49 +0200 | [diff] [blame] | 542 | } else { |
| 543 | /* |
| 544 | * In case the user somehow managed to save environment with |
| 545 | * boot_targets=rescue, reset boot_targets to default value. |
| 546 | * This could happen in subsequent commands if bootcmd_rescue |
| 547 | * failed. |
| 548 | */ |
| 549 | if (!strcmp(env_get("boot_targets"), "rescue")) { |
| 550 | const char * const vars[1] = { |
| 551 | "boot_targets", |
| 552 | }; |
| 553 | |
| 554 | env_set_default_vars(1, (char * const *)vars, 0); |
| 555 | } |
Marek Behún | 0f2e66a | 2019-05-02 16:53:37 +0200 | [diff] [blame] | 556 | } |
| 557 | } |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 558 | |
Pali Rohár | 1e0a975 | 2022-07-29 13:29:07 +0200 | [diff] [blame] | 559 | static void initialize_switch(void) |
| 560 | { |
| 561 | u32 val, val04, val08, val10, val14; |
| 562 | u16 ctrl[2]; |
| 563 | int err; |
| 564 | |
| 565 | printf("Initializing LAN eth switch... "); |
| 566 | |
| 567 | /* Change RGMII pins to GPIO mode */ |
| 568 | |
| 569 | val = val04 = readl(MVEBU_MPP_BASE + 0x04); |
| 570 | val &= ~GENMASK(19, 16); /* MPP[12] := GPIO */ |
| 571 | val &= ~GENMASK(23, 20); /* MPP[13] := GPIO */ |
| 572 | val &= ~GENMASK(27, 24); /* MPP[14] := GPIO */ |
| 573 | val &= ~GENMASK(31, 28); /* MPP[15] := GPIO */ |
| 574 | writel(val, MVEBU_MPP_BASE + 0x04); |
| 575 | |
| 576 | val = val08 = readl(MVEBU_MPP_BASE + 0x08); |
| 577 | val &= ~GENMASK(3, 0); /* MPP[16] := GPIO */ |
| 578 | val &= ~GENMASK(23, 20); /* MPP[21] := GPIO */ |
| 579 | writel(val, MVEBU_MPP_BASE + 0x08); |
| 580 | |
| 581 | val = val10 = readl(MVEBU_MPP_BASE + 0x10); |
| 582 | val &= ~GENMASK(27, 24); /* MPP[38] := GPIO */ |
| 583 | val &= ~GENMASK(31, 28); /* MPP[39] := GPIO */ |
| 584 | writel(val, MVEBU_MPP_BASE + 0x10); |
| 585 | |
| 586 | val = val14 = readl(MVEBU_MPP_BASE + 0x14); |
| 587 | val &= ~GENMASK(3, 0); /* MPP[40] := GPIO */ |
| 588 | val &= ~GENMASK(7, 4); /* MPP[41] := GPIO */ |
| 589 | writel(val, MVEBU_MPP_BASE + 0x14); |
| 590 | |
| 591 | /* Set initial values for switch reset strapping pins */ |
| 592 | |
| 593 | val = readl(MVEBU_GPIO0_BASE + 0x00); |
| 594 | val |= BIT(12); /* GPIO[12] := 1 */ |
| 595 | val |= BIT(13); /* GPIO[13] := 1 */ |
| 596 | val |= BIT(14); /* GPIO[14] := 1 */ |
| 597 | val |= BIT(15); /* GPIO[15] := 1 */ |
| 598 | val &= ~BIT(16); /* GPIO[16] := 0 */ |
| 599 | val |= BIT(21); /* GPIO[21] := 1 */ |
| 600 | writel(val, MVEBU_GPIO0_BASE + 0x00); |
| 601 | |
| 602 | val = readl(MVEBU_GPIO1_BASE + 0x00); |
| 603 | val |= BIT(6); /* GPIO[38] := 1 */ |
| 604 | val |= BIT(7); /* GPIO[39] := 1 */ |
| 605 | val |= BIT(8); /* GPIO[40] := 1 */ |
| 606 | val &= ~BIT(9); /* GPIO[41] := 0 */ |
| 607 | writel(val, MVEBU_GPIO1_BASE + 0x00); |
| 608 | |
| 609 | val = readl(MVEBU_GPIO0_BASE + 0x04); |
| 610 | val &= ~BIT(12); /* GPIO[12] := Out Enable */ |
| 611 | val &= ~BIT(13); /* GPIO[13] := Out Enable */ |
| 612 | val &= ~BIT(14); /* GPIO[14] := Out Enable */ |
| 613 | val &= ~BIT(15); /* GPIO[15] := Out Enable */ |
| 614 | val &= ~BIT(16); /* GPIO[16] := Out Enable */ |
| 615 | val &= ~BIT(21); /* GPIO[21] := Out Enable */ |
| 616 | writel(val, MVEBU_GPIO0_BASE + 0x04); |
| 617 | |
| 618 | val = readl(MVEBU_GPIO1_BASE + 0x04); |
| 619 | val &= ~BIT(6); /* GPIO[38] := Out Enable */ |
| 620 | val &= ~BIT(7); /* GPIO[39] := Out Enable */ |
| 621 | val &= ~BIT(8); /* GPIO[40] := Out Enable */ |
| 622 | val &= ~BIT(9); /* GPIO[41] := Out Enable */ |
| 623 | writel(val, MVEBU_GPIO1_BASE + 0x04); |
| 624 | |
| 625 | /* Release switch reset */ |
| 626 | |
| 627 | ctrl[0] = EXT_CTL_nRES_LAN; |
| 628 | ctrl[1] = EXT_CTL_nRES_LAN; |
| 629 | err = omnia_mcu_write(CMD_EXT_CONTROL, ctrl, sizeof(ctrl)); |
| 630 | |
| 631 | mdelay(10); |
| 632 | |
| 633 | /* Change RGMII pins back to RGMII mode */ |
| 634 | |
| 635 | writel(val04, MVEBU_MPP_BASE + 0x04); |
| 636 | writel(val08, MVEBU_MPP_BASE + 0x08); |
| 637 | writel(val10, MVEBU_MPP_BASE + 0x10); |
| 638 | writel(val14, MVEBU_MPP_BASE + 0x14); |
| 639 | |
| 640 | puts(err ? "failed\n" : "done\n"); |
| 641 | } |
| 642 | |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 643 | int board_early_init_f(void) |
| 644 | { |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 645 | /* Configure MPP */ |
| 646 | writel(0x11111111, MVEBU_MPP_BASE + 0x00); |
| 647 | writel(0x11111111, MVEBU_MPP_BASE + 0x04); |
| 648 | writel(0x11244011, MVEBU_MPP_BASE + 0x08); |
| 649 | writel(0x22222111, MVEBU_MPP_BASE + 0x0c); |
| 650 | writel(0x22200002, MVEBU_MPP_BASE + 0x10); |
| 651 | writel(0x30042022, MVEBU_MPP_BASE + 0x14); |
| 652 | writel(0x55550555, MVEBU_MPP_BASE + 0x18); |
| 653 | writel(0x00005550, MVEBU_MPP_BASE + 0x1c); |
| 654 | |
| 655 | /* Set GPP Out value */ |
| 656 | writel(OMNIA_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); |
| 657 | writel(OMNIA_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); |
| 658 | |
| 659 | /* Set GPP Polarity */ |
| 660 | writel(OMNIA_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); |
| 661 | writel(OMNIA_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); |
| 662 | |
| 663 | /* Set GPP Out Enable */ |
| 664 | writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); |
| 665 | writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); |
| 666 | |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 667 | return 0; |
| 668 | } |
| 669 | |
Marek Behún | f355616 | 2021-08-16 15:19:39 +0200 | [diff] [blame] | 670 | void spl_board_init(void) |
| 671 | { |
Pali Rohár | 1e0a975 | 2022-07-29 13:29:07 +0200 | [diff] [blame] | 672 | u16 val; |
| 673 | int ret; |
| 674 | |
Marek Behún | f355616 | 2021-08-16 15:19:39 +0200 | [diff] [blame] | 675 | /* |
| 676 | * If booting from UART, disable MCU watchdog in SPL, since uploading |
Pali Rohár | 7fcda0c | 2021-11-09 17:14:02 +0100 | [diff] [blame] | 677 | * U-Boot proper can take too much time and trigger it. Instead enable |
| 678 | * A385 watchdog with very high timeout (10 minutes) to prevent hangup. |
Marek Behún | f355616 | 2021-08-16 15:19:39 +0200 | [diff] [blame] | 679 | */ |
Pali Rohár | 7fcda0c | 2021-11-09 17:14:02 +0100 | [diff] [blame] | 680 | if (get_boot_device() == BOOT_DEVICE_UART) { |
| 681 | enable_a385_watchdog(10); |
Marek Behún | f355616 | 2021-08-16 15:19:39 +0200 | [diff] [blame] | 682 | disable_mcu_watchdog(); |
Pali Rohár | 7fcda0c | 2021-11-09 17:14:02 +0100 | [diff] [blame] | 683 | } |
Pali Rohár | 1e0a975 | 2022-07-29 13:29:07 +0200 | [diff] [blame] | 684 | |
| 685 | /* |
| 686 | * When MCU controls peripheral resets then release LAN eth switch from |
| 687 | * the reset and initialize it. When MCU does not control peripheral |
| 688 | * resets then LAN eth switch is initialized automatically by bootstrap |
| 689 | * pins when A385 is released from the reset. |
| 690 | */ |
| 691 | ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &val, sizeof(val)); |
| 692 | if (ret == 0 && (val & STS_FEATURES_SUPPORTED)) { |
| 693 | ret = omnia_mcu_read(CMD_GET_FEATURES, &val, sizeof(val)); |
| 694 | if (ret == 0 && (val & FEAT_PERIPH_MCU)) |
| 695 | initialize_switch(); |
| 696 | } |
Marek Behún | f355616 | 2021-08-16 15:19:39 +0200 | [diff] [blame] | 697 | } |
| 698 | |
Pali Rohár | cbda3e2 | 2022-01-10 11:47:18 +0100 | [diff] [blame] | 699 | #if IS_ENABLED(CONFIG_OF_BOARD_FIXUP) || IS_ENABLED(CONFIG_OF_BOARD_SETUP) |
| 700 | |
Pali Rohár | 7cd4173 | 2022-03-02 12:47:56 +0100 | [diff] [blame] | 701 | static void disable_sata_node(void *blob) |
Pali Rohár | cbda3e2 | 2022-01-10 11:47:18 +0100 | [diff] [blame] | 702 | { |
Pali Rohár | cbda3e2 | 2022-01-10 11:47:18 +0100 | [diff] [blame] | 703 | int node; |
| 704 | |
Pali Rohár | 7cd4173 | 2022-03-02 12:47:56 +0100 | [diff] [blame] | 705 | fdt_for_each_node_by_compatible(node, blob, -1, "marvell,armada-380-ahci") { |
| 706 | if (!fdtdec_get_is_enabled(blob, node)) |
| 707 | continue; |
| 708 | |
| 709 | if (fdt_status_disabled(blob, node) < 0) |
| 710 | printf("Cannot disable SATA DT node!\n"); |
| 711 | else |
| 712 | debug("Disabled SATA DT node\n"); |
| 713 | |
Pali Rohár | e910526 | 2022-03-02 12:47:57 +0100 | [diff] [blame] | 714 | return; |
Pali Rohár | 7cd4173 | 2022-03-02 12:47:56 +0100 | [diff] [blame] | 715 | } |
Pali Rohár | e910526 | 2022-03-02 12:47:57 +0100 | [diff] [blame] | 716 | |
| 717 | printf("Cannot find SATA DT node!\n"); |
Pali Rohár | 7cd4173 | 2022-03-02 12:47:56 +0100 | [diff] [blame] | 718 | } |
| 719 | |
| 720 | static void disable_pcie_node(void *blob, int port) |
| 721 | { |
| 722 | int node; |
| 723 | |
| 724 | fdt_for_each_node_by_compatible(node, blob, -1, "marvell,armada-370-pcie") { |
| 725 | int port_node; |
| 726 | |
| 727 | if (!fdtdec_get_is_enabled(blob, node)) |
| 728 | continue; |
| 729 | |
| 730 | fdt_for_each_subnode (port_node, blob, node) { |
| 731 | if (!fdtdec_get_is_enabled(blob, port_node)) |
| 732 | continue; |
| 733 | |
| 734 | if (fdtdec_get_int(blob, port_node, "marvell,pcie-port", -1) != port) |
| 735 | continue; |
| 736 | |
| 737 | if (fdt_status_disabled(blob, port_node) < 0) |
| 738 | printf("Cannot disable PCIe port %d DT node!\n", port); |
| 739 | else |
| 740 | debug("Disabled PCIe port %d DT node\n", port); |
| 741 | |
| 742 | return; |
| 743 | } |
| 744 | } |
Pali Rohár | e910526 | 2022-03-02 12:47:57 +0100 | [diff] [blame] | 745 | |
| 746 | printf("Cannot find PCIe port %d DT node!\n", port); |
Pali Rohár | 7cd4173 | 2022-03-02 12:47:56 +0100 | [diff] [blame] | 747 | } |
| 748 | |
| 749 | static void fixup_msata_port_nodes(void *blob) |
| 750 | { |
| 751 | bool mode_sata; |
| 752 | |
Pali Rohár | cbda3e2 | 2022-01-10 11:47:18 +0100 | [diff] [blame] | 753 | /* |
| 754 | * Determine if SerDes 0 is configured to SATA mode. |
| 755 | * We do this instead of calling omnia_detect_sata() to avoid another |
| 756 | * call to the MCU. By this time the common PHYs are initialized (it is |
| 757 | * done in SPL), so we can read this common PHY register. |
| 758 | */ |
| 759 | mode_sata = (readl(MVEBU_REGISTER(0x183fc)) & GENMASK(3, 0)) == 2; |
| 760 | |
| 761 | /* |
| 762 | * We're either adding status = "disabled" property, or changing |
| 763 | * status = "okay" to status = "disabled". In both cases we'll need more |
| 764 | * space. Increase the size a little. |
| 765 | */ |
| 766 | if (fdt_increase_size(blob, 32) < 0) { |
| 767 | printf("Cannot increase FDT size!\n"); |
| 768 | return; |
| 769 | } |
| 770 | |
Pali Rohár | cbda3e2 | 2022-01-10 11:47:18 +0100 | [diff] [blame] | 771 | if (!mode_sata) { |
Pali Rohár | 7cd4173 | 2022-03-02 12:47:56 +0100 | [diff] [blame] | 772 | /* If mSATA card is not present, disable SATA DT node */ |
| 773 | disable_sata_node(blob); |
| 774 | } else { |
| 775 | /* Otherwise disable PCIe port 0 DT node (MiniPCIe / mSATA port) */ |
| 776 | disable_pcie_node(blob, 0); |
Pali Rohár | cbda3e2 | 2022-01-10 11:47:18 +0100 | [diff] [blame] | 777 | } |
Pali Rohár | 93a89c5 | 2022-03-02 12:47:58 +0100 | [diff] [blame] | 778 | } |
| 779 | |
| 780 | static void fixup_wwan_port_nodes(void *blob) |
| 781 | { |
| 782 | bool mode_usb3; |
| 783 | |
| 784 | /* Determine if SerDes 4 is configured to USB3 mode */ |
| 785 | mode_usb3 = ((readl(MVEBU_REGISTER(0x183fc)) & GENMASK(19, 16)) >> 16) == 4; |
| 786 | |
| 787 | /* If SerDes 4 is not configured to USB3 mode then nothing is needed to fixup */ |
| 788 | if (!mode_usb3) |
| 789 | return; |
| 790 | |
| 791 | /* |
| 792 | * We're either adding status = "disabled" property, or changing |
| 793 | * status = "okay" to status = "disabled". In both cases we'll need more |
| 794 | * space. Increase the size a little. |
| 795 | */ |
| 796 | if (fdt_increase_size(blob, 32) < 0) { |
| 797 | printf("Cannot increase FDT size!\n"); |
| 798 | return; |
| 799 | } |
| 800 | |
| 801 | /* Disable PCIe port 2 DT node (WWAN) */ |
| 802 | disable_pcie_node(blob, 2); |
Pali Rohár | cbda3e2 | 2022-01-10 11:47:18 +0100 | [diff] [blame] | 803 | } |
| 804 | |
Pali Rohár | 1e0a975 | 2022-07-29 13:29:07 +0200 | [diff] [blame] | 805 | static int insert_mcu_gpio_prop(void *blob, int node, const char *prop, |
| 806 | unsigned int phandle, u32 bank, u32 gpio, |
| 807 | u32 flags) |
| 808 | { |
| 809 | fdt32_t val[4] = { cpu_to_fdt32(phandle), cpu_to_fdt32(bank), |
| 810 | cpu_to_fdt32(gpio), cpu_to_fdt32(flags) }; |
| 811 | return fdt_setprop(blob, node, prop, &val, sizeof(val)); |
| 812 | } |
| 813 | |
| 814 | static int fixup_mcu_gpio_in_pcie_nodes(void *blob) |
| 815 | { |
| 816 | unsigned int mcu_phandle; |
| 817 | int port, gpio; |
| 818 | int pcie_node; |
| 819 | int port_node; |
| 820 | int ret; |
| 821 | |
| 822 | ret = fdt_increase_size(blob, 128); |
| 823 | if (ret < 0) { |
| 824 | printf("Cannot increase FDT size!\n"); |
| 825 | return ret; |
| 826 | } |
| 827 | |
| 828 | mcu_phandle = fdt_create_phandle_by_compatible(blob, "cznic,turris-omnia-mcu"); |
| 829 | if (!mcu_phandle) |
| 830 | return -FDT_ERR_NOPHANDLES; |
| 831 | |
| 832 | fdt_for_each_node_by_compatible(pcie_node, blob, -1, "marvell,armada-370-pcie") { |
| 833 | if (!fdtdec_get_is_enabled(blob, pcie_node)) |
| 834 | continue; |
| 835 | |
| 836 | fdt_for_each_subnode(port_node, blob, pcie_node) { |
| 837 | if (!fdtdec_get_is_enabled(blob, port_node)) |
| 838 | continue; |
| 839 | |
| 840 | port = fdtdec_get_int(blob, port_node, "marvell,pcie-port", -1); |
| 841 | |
| 842 | if (port == 0) |
| 843 | gpio = ilog2(EXT_CTL_nPERST0); |
| 844 | else if (port == 1) |
| 845 | gpio = ilog2(EXT_CTL_nPERST1); |
| 846 | else if (port == 2) |
| 847 | gpio = ilog2(EXT_CTL_nPERST2); |
| 848 | else |
| 849 | continue; |
| 850 | |
| 851 | /* insert: reset-gpios = <&mcu 2 gpio GPIO_ACTIVE_LOW>; */ |
| 852 | ret = insert_mcu_gpio_prop(blob, port_node, "reset-gpios", |
| 853 | mcu_phandle, 2, gpio, GPIO_ACTIVE_LOW); |
| 854 | if (ret < 0) |
| 855 | return ret; |
| 856 | } |
| 857 | } |
| 858 | |
| 859 | return 0; |
| 860 | } |
| 861 | |
| 862 | static int fixup_mcu_gpio_in_eth_wan_node(void *blob) |
| 863 | { |
| 864 | unsigned int mcu_phandle; |
| 865 | int eth_wan_node; |
| 866 | int ret; |
| 867 | |
| 868 | ret = fdt_increase_size(blob, 64); |
| 869 | if (ret < 0) { |
| 870 | printf("Cannot increase FDT size!\n"); |
| 871 | return ret; |
| 872 | } |
| 873 | |
| 874 | eth_wan_node = fdt_path_offset(blob, "ethernet2"); |
| 875 | if (eth_wan_node < 0) |
| 876 | return eth_wan_node; |
| 877 | |
| 878 | mcu_phandle = fdt_create_phandle_by_compatible(blob, "cznic,turris-omnia-mcu"); |
| 879 | if (!mcu_phandle) |
| 880 | return -FDT_ERR_NOPHANDLES; |
| 881 | |
| 882 | /* insert: phy-reset-gpios = <&mcu 2 gpio GPIO_ACTIVE_LOW>; */ |
| 883 | ret = insert_mcu_gpio_prop(blob, eth_wan_node, "phy-reset-gpios", |
| 884 | mcu_phandle, 2, ilog2(EXT_CTL_nRES_PHY), GPIO_ACTIVE_LOW); |
| 885 | if (ret < 0) |
| 886 | return ret; |
| 887 | |
| 888 | return 0; |
| 889 | } |
| 890 | |
Pali Rohár | cbda3e2 | 2022-01-10 11:47:18 +0100 | [diff] [blame] | 891 | #endif |
| 892 | |
| 893 | #if IS_ENABLED(CONFIG_OF_BOARD_FIXUP) |
| 894 | int board_fix_fdt(void *blob) |
| 895 | { |
Pali Rohár | 1e0a975 | 2022-07-29 13:29:07 +0200 | [diff] [blame] | 896 | u16 val; |
| 897 | int ret; |
| 898 | |
| 899 | ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &val, sizeof(val)); |
| 900 | if (ret == 0 && (val & STS_FEATURES_SUPPORTED)) { |
| 901 | ret = omnia_mcu_read(CMD_GET_FEATURES, &val, sizeof(val)); |
| 902 | if (ret == 0 && (val & FEAT_PERIPH_MCU)) { |
| 903 | fixup_mcu_gpio_in_pcie_nodes(blob); |
| 904 | fixup_mcu_gpio_in_eth_wan_node(blob); |
| 905 | } |
| 906 | } |
| 907 | |
Pali Rohár | 7cd4173 | 2022-03-02 12:47:56 +0100 | [diff] [blame] | 908 | fixup_msata_port_nodes(blob); |
Pali Rohár | 93a89c5 | 2022-03-02 12:47:58 +0100 | [diff] [blame] | 909 | fixup_wwan_port_nodes(blob); |
Pali Rohár | cbda3e2 | 2022-01-10 11:47:18 +0100 | [diff] [blame] | 910 | |
| 911 | return 0; |
| 912 | } |
| 913 | #endif |
| 914 | |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 915 | int board_init(void) |
| 916 | { |
Marek Behún | 4dfc57e | 2019-05-02 16:53:31 +0200 | [diff] [blame] | 917 | /* address of boot parameters */ |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 918 | gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; |
| 919 | |
Marek Behún | 88dc024 | 2021-08-16 15:19:40 +0200 | [diff] [blame] | 920 | return 0; |
| 921 | } |
| 922 | |
| 923 | int board_late_init(void) |
| 924 | { |
Marek Behún | f355616 | 2021-08-16 15:19:39 +0200 | [diff] [blame] | 925 | /* |
| 926 | * If not booting from UART, MCU watchdog was not disabled in SPL, |
| 927 | * disable it now. |
| 928 | */ |
| 929 | if (get_boot_device() != BOOT_DEVICE_UART) |
| 930 | disable_mcu_watchdog(); |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 931 | |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 932 | set_regdomain(); |
Marek Behún | 0f2e66a | 2019-05-02 16:53:37 +0200 | [diff] [blame] | 933 | handle_reset_button(); |
Marek Behún | db1e5c6 | 2019-05-24 14:57:53 +0200 | [diff] [blame] | 934 | pci_init(); |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 935 | |
| 936 | return 0; |
| 937 | } |
| 938 | |
Marek Behún | ab9447f | 2021-10-09 19:33:44 +0200 | [diff] [blame] | 939 | int show_board_info(void) |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 940 | { |
| 941 | u32 version_num, serial_num; |
Pali Rohár | 0387f7f | 2022-04-08 16:30:12 +0200 | [diff] [blame] | 942 | int err; |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 943 | |
Pali Rohár | 0387f7f | 2022-04-08 16:30:12 +0200 | [diff] [blame] | 944 | err = turris_atsha_otp_get_serial_number(&version_num, &serial_num); |
Marek Behún | ab9447f | 2021-10-09 19:33:44 +0200 | [diff] [blame] | 945 | printf("Model: Turris Omnia\n"); |
Pali Rohár | 4798ba9 | 2022-07-29 13:29:06 +0200 | [diff] [blame] | 946 | printf(" MCU type: %s\n", omnia_get_mcu_type()); |
Marek Behún | c4ba72a | 2019-05-02 16:53:34 +0200 | [diff] [blame] | 947 | printf(" RAM size: %i MiB\n", omnia_get_ram_size_gb() * 1024); |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 948 | if (err) |
Marek Behún | c4ba72a | 2019-05-02 16:53:34 +0200 | [diff] [blame] | 949 | printf(" Serial Number: unknown\n"); |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 950 | else |
Marek Behún | c4ba72a | 2019-05-02 16:53:34 +0200 | [diff] [blame] | 951 | printf(" Serial Number: %08X%08X\n", be32_to_cpu(version_num), |
| 952 | be32_to_cpu(serial_num)); |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 953 | |
| 954 | return 0; |
| 955 | } |
| 956 | |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 957 | int misc_init_r(void) |
| 958 | { |
Pali Rohár | 60f37e8 | 2022-04-08 16:30:14 +0200 | [diff] [blame] | 959 | turris_atsha_otp_init_mac_addresses(1); |
Marek Behún | 09e16b8 | 2017-06-09 19:28:45 +0200 | [diff] [blame] | 960 | return 0; |
| 961 | } |
| 962 | |
Marek Behún | 91ef59c | 2021-07-15 19:21:02 +0200 | [diff] [blame] | 963 | #if defined(CONFIG_OF_BOARD_SETUP) |
| 964 | /* |
| 965 | * I plan to generalize this function and move it to common/fdt_support.c. |
| 966 | * This will require some more work on multiple boards, though, so for now leave |
| 967 | * it here. |
| 968 | */ |
| 969 | static bool fixup_mtd_partitions(void *blob, int offset, struct mtd_info *mtd) |
| 970 | { |
| 971 | struct mtd_info *slave; |
| 972 | int parts; |
| 973 | |
| 974 | parts = fdt_subnode_offset(blob, offset, "partitions"); |
Pali Rohár | e2b1ba0 | 2022-08-01 12:02:19 +0200 | [diff] [blame] | 975 | if (parts >= 0) { |
| 976 | if (fdt_del_node(blob, parts) < 0) |
| 977 | return false; |
| 978 | } |
Marek Behún | 91ef59c | 2021-07-15 19:21:02 +0200 | [diff] [blame] | 979 | |
Pali Rohár | d35b6f2 | 2022-08-01 12:02:20 +0200 | [diff] [blame] | 980 | if (fdt_increase_size(blob, 512) < 0) |
| 981 | return false; |
| 982 | |
Marek Behún | 91ef59c | 2021-07-15 19:21:02 +0200 | [diff] [blame] | 983 | parts = fdt_add_subnode(blob, offset, "partitions"); |
| 984 | if (parts < 0) |
| 985 | return false; |
| 986 | |
| 987 | if (fdt_setprop_u32(blob, parts, "#address-cells", 1) < 0) |
| 988 | return false; |
| 989 | |
| 990 | if (fdt_setprop_u32(blob, parts, "#size-cells", 1) < 0) |
| 991 | return false; |
| 992 | |
| 993 | if (fdt_setprop_string(blob, parts, "compatible", |
| 994 | "fixed-partitions") < 0) |
| 995 | return false; |
| 996 | |
| 997 | mtd_probe_devices(); |
| 998 | |
Pali Rohár | d8210ef | 2021-10-21 17:55:48 +0200 | [diff] [blame] | 999 | list_for_each_entry_reverse(slave, &mtd->partitions, node) { |
Marek Behún | 91ef59c | 2021-07-15 19:21:02 +0200 | [diff] [blame] | 1000 | char name[32]; |
| 1001 | int part; |
| 1002 | |
| 1003 | snprintf(name, sizeof(name), "partition@%llx", slave->offset); |
| 1004 | part = fdt_add_subnode(blob, parts, name); |
| 1005 | if (part < 0) |
| 1006 | return false; |
| 1007 | |
| 1008 | if (fdt_setprop_u32(blob, part, "reg", slave->offset) < 0) |
| 1009 | return false; |
| 1010 | |
| 1011 | if (fdt_appendprop_u32(blob, part, "reg", slave->size) < 0) |
| 1012 | return false; |
| 1013 | |
| 1014 | if (fdt_setprop_string(blob, part, "label", slave->name) < 0) |
| 1015 | return false; |
| 1016 | |
| 1017 | if (!(slave->flags & MTD_WRITEABLE)) |
| 1018 | if (fdt_setprop_empty(blob, part, "read-only") < 0) |
| 1019 | return false; |
| 1020 | |
| 1021 | if (slave->flags & MTD_POWERUP_LOCK) |
| 1022 | if (fdt_setprop_empty(blob, part, "lock") < 0) |
| 1023 | return false; |
| 1024 | } |
| 1025 | |
| 1026 | return true; |
| 1027 | } |
| 1028 | |
Pali Rohár | cbda3e2 | 2022-01-10 11:47:18 +0100 | [diff] [blame] | 1029 | static void fixup_spi_nor_partitions(void *blob) |
Marek Behún | 91ef59c | 2021-07-15 19:21:02 +0200 | [diff] [blame] | 1030 | { |
Pali Rohár | 3215c03 | 2022-08-01 23:58:42 +0200 | [diff] [blame] | 1031 | struct mtd_info *mtd = NULL; |
| 1032 | char mtd_path[64]; |
Marek Behún | 91ef59c | 2021-07-15 19:21:02 +0200 | [diff] [blame] | 1033 | int node; |
| 1034 | |
Pali Rohár | 3215c03 | 2022-08-01 23:58:42 +0200 | [diff] [blame] | 1035 | node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "jedec,spi-nor"); |
| 1036 | if (node < 0) |
| 1037 | goto fail; |
| 1038 | |
| 1039 | if (fdt_get_path(gd->fdt_blob, node, mtd_path, sizeof(mtd_path)) < 0) |
| 1040 | goto fail; |
| 1041 | |
| 1042 | mtd = get_mtd_device_nm(mtd_path); |
Marek Behún | 91ef59c | 2021-07-15 19:21:02 +0200 | [diff] [blame] | 1043 | if (IS_ERR_OR_NULL(mtd)) |
| 1044 | goto fail; |
| 1045 | |
Pali Rohár | 3215c03 | 2022-08-01 23:58:42 +0200 | [diff] [blame] | 1046 | node = fdt_node_offset_by_compatible(blob, -1, "jedec,spi-nor"); |
Marek Behún | 91ef59c | 2021-07-15 19:21:02 +0200 | [diff] [blame] | 1047 | if (node < 0) |
| 1048 | goto fail; |
| 1049 | |
| 1050 | if (!fixup_mtd_partitions(blob, node, mtd)) |
| 1051 | goto fail; |
| 1052 | |
Marek Behún | 36feac9 | 2021-09-25 02:49:18 +0200 | [diff] [blame] | 1053 | put_mtd_device(mtd); |
Pali Rohár | cbda3e2 | 2022-01-10 11:47:18 +0100 | [diff] [blame] | 1054 | return; |
Marek Behún | 91ef59c | 2021-07-15 19:21:02 +0200 | [diff] [blame] | 1055 | |
| 1056 | fail: |
| 1057 | printf("Failed fixing SPI NOR partitions!\n"); |
Marek Behún | 36feac9 | 2021-09-25 02:49:18 +0200 | [diff] [blame] | 1058 | if (!IS_ERR_OR_NULL(mtd)) |
| 1059 | put_mtd_device(mtd); |
Pali Rohár | cbda3e2 | 2022-01-10 11:47:18 +0100 | [diff] [blame] | 1060 | } |
| 1061 | |
| 1062 | int ft_board_setup(void *blob, struct bd_info *bd) |
| 1063 | { |
Pali Rohár | 1e0a975 | 2022-07-29 13:29:07 +0200 | [diff] [blame] | 1064 | int node; |
| 1065 | |
| 1066 | /* |
| 1067 | * U-Boot's FDT blob contains phy-reset-gpios in ethernet2 |
| 1068 | * node when MCU controls all peripherals resets. |
| 1069 | * Fixup MCU GPIO nodes in PCIe and eth wan nodes in this case. |
| 1070 | */ |
| 1071 | node = fdt_path_offset(gd->fdt_blob, "ethernet2"); |
| 1072 | if (node >= 0 && fdt_getprop(gd->fdt_blob, node, "phy-reset-gpios", NULL)) { |
| 1073 | fixup_mcu_gpio_in_pcie_nodes(blob); |
| 1074 | fixup_mcu_gpio_in_eth_wan_node(blob); |
| 1075 | } |
| 1076 | |
Pali Rohár | cbda3e2 | 2022-01-10 11:47:18 +0100 | [diff] [blame] | 1077 | fixup_spi_nor_partitions(blob); |
Pali Rohár | 7cd4173 | 2022-03-02 12:47:56 +0100 | [diff] [blame] | 1078 | fixup_msata_port_nodes(blob); |
Pali Rohár | 93a89c5 | 2022-03-02 12:47:58 +0100 | [diff] [blame] | 1079 | fixup_wwan_port_nodes(blob); |
Pali Rohár | cbda3e2 | 2022-01-10 11:47:18 +0100 | [diff] [blame] | 1080 | |
Marek Behún | 91ef59c | 2021-07-15 19:21:02 +0200 | [diff] [blame] | 1081 | return 0; |
| 1082 | } |
| 1083 | #endif |