blob: 25902742e3d3fc6ad99e826ff58e0e3e1def51f1 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Marek Behún09e16b82017-06-09 19:28:45 +02002/*
3 * Copyright (C) 2017 Marek Behun <marek.behun@nic.cz>
4 * Copyright (C) 2016 Tomas Hlavacek <tomas.hlavacek@nic.cz>
5 *
6 * Derived from the code for
7 * Marvell/db-88f6820-gp by Stefan Roese <sr@denx.de>
Marek Behún09e16b82017-06-09 19:28:45 +02008 */
9
10#include <common.h>
Simon Glass07dc93c2019-08-01 09:46:47 -060011#include <env.h>
Marek Behún09e16b82017-06-09 19:28:45 +020012#include <i2c.h>
Simon Glassa7b51302019-11-14 12:57:46 -070013#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060014#include <log.h>
Marek Behún09e16b82017-06-09 19:28:45 +020015#include <miiphy.h>
Marek Behún91ef59c2021-07-15 19:21:02 +020016#include <mtd.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060017#include <asm/global_data.h>
Marek Behún09e16b82017-06-09 19:28:45 +020018#include <asm/io.h>
19#include <asm/arch/cpu.h>
20#include <asm/arch/soc.h>
21#include <dm/uclass.h>
22#include <fdt_support.h>
23#include <time.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060024#include <linux/bitops.h>
Simon Glass48b6c6b2019-11-14 12:57:16 -070025#include <u-boot/crc.h>
Marek Behún09e16b82017-06-09 19:28:45 +020026
Chris Packham1a07d212018-05-10 13:28:29 +120027#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
Marek Behún09e16b82017-06-09 19:28:45 +020028#include <../serdes/a38x/high_speed_env_spec.h>
Pali Rohár0387f7f2022-04-08 16:30:12 +020029#include "../turris_atsha_otp.h"
Marek Behún09e16b82017-06-09 19:28:45 +020030
31DECLARE_GLOBAL_DATA_PTR;
32
Marek Behún91ef59c2021-07-15 19:21:02 +020033#define OMNIA_SPI_NOR_PATH "/soc/spi@10600/spi-nor@0"
34
Marek Behúnba53b6b2019-05-02 16:53:30 +020035#define OMNIA_I2C_BUS_NAME "i2c@11000->i2cmux@70->i2c@0"
36
37#define OMNIA_I2C_MCU_CHIP_ADDR 0x2a
38#define OMNIA_I2C_MCU_CHIP_LEN 1
39
40#define OMNIA_I2C_EEPROM_CHIP_ADDR 0x54
41#define OMNIA_I2C_EEPROM_CHIP_LEN 2
Marek Behún09e16b82017-06-09 19:28:45 +020042#define OMNIA_I2C_EEPROM_MAGIC 0x0341a034
43
Pali Rohár7fcda0c2021-11-09 17:14:02 +010044#define SYS_RSTOUT_MASK MVEBU_REGISTER(0x18260)
45#define SYS_RSTOUT_MASK_WD BIT(10)
46
47#define A385_WDT_GLOBAL_CTRL MVEBU_REGISTER(0x20300)
48#define A385_WDT_GLOBAL_RATIO_MASK GENMASK(18, 16)
49#define A385_WDT_GLOBAL_RATIO_SHIFT 16
50#define A385_WDT_GLOBAL_25MHZ BIT(10)
51#define A385_WDT_GLOBAL_ENABLE BIT(8)
52
53#define A385_WDT_GLOBAL_STATUS MVEBU_REGISTER(0x20304)
54#define A385_WDT_GLOBAL_EXPIRED BIT(31)
55
56#define A385_WDT_DURATION MVEBU_REGISTER(0x20334)
57
58#define A385_WD_RSTOUT_UNMASK MVEBU_REGISTER(0x20704)
59#define A385_WD_RSTOUT_UNMASK_GLOBAL BIT(8)
60
Marek Behúnba53b6b2019-05-02 16:53:30 +020061enum mcu_commands {
62 CMD_GET_STATUS_WORD = 0x01,
63 CMD_GET_RESET = 0x09,
64 CMD_WATCHDOG_STATE = 0x0b,
65};
66
67enum status_word_bits {
68 CARD_DET_STSBIT = 0x0010,
69 MSATA_IND_STSBIT = 0x0020,
70};
Marek Behún09e16b82017-06-09 19:28:45 +020071
Marek Behún09e16b82017-06-09 19:28:45 +020072/*
73 * Those values and defines are taken from the Marvell U-Boot version
74 * "u-boot-2013.01-2014_T3.0"
75 */
76#define OMNIA_GPP_OUT_ENA_LOW \
77 (~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \
78 BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \
79 BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
80#define OMNIA_GPP_OUT_ENA_MID \
81 (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \
82 BIT(16) | BIT(17) | BIT(18)))
83
84#define OMNIA_GPP_OUT_VAL_LOW 0x0
85#define OMNIA_GPP_OUT_VAL_MID 0x0
86#define OMNIA_GPP_POL_LOW 0x0
87#define OMNIA_GPP_POL_MID 0x0
88
Pali Rohár3c4dd982022-03-02 12:47:54 +010089static struct serdes_map board_serdes_map[] = {
Marek Behún09e16b82017-06-09 19:28:45 +020090 {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
91 {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
92 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
93 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
94 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
95 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
96};
97
Marek Behúnba53b6b2019-05-02 16:53:30 +020098static struct udevice *omnia_get_i2c_chip(const char *name, uint addr,
99 uint offset_len)
Marek Behún09e16b82017-06-09 19:28:45 +0200100{
101 struct udevice *bus, *dev;
Marek Behúnba53b6b2019-05-02 16:53:30 +0200102 int ret;
Marek Behún09e16b82017-06-09 19:28:45 +0200103
Marek Behúnba53b6b2019-05-02 16:53:30 +0200104 ret = uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_BUS_NAME, &bus);
105 if (ret) {
106 printf("Cannot get I2C bus %s: uclass_get_device_by_name failed: %i\n",
107 OMNIA_I2C_BUS_NAME, ret);
108 return NULL;
Marek Behún09e16b82017-06-09 19:28:45 +0200109 }
110
Marek Behúnba53b6b2019-05-02 16:53:30 +0200111 ret = i2c_get_chip(bus, addr, offset_len, &dev);
Marek Behún09e16b82017-06-09 19:28:45 +0200112 if (ret) {
Marek Behúnba53b6b2019-05-02 16:53:30 +0200113 printf("Cannot get %s I2C chip: i2c_get_chip failed: %i\n",
114 name, ret);
115 return NULL;
Marek Behún09e16b82017-06-09 19:28:45 +0200116 }
117
Marek Behúnba53b6b2019-05-02 16:53:30 +0200118 return dev;
119}
Marek Behúnd0b374d2017-08-04 15:28:25 +0200120
Marek Behúnba53b6b2019-05-02 16:53:30 +0200121static int omnia_mcu_read(u8 cmd, void *buf, int len)
122{
123 struct udevice *chip;
124
125 chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
126 OMNIA_I2C_MCU_CHIP_LEN);
127 if (!chip)
128 return -ENODEV;
129
130 return dm_i2c_read(chip, cmd, buf, len);
131}
132
Marek Behúnba53b6b2019-05-02 16:53:30 +0200133static int omnia_mcu_write(u8 cmd, const void *buf, int len)
134{
135 struct udevice *chip;
136
137 chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
138 OMNIA_I2C_MCU_CHIP_LEN);
139 if (!chip)
140 return -ENODEV;
141
142 return dm_i2c_write(chip, cmd, buf, len);
143}
144
Pali Rohár7fcda0c2021-11-09 17:14:02 +0100145static void enable_a385_watchdog(unsigned int timeout_minutes)
146{
147 struct sar_freq_modes sar_freq;
148 u32 watchdog_freq;
149
150 printf("Enabling A385 watchdog with %u minutes timeout...\n",
151 timeout_minutes);
152
153 /*
154 * Use NBCLK clock (a.k.a. L2 clock) as watchdog input clock with
155 * its maximal ratio 7 instead of default fixed 25 MHz clock.
156 * It allows to set watchdog duration up to the 22 minutes.
157 */
158 clrsetbits_32(A385_WDT_GLOBAL_CTRL,
159 A385_WDT_GLOBAL_25MHZ | A385_WDT_GLOBAL_RATIO_MASK,
160 7 << A385_WDT_GLOBAL_RATIO_SHIFT);
161
162 /*
163 * Calculate watchdog clock frequency. It is defined by formula:
164 * freq = NBCLK / 2 / (2 ^ ratio)
165 * We set ratio to the maximal possible value 7.
166 */
167 get_sar_freq(&sar_freq);
168 watchdog_freq = sar_freq.nb_clk * 1000000 / 2 / (1 << 7);
169
170 /* Set watchdog duration */
171 writel(timeout_minutes * 60 * watchdog_freq, A385_WDT_DURATION);
172
173 /* Clear the watchdog expiration bit */
174 clrbits_32(A385_WDT_GLOBAL_STATUS, A385_WDT_GLOBAL_EXPIRED);
175
176 /* Enable watchdog timer */
177 setbits_32(A385_WDT_GLOBAL_CTRL, A385_WDT_GLOBAL_ENABLE);
178
179 /* Enable reset on watchdog */
180 setbits_32(A385_WD_RSTOUT_UNMASK, A385_WD_RSTOUT_UNMASK_GLOBAL);
181
182 /* Unmask reset for watchdog */
183 clrbits_32(SYS_RSTOUT_MASK, SYS_RSTOUT_MASK_WD);
184}
185
Marek Behúnba53b6b2019-05-02 16:53:30 +0200186static bool disable_mcu_watchdog(void)
187{
188 int ret;
189
190 puts("Disabling MCU watchdog... ");
191
192 ret = omnia_mcu_write(CMD_WATCHDOG_STATE, "\x00", 1);
193 if (ret) {
194 printf("omnia_mcu_write failed: %i\n", ret);
Marek Behún09e16b82017-06-09 19:28:45 +0200195 return false;
196 }
197
Marek Behúnba53b6b2019-05-02 16:53:30 +0200198 puts("disabled\n");
199
200 return true;
201}
Marek Behúnba53b6b2019-05-02 16:53:30 +0200202
203static bool omnia_detect_sata(void)
204{
205 int ret;
206 u16 stsword;
207
208 puts("MiniPCIe/mSATA card detection... ");
209
210 ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &stsword, sizeof(stsword));
211 if (ret) {
212 printf("omnia_mcu_read failed: %i, defaulting to MiniPCIe card\n",
213 ret);
Marek Behún09e16b82017-06-09 19:28:45 +0200214 return false;
215 }
216
Marek Behúnba53b6b2019-05-02 16:53:30 +0200217 if (!(stsword & CARD_DET_STSBIT)) {
218 puts("none\n");
Marek Behún09e16b82017-06-09 19:28:45 +0200219 return false;
220 }
Marek Behúnba53b6b2019-05-02 16:53:30 +0200221
222 if (stsword & MSATA_IND_STSBIT)
223 puts("mSATA\n");
224 else
225 puts("MiniPCIe\n");
226
227 return stsword & MSATA_IND_STSBIT ? true : false;
Marek Behún09e16b82017-06-09 19:28:45 +0200228}
229
Pali Rohárc13401b2022-03-02 12:47:52 +0100230void *env_sf_get_env_addr(void)
231{
232 /* SPI Flash is mapped to address 0xD4000000 only in SPL */
233#ifdef CONFIG_SPL_BUILD
234 return (void *)0xD4000000 + CONFIG_ENV_OFFSET;
235#else
236 return NULL;
237#endif
238}
239
Marek Behún09e16b82017-06-09 19:28:45 +0200240int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
241{
242 if (omnia_detect_sata()) {
Pali Rohár3c4dd982022-03-02 12:47:54 +0100243 /* Change SerDes for first mPCIe port (mSATA) from PCIe to SATA */
244 board_serdes_map[0].serdes_type = SATA0;
245 board_serdes_map[0].serdes_speed = SERDES_SPEED_6_GBPS;
246 board_serdes_map[0].serdes_mode = SERDES_DEFAULT_MODE;
Marek Behún09e16b82017-06-09 19:28:45 +0200247 }
248
Pali Rohár3c4dd982022-03-02 12:47:54 +0100249 *serdes_map_array = board_serdes_map;
250 *count = ARRAY_SIZE(board_serdes_map);
251
Marek Behún09e16b82017-06-09 19:28:45 +0200252 return 0;
253}
254
255struct omnia_eeprom {
256 u32 magic;
257 u32 ramsize;
258 char region[4];
259 u32 crc;
260};
261
262static bool omnia_read_eeprom(struct omnia_eeprom *oep)
263{
Marek Behúnba53b6b2019-05-02 16:53:30 +0200264 struct udevice *chip;
265 u32 crc;
266 int ret;
Marek Behún09e16b82017-06-09 19:28:45 +0200267
Marek Behúnba53b6b2019-05-02 16:53:30 +0200268 chip = omnia_get_i2c_chip("EEPROM", OMNIA_I2C_EEPROM_CHIP_ADDR,
269 OMNIA_I2C_EEPROM_CHIP_LEN);
270
271 if (!chip)
Marek Behún09e16b82017-06-09 19:28:45 +0200272 return false;
Marek Behún09e16b82017-06-09 19:28:45 +0200273
Marek Behúnba53b6b2019-05-02 16:53:30 +0200274 ret = dm_i2c_read(chip, 0, (void *)oep, sizeof(*oep));
Marek Behún09e16b82017-06-09 19:28:45 +0200275 if (ret) {
Marek Behúnba53b6b2019-05-02 16:53:30 +0200276 printf("dm_i2c_read failed: %i, cannot read EEPROM\n", ret);
Marek Behún09e16b82017-06-09 19:28:45 +0200277 return false;
278 }
279
Marek Behúnba53b6b2019-05-02 16:53:30 +0200280 if (oep->magic != OMNIA_I2C_EEPROM_MAGIC) {
281 printf("bad EEPROM magic number (%08x, should be %08x)\n",
282 oep->magic, OMNIA_I2C_EEPROM_MAGIC);
283 return false;
Marek Behún09e16b82017-06-09 19:28:45 +0200284 }
285
Marek Behúnba53b6b2019-05-02 16:53:30 +0200286 crc = crc32(0, (void *)oep, sizeof(*oep) - 4);
287 if (crc != oep->crc) {
288 printf("bad EEPROM CRC (stored %08x, computed %08x)\n",
289 oep->crc, crc);
Marek Behún09e16b82017-06-09 19:28:45 +0200290 return false;
291 }
292
293 return true;
294}
295
Marek Behún77652c72019-05-02 16:53:33 +0200296static int omnia_get_ram_size_gb(void)
297{
298 static int ram_size;
299 struct omnia_eeprom oep;
300
301 if (!ram_size) {
302 /* Get the board config from EEPROM */
303 if (omnia_read_eeprom(&oep)) {
304 debug("Memory config in EEPROM: 0x%02x\n", oep.ramsize);
305
306 if (oep.ramsize == 0x2)
307 ram_size = 2;
308 else
309 ram_size = 1;
310 } else {
311 /* Hardcoded fallback */
312 puts("Memory config from EEPROM read failed!\n");
313 puts("Falling back to default 1 GiB!\n");
314 ram_size = 1;
315 }
316 }
317
318 return ram_size;
319}
320
Marek Behún09e16b82017-06-09 19:28:45 +0200321/*
322 * Define the DDR layout / topology here in the board file. This will
323 * be used by the DDR3 init code in the SPL U-Boot version to configure
324 * the DDR3 controller.
325 */
Chris Packham1a07d212018-05-10 13:28:29 +1200326static struct mv_ddr_topology_map board_topology_map_1g = {
327 DEBUG_LEVEL_ERROR,
Marek Behún09e16b82017-06-09 19:28:45 +0200328 0x1, /* active interfaces */
329 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
330 { { { {0x1, 0, 0, 0},
331 {0x1, 0, 0, 0},
332 {0x1, 0, 0, 0},
333 {0x1, 0, 0, 0},
334 {0x1, 0, 0, 0} },
335 SPEED_BIN_DDR_1600K, /* speed_bin */
Chris Packham1a07d212018-05-10 13:28:29 +1200336 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
337 MV_DDR_DIE_CAP_4GBIT, /* mem_size */
Chris Packham4bf81db2018-12-03 14:26:49 +1300338 MV_DDR_FREQ_800, /* frequency */
Chris Packhamdd092bd2017-11-29 10:38:34 +1300339 0, 0, /* cas_wl cas_l */
Chris Packham3a09e132018-05-10 13:28:30 +1200340 MV_DDR_TEMP_NORMAL, /* temperature */
341 MV_DDR_TIM_2T} }, /* timing */
Chris Packham1a07d212018-05-10 13:28:29 +1200342 BUS_MASK_32BIT, /* Busses mask */
343 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
Moti Buskila498475e2021-02-19 17:11:19 +0100344 NOT_COMBINED, /* ddr twin-die combined */
Chris Packham1a07d212018-05-10 13:28:29 +1200345 { {0} }, /* raw spd data */
346 {0} /* timing parameters */
Marek Behún09e16b82017-06-09 19:28:45 +0200347};
348
Chris Packham1a07d212018-05-10 13:28:29 +1200349static struct mv_ddr_topology_map board_topology_map_2g = {
350 DEBUG_LEVEL_ERROR,
Marek Behún09e16b82017-06-09 19:28:45 +0200351 0x1, /* active interfaces */
352 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
353 { { { {0x1, 0, 0, 0},
354 {0x1, 0, 0, 0},
355 {0x1, 0, 0, 0},
356 {0x1, 0, 0, 0},
357 {0x1, 0, 0, 0} },
358 SPEED_BIN_DDR_1600K, /* speed_bin */
Chris Packham1a07d212018-05-10 13:28:29 +1200359 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
360 MV_DDR_DIE_CAP_8GBIT, /* mem_size */
Chris Packham4bf81db2018-12-03 14:26:49 +1300361 MV_DDR_FREQ_800, /* frequency */
Chris Packhamdd092bd2017-11-29 10:38:34 +1300362 0, 0, /* cas_wl cas_l */
Chris Packham3a09e132018-05-10 13:28:30 +1200363 MV_DDR_TEMP_NORMAL, /* temperature */
364 MV_DDR_TIM_2T} }, /* timing */
Chris Packham1a07d212018-05-10 13:28:29 +1200365 BUS_MASK_32BIT, /* Busses mask */
366 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
Moti Buskila498475e2021-02-19 17:11:19 +0100367 NOT_COMBINED, /* ddr twin-die combined */
Chris Packham1a07d212018-05-10 13:28:29 +1200368 { {0} }, /* raw spd data */
369 {0} /* timing parameters */
Marek Behún09e16b82017-06-09 19:28:45 +0200370};
371
Chris Packham1a07d212018-05-10 13:28:29 +1200372struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
Marek Behún09e16b82017-06-09 19:28:45 +0200373{
Marek Behún77652c72019-05-02 16:53:33 +0200374 if (omnia_get_ram_size_gb() == 2)
Marek Behún09e16b82017-06-09 19:28:45 +0200375 return &board_topology_map_2g;
Marek Behún77652c72019-05-02 16:53:33 +0200376 else
377 return &board_topology_map_1g;
Marek Behún09e16b82017-06-09 19:28:45 +0200378}
379
Marek Behún09e16b82017-06-09 19:28:45 +0200380static int set_regdomain(void)
381{
382 struct omnia_eeprom oep;
383 char rd[3] = {' ', ' ', 0};
384
385 if (omnia_read_eeprom(&oep))
386 memcpy(rd, &oep.region, 2);
387 else
388 puts("EEPROM regdomain read failed.\n");
389
390 printf("Regdomain set to %s\n", rd);
Simon Glass6a38e412017-08-03 12:22:09 -0600391 return env_set("regdomain", rd);
Marek Behún09e16b82017-06-09 19:28:45 +0200392}
Marek Behún0f2e66a2019-05-02 16:53:37 +0200393
Marek Behún0f2e66a2019-05-02 16:53:37 +0200394static void handle_reset_button(void)
395{
Pali Rohár905c3bf2021-06-14 16:45:58 +0200396 const char * const vars[1] = { "bootcmd_rescue", };
Marek Behún0f2e66a2019-05-02 16:53:37 +0200397 int ret;
398 u8 reset_status;
399
Pali Rohár905c3bf2021-06-14 16:45:58 +0200400 /*
401 * Ensure that bootcmd_rescue has always stock value, so that running
402 * run bootcmd_rescue
403 * always works correctly.
404 */
405 env_set_default_vars(1, (char * const *)vars, 0);
406
Marek Behún0f2e66a2019-05-02 16:53:37 +0200407 ret = omnia_mcu_read(CMD_GET_RESET, &reset_status, 1);
408 if (ret) {
409 printf("omnia_mcu_read failed: %i, reset status unknown!\n",
410 ret);
411 return;
412 }
413
414 env_set_ulong("omnia_reset", reset_status);
415
416 if (reset_status) {
Pali Rohár905c3bf2021-06-14 16:45:58 +0200417 const char * const vars[2] = {
Marek Behún09f8de22021-05-28 10:00:49 +0200418 "bootcmd",
Marek Behún09f8de22021-05-28 10:00:49 +0200419 "distro_bootcmd",
420 };
421
422 /*
423 * Set the above envs to their default values, in case the user
424 * managed to break them.
425 */
Pali Rohár905c3bf2021-06-14 16:45:58 +0200426 env_set_default_vars(2, (char * const *)vars, 0);
Marek Behún09f8de22021-05-28 10:00:49 +0200427
428 /* Ensure bootcmd_rescue is used by distroboot */
429 env_set("boot_targets", "rescue");
430
Marek Behún0f2e66a2019-05-02 16:53:37 +0200431 printf("RESET button was pressed, overwriting bootcmd!\n");
Marek Behún09f8de22021-05-28 10:00:49 +0200432 } else {
433 /*
434 * In case the user somehow managed to save environment with
435 * boot_targets=rescue, reset boot_targets to default value.
436 * This could happen in subsequent commands if bootcmd_rescue
437 * failed.
438 */
439 if (!strcmp(env_get("boot_targets"), "rescue")) {
440 const char * const vars[1] = {
441 "boot_targets",
442 };
443
444 env_set_default_vars(1, (char * const *)vars, 0);
445 }
Marek Behún0f2e66a2019-05-02 16:53:37 +0200446 }
447}
Marek Behún09e16b82017-06-09 19:28:45 +0200448
449int board_early_init_f(void)
450{
Marek Behún09e16b82017-06-09 19:28:45 +0200451 /* Configure MPP */
452 writel(0x11111111, MVEBU_MPP_BASE + 0x00);
453 writel(0x11111111, MVEBU_MPP_BASE + 0x04);
454 writel(0x11244011, MVEBU_MPP_BASE + 0x08);
455 writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
456 writel(0x22200002, MVEBU_MPP_BASE + 0x10);
457 writel(0x30042022, MVEBU_MPP_BASE + 0x14);
458 writel(0x55550555, MVEBU_MPP_BASE + 0x18);
459 writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
460
461 /* Set GPP Out value */
462 writel(OMNIA_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
463 writel(OMNIA_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
464
465 /* Set GPP Polarity */
466 writel(OMNIA_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
467 writel(OMNIA_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
468
469 /* Set GPP Out Enable */
470 writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
471 writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
472
Marek Behún09e16b82017-06-09 19:28:45 +0200473 return 0;
474}
475
Marek Behúnf3556162021-08-16 15:19:39 +0200476void spl_board_init(void)
477{
478 /*
479 * If booting from UART, disable MCU watchdog in SPL, since uploading
Pali Rohár7fcda0c2021-11-09 17:14:02 +0100480 * U-Boot proper can take too much time and trigger it. Instead enable
481 * A385 watchdog with very high timeout (10 minutes) to prevent hangup.
Marek Behúnf3556162021-08-16 15:19:39 +0200482 */
Pali Rohár7fcda0c2021-11-09 17:14:02 +0100483 if (get_boot_device() == BOOT_DEVICE_UART) {
484 enable_a385_watchdog(10);
Marek Behúnf3556162021-08-16 15:19:39 +0200485 disable_mcu_watchdog();
Pali Rohár7fcda0c2021-11-09 17:14:02 +0100486 }
Marek Behúnf3556162021-08-16 15:19:39 +0200487}
488
Pali Rohárcbda3e22022-01-10 11:47:18 +0100489#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP) || IS_ENABLED(CONFIG_OF_BOARD_SETUP)
490
491static void fixup_serdes_0_nodes(void *blob)
492{
493 bool mode_sata;
494 int node;
495
496 /*
497 * Determine if SerDes 0 is configured to SATA mode.
498 * We do this instead of calling omnia_detect_sata() to avoid another
499 * call to the MCU. By this time the common PHYs are initialized (it is
500 * done in SPL), so we can read this common PHY register.
501 */
502 mode_sata = (readl(MVEBU_REGISTER(0x183fc)) & GENMASK(3, 0)) == 2;
503
504 /*
505 * We're either adding status = "disabled" property, or changing
506 * status = "okay" to status = "disabled". In both cases we'll need more
507 * space. Increase the size a little.
508 */
509 if (fdt_increase_size(blob, 32) < 0) {
510 printf("Cannot increase FDT size!\n");
511 return;
512 }
513
514 /* If mSATA card is not present, disable SATA DT node */
515 if (!mode_sata) {
516 fdt_for_each_node_by_compatible(node, blob, -1,
517 "marvell,armada-380-ahci") {
518 if (!fdtdec_get_is_enabled(blob, node))
519 continue;
520
521 if (fdt_status_disabled(blob, node) < 0)
522 printf("Cannot disable SATA DT node!\n");
523 else
524 debug("Disabled SATA DT node\n");
525
526 break;
527 }
528
529 return;
530 }
531
532 /* Otherwise disable PCIe port 0 DT node (MiniPCIe / mSATA port) */
533 fdt_for_each_node_by_compatible(node, blob, -1,
534 "marvell,armada-370-pcie") {
535 int port;
536
537 if (!fdtdec_get_is_enabled(blob, node))
538 continue;
539
540 fdt_for_each_subnode (port, blob, node) {
541 if (!fdtdec_get_is_enabled(blob, port))
542 continue;
543
544 if (fdtdec_get_int(blob, port, "marvell,pcie-port",
545 -1) != 0)
546 continue;
547
548 if (fdt_status_disabled(blob, port) < 0)
549 printf("Cannot disable PCIe port 0 DT node!\n");
550 else
551 debug("Disabled PCIe port 0 DT node\n");
552
553 return;
554 }
555 }
556}
557
558#endif
559
560#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP)
561int board_fix_fdt(void *blob)
562{
563 fixup_serdes_0_nodes(blob);
564
565 return 0;
566}
567#endif
568
Marek Behún09e16b82017-06-09 19:28:45 +0200569int board_init(void)
570{
Marek Behún4dfc57e2019-05-02 16:53:31 +0200571 /* address of boot parameters */
Marek Behún09e16b82017-06-09 19:28:45 +0200572 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
573
Marek Behún88dc0242021-08-16 15:19:40 +0200574 return 0;
575}
576
577int board_late_init(void)
578{
Marek Behúnf3556162021-08-16 15:19:39 +0200579 /*
580 * If not booting from UART, MCU watchdog was not disabled in SPL,
581 * disable it now.
582 */
583 if (get_boot_device() != BOOT_DEVICE_UART)
584 disable_mcu_watchdog();
Marek Behún09e16b82017-06-09 19:28:45 +0200585
Marek Behún09e16b82017-06-09 19:28:45 +0200586 set_regdomain();
Marek Behún0f2e66a2019-05-02 16:53:37 +0200587 handle_reset_button();
Marek Behúndb1e5c62019-05-24 14:57:53 +0200588 pci_init();
Marek Behún09e16b82017-06-09 19:28:45 +0200589
590 return 0;
591}
592
Marek Behúnab9447f2021-10-09 19:33:44 +0200593int show_board_info(void)
Marek Behún09e16b82017-06-09 19:28:45 +0200594{
595 u32 version_num, serial_num;
Pali Rohár0387f7f2022-04-08 16:30:12 +0200596 int err;
Marek Behún09e16b82017-06-09 19:28:45 +0200597
Pali Rohár0387f7f2022-04-08 16:30:12 +0200598 err = turris_atsha_otp_get_serial_number(&version_num, &serial_num);
Marek Behúnab9447f2021-10-09 19:33:44 +0200599 printf("Model: Turris Omnia\n");
Marek Behúnc4ba72a2019-05-02 16:53:34 +0200600 printf(" RAM size: %i MiB\n", omnia_get_ram_size_gb() * 1024);
Marek Behún09e16b82017-06-09 19:28:45 +0200601 if (err)
Marek Behúnc4ba72a2019-05-02 16:53:34 +0200602 printf(" Serial Number: unknown\n");
Marek Behún09e16b82017-06-09 19:28:45 +0200603 else
Marek Behúnc4ba72a2019-05-02 16:53:34 +0200604 printf(" Serial Number: %08X%08X\n", be32_to_cpu(version_num),
605 be32_to_cpu(serial_num));
Marek Behún09e16b82017-06-09 19:28:45 +0200606
607 return 0;
608}
609
Marek Behún09e16b82017-06-09 19:28:45 +0200610int misc_init_r(void)
611{
Pali Rohár60f37e82022-04-08 16:30:14 +0200612 turris_atsha_otp_init_mac_addresses(1);
Marek Behún09e16b82017-06-09 19:28:45 +0200613 return 0;
614}
615
Marek Behún91ef59c2021-07-15 19:21:02 +0200616#if defined(CONFIG_OF_BOARD_SETUP)
617/*
618 * I plan to generalize this function and move it to common/fdt_support.c.
619 * This will require some more work on multiple boards, though, so for now leave
620 * it here.
621 */
622static bool fixup_mtd_partitions(void *blob, int offset, struct mtd_info *mtd)
623{
624 struct mtd_info *slave;
625 int parts;
626
627 parts = fdt_subnode_offset(blob, offset, "partitions");
628 if (parts < 0)
629 return false;
630
631 if (fdt_del_node(blob, parts) < 0)
632 return false;
633
634 parts = fdt_add_subnode(blob, offset, "partitions");
635 if (parts < 0)
636 return false;
637
638 if (fdt_setprop_u32(blob, parts, "#address-cells", 1) < 0)
639 return false;
640
641 if (fdt_setprop_u32(blob, parts, "#size-cells", 1) < 0)
642 return false;
643
644 if (fdt_setprop_string(blob, parts, "compatible",
645 "fixed-partitions") < 0)
646 return false;
647
648 mtd_probe_devices();
649
Pali Rohárd8210ef2021-10-21 17:55:48 +0200650 list_for_each_entry_reverse(slave, &mtd->partitions, node) {
Marek Behún91ef59c2021-07-15 19:21:02 +0200651 char name[32];
652 int part;
653
654 snprintf(name, sizeof(name), "partition@%llx", slave->offset);
655 part = fdt_add_subnode(blob, parts, name);
656 if (part < 0)
657 return false;
658
659 if (fdt_setprop_u32(blob, part, "reg", slave->offset) < 0)
660 return false;
661
662 if (fdt_appendprop_u32(blob, part, "reg", slave->size) < 0)
663 return false;
664
665 if (fdt_setprop_string(blob, part, "label", slave->name) < 0)
666 return false;
667
668 if (!(slave->flags & MTD_WRITEABLE))
669 if (fdt_setprop_empty(blob, part, "read-only") < 0)
670 return false;
671
672 if (slave->flags & MTD_POWERUP_LOCK)
673 if (fdt_setprop_empty(blob, part, "lock") < 0)
674 return false;
675 }
676
677 return true;
678}
679
Pali Rohárcbda3e22022-01-10 11:47:18 +0100680static void fixup_spi_nor_partitions(void *blob)
Marek Behún91ef59c2021-07-15 19:21:02 +0200681{
682 struct mtd_info *mtd;
683 int node;
684
685 mtd = get_mtd_device_nm(OMNIA_SPI_NOR_PATH);
686 if (IS_ERR_OR_NULL(mtd))
687 goto fail;
688
689 node = fdt_path_offset(blob, OMNIA_SPI_NOR_PATH);
690 if (node < 0)
691 goto fail;
692
693 if (!fixup_mtd_partitions(blob, node, mtd))
694 goto fail;
695
Marek Behún36feac92021-09-25 02:49:18 +0200696 put_mtd_device(mtd);
Pali Rohárcbda3e22022-01-10 11:47:18 +0100697 return;
Marek Behún91ef59c2021-07-15 19:21:02 +0200698
699fail:
700 printf("Failed fixing SPI NOR partitions!\n");
Marek Behún36feac92021-09-25 02:49:18 +0200701 if (!IS_ERR_OR_NULL(mtd))
702 put_mtd_device(mtd);
Pali Rohárcbda3e22022-01-10 11:47:18 +0100703}
704
705int ft_board_setup(void *blob, struct bd_info *bd)
706{
707 fixup_spi_nor_partitions(blob);
708 fixup_serdes_0_nodes(blob);
709
Marek Behún91ef59c2021-07-15 19:21:02 +0200710 return 0;
711}
712#endif