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Simon Glassb2c1cac2014-02-26 15:59:21 -07001/dts-v1/;
2
Patrick Delaunay23aee612020-01-13 11:35:13 +01003#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +01005#include <dt-bindings/input/input.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -04006#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05307#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +01008
Simon Glassb2c1cac2014-02-26 15:59:21 -07009/ {
10 model = "sandbox";
11 compatible = "sandbox";
12 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060013 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070014
Simon Glassfef72b72014-07-23 06:55:03 -060015 aliases {
16 console = &uart0;
Michael Walle7efcdfd2021-02-25 16:51:11 +010017 ethernet0 = "/eth@10002000";
18 ethernet2 = &swp_0;
19 ethernet3 = &eth_3;
20 ethernet4 = &dsa_eth0;
21 ethernet5 = &eth_5;
Simon Glass5620cf82018-10-01 12:22:40 -060022 gpio1 = &gpio_a;
23 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010024 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070025 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060026 mmc0 = "/mmc0";
27 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -070028 pci0 = &pci0;
29 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070030 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020031 remoteproc0 = &rproc_1;
32 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060033 rtc0 = &rtc_0;
34 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060035 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020036 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070037 testbus3 = "/some-bus";
38 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070039 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070040 testfdt3 = "/b-test";
41 testfdt5 = "/some-bus/c-test@5";
42 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070043 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020044 fdt-dummy0 = "/translation-test@8000/dev@0,0";
45 fdt-dummy1 = "/translation-test@8000/dev@1,100";
46 fdt-dummy2 = "/translation-test@8000/dev@2,200";
47 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060048 usb0 = &usb_0;
49 usb1 = &usb_1;
50 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020051 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020052 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060053 };
54
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020055 config {
56 environment {
57 from_fdt = "yes";
58 fdt_env_path = "";
59 };
60 };
61
Nandor Han6521e5d2021-06-10 16:56:44 +030062 reboot-mode0 {
63 compatible = "reboot-mode-gpio";
64 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
65 u-boot,env-variable = "bootstatus";
66 mode-test = <0x01>;
67 mode-download = <0x03>;
68 };
69
Nandor Han7e4067a2021-06-10 16:56:45 +030070 reboot_mode1: reboot-mode@14 {
71 compatible = "reboot-mode-rtc";
72 rtc = <&rtc_0>;
73 reg = <0x30 4>;
74 u-boot,env-variable = "bootstatus";
75 big-endian;
76 mode-test = <0x21969147>;
77 mode-download = <0x51939147>;
78 };
79
Simon Glassed96cde2018-12-10 10:37:33 -070080 audio: audio-codec {
81 compatible = "sandbox,audio-codec";
82 #sound-dai-cells = <1>;
83 };
84
Philippe Reynes1ee26482020-07-24 18:19:51 +020085 buttons {
86 compatible = "gpio-keys";
87
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020088 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +020089 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020090 label = "button1";
Philippe Reynes1ee26482020-07-24 18:19:51 +020091 };
92
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020093 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +020094 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020095 label = "button2";
Philippe Reynes1ee26482020-07-24 18:19:51 +020096 };
97 };
98
Marek Szyprowskiad398592021-02-18 11:33:18 +010099 buttons2 {
100 compatible = "adc-keys";
101 io-channels = <&adc 3>;
102 keyup-threshold-microvolt = <3000000>;
103
104 button-up {
105 label = "button3";
106 linux,code = <KEY_F3>;
107 press-threshold-microvolt = <1500000>;
108 };
109
110 button-down {
111 label = "button4";
112 linux,code = <KEY_F4>;
113 press-threshold-microvolt = <1000000>;
114 };
115
116 button-enter {
117 label = "button5";
118 linux,code = <KEY_F5>;
119 press-threshold-microvolt = <500000>;
120 };
121 };
122
Simon Glassc953aaf2018-12-10 10:37:34 -0700123 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600124 reg = <0 0>;
125 compatible = "google,cros-ec-sandbox";
126
127 /*
128 * This describes the flash memory within the EC. Note
129 * that the STM32L flash erases to 0, not 0xff.
130 */
131 flash {
132 image-pos = <0x08000000>;
133 size = <0x20000>;
134 erase-value = <0>;
135
136 /* Information for sandbox */
137 ro {
138 image-pos = <0>;
139 size = <0xf000>;
140 };
141 wp-ro {
142 image-pos = <0xf000>;
143 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700144 used = <0x884>;
145 compress = "lz4";
146 uncomp-size = <0xcf8>;
147 hash {
148 algo = "sha256";
149 value = [00 01 02 03 04 05 06 07
150 08 09 0a 0b 0c 0d 0e 0f
151 10 11 12 13 14 15 16 17
152 18 19 1a 1b 1c 1d 1e 1f];
153 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600154 };
155 rw {
156 image-pos = <0x10000>;
157 size = <0x10000>;
158 };
159 };
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300160
161 cros_ec_pwm: cros-ec-pwm {
162 compatible = "google,cros-ec-pwm";
163 #pwm-cells = <1>;
164 };
165
Simon Glass699c9ca2018-10-01 12:22:08 -0600166 };
167
Yannick Fertré9712c822019-10-07 15:29:05 +0200168 dsi_host: dsi_host {
169 compatible = "sandbox,dsi-host";
170 };
171
Simon Glassb2c1cac2014-02-26 15:59:21 -0700172 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600173 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700174 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600175 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700176 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600177 u-boot,dm-pre-reloc;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100178 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
179 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700180 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100181 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
182 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
183 <&gpio_b 7 GPIO_IN 3 2 1>,
184 <&gpio_b 8 GPIO_OUT 3 2 1>,
185 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100186 test3-gpios =
187 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
188 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
189 <&gpio_c 2 GPIO_OUT>,
190 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
191 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200192 <&gpio_c 5 GPIO_IN>,
193 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
194 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530195 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
196 test5-gpios = <&gpio_a 19>;
197
Simon Glass6df01f92018-12-10 10:37:37 -0700198 int-value = <1234>;
199 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200200 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200201 int-array = <5678 9123 4567>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600202 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700203 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600204 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200205 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530206
207 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
208 <&muxcontroller0 2>, <&muxcontroller0 3>,
209 <&muxcontroller1>;
210 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
211 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100212 display-timings {
213 timing0: 240x320 {
214 clock-frequency = <6500000>;
215 hactive = <240>;
216 vactive = <320>;
217 hfront-porch = <6>;
218 hback-porch = <7>;
219 hsync-len = <1>;
220 vback-porch = <5>;
221 vfront-porch = <8>;
222 vsync-len = <2>;
223 hsync-active = <1>;
224 vsync-active = <0>;
225 de-active = <1>;
226 pixelclk-active = <1>;
227 interlaced;
228 doublescan;
229 doubleclk;
230 };
231 timing1: 480x800 {
232 clock-frequency = <9000000>;
233 hactive = <480>;
234 vactive = <800>;
235 hfront-porch = <10>;
236 hback-porch = <59>;
237 hsync-len = <12>;
238 vback-porch = <15>;
239 vfront-porch = <17>;
240 vsync-len = <16>;
241 hsync-active = <0>;
242 vsync-active = <1>;
243 de-active = <0>;
244 pixelclk-active = <0>;
245 };
246 timing2: 800x480 {
247 clock-frequency = <33500000>;
248 hactive = <800>;
249 vactive = <480>;
250 hback-porch = <89>;
251 hfront-porch = <164>;
252 vback-porch = <23>;
253 vfront-porch = <10>;
254 hsync-len = <11>;
255 vsync-len = <13>;
256 };
257 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700258 };
259
260 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600261 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700262 compatible = "not,compatible";
263 };
264
265 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600266 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700267 };
268
Simon Glass5620cf82018-10-01 12:22:40 -0600269 backlight: backlight {
270 compatible = "pwm-backlight";
271 enable-gpios = <&gpio_a 1>;
272 power-supply = <&ldo_1>;
273 pwms = <&pwm 0 1000>;
274 default-brightness-level = <5>;
275 brightness-levels = <0 16 32 64 128 170 202 234 255>;
276 };
277
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200278 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200279 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200280 bind-test-child1 {
281 compatible = "sandbox,phy";
282 #phy-cells = <1>;
283 };
284
285 bind-test-child2 {
286 compatible = "simple-bus";
287 };
288 };
289
Simon Glassb2c1cac2014-02-26 15:59:21 -0700290 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600291 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700292 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600293 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700294 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530295
296 mux-controls = <&muxcontroller0 0>;
297 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700298 };
299
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200300 phy_provider0: gen_phy@0 {
301 compatible = "sandbox,phy";
302 #phy-cells = <1>;
303 };
304
305 phy_provider1: gen_phy@1 {
306 compatible = "sandbox,phy";
307 #phy-cells = <0>;
308 broken;
309 };
310
developer71092972020-05-02 11:35:12 +0200311 phy_provider2: gen_phy@2 {
312 compatible = "sandbox,phy";
313 #phy-cells = <0>;
314 };
315
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200316 gen_phy_user: gen_phy_user {
317 compatible = "simple-bus";
318 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
319 phy-names = "phy1", "phy2", "phy3";
320 };
321
developer71092972020-05-02 11:35:12 +0200322 gen_phy_user1: gen_phy_user1 {
323 compatible = "simple-bus";
324 phys = <&phy_provider0 0>, <&phy_provider2>;
325 phy-names = "phy1", "phy2";
326 };
327
Simon Glassb2c1cac2014-02-26 15:59:21 -0700328 some-bus {
329 #address-cells = <1>;
330 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600331 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600332 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600333 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700334 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600335 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700336 compatible = "denx,u-boot-fdt-test";
337 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600338 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700339 ping-add = <5>;
340 };
Simon Glass40717422014-07-23 06:55:18 -0600341 c-test@0 {
342 compatible = "denx,u-boot-fdt-test";
343 reg = <0>;
344 ping-expect = <6>;
345 ping-add = <6>;
346 };
347 c-test@1 {
348 compatible = "denx,u-boot-fdt-test";
349 reg = <1>;
350 ping-expect = <7>;
351 ping-add = <7>;
352 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700353 };
354
355 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600356 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600357 ping-expect = <6>;
358 ping-add = <6>;
359 compatible = "google,another-fdt-test";
360 };
361
362 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600363 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600364 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700365 ping-add = <6>;
366 compatible = "google,another-fdt-test";
367 };
368
Simon Glass0ccb0972015-01-25 08:27:05 -0700369 f-test {
370 compatible = "denx,u-boot-fdt-test";
371 };
372
373 g-test {
374 compatible = "denx,u-boot-fdt-test";
375 };
376
Bin Mengd9d24782018-10-10 22:07:01 -0700377 h-test {
378 compatible = "denx,u-boot-fdt-test1";
379 };
380
developercf8bc132020-05-02 11:35:10 +0200381 i-test {
382 compatible = "mediatek,u-boot-fdt-test";
383 #address-cells = <1>;
384 #size-cells = <0>;
385
386 subnode@0 {
387 reg = <0>;
388 };
389
390 subnode@1 {
391 reg = <1>;
392 };
393
394 subnode@2 {
395 reg = <2>;
396 };
397 };
398
Simon Glass204675c2019-12-29 21:19:25 -0700399 devres-test {
400 compatible = "denx,u-boot-devres-test";
401 };
402
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530403 another-test {
404 reg = <0 2>;
405 compatible = "denx,u-boot-fdt-test";
406 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
407 test5-gpios = <&gpio_a 19>;
408 };
409
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100410 mmio-bus@0 {
411 #address-cells = <1>;
412 #size-cells = <1>;
413 compatible = "denx,u-boot-test-bus";
414 dma-ranges = <0x10000000 0x00000000 0x00040000>;
415
416 subnode@0 {
417 compatible = "denx,u-boot-fdt-test";
418 };
419 };
420
421 mmio-bus@1 {
422 #address-cells = <1>;
423 #size-cells = <1>;
424 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100425
426 subnode@0 {
427 compatible = "denx,u-boot-fdt-test";
428 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100429 };
430
Simon Glass3c601b12020-07-07 13:12:06 -0600431 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600432 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600433 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600434 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600435 child {
436 compatible = "denx,u-boot-acpi-test";
437 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600438 };
439
Simon Glass3c601b12020-07-07 13:12:06 -0600440 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600441 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600442 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600443 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600444 };
445
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200446 clocks {
447 clk_fixed: clk-fixed {
448 compatible = "fixed-clock";
449 #clock-cells = <0>;
450 clock-frequency = <1234>;
451 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000452
453 clk_fixed_factor: clk-fixed-factor {
454 compatible = "fixed-factor-clock";
455 #clock-cells = <0>;
456 clock-div = <3>;
457 clock-mult = <2>;
458 clocks = <&clk_fixed>;
459 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200460
461 osc {
462 compatible = "fixed-clock";
463 #clock-cells = <0>;
464 clock-frequency = <20000000>;
465 };
Stephen Warrena9622432016-06-17 09:44:00 -0600466 };
467
468 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600469 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600470 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200471 assigned-clocks = <&clk_sandbox 3>;
472 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600473 };
474
475 clk-test {
476 compatible = "sandbox,clk-test";
477 clocks = <&clk_fixed>,
478 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200479 <&clk_sandbox 0>,
480 <&clk_sandbox 3>,
481 <&clk_sandbox 2>;
482 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600483 };
484
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200485 ccf: clk-ccf {
486 compatible = "sandbox,clk-ccf";
487 };
488
Simon Glass5b968632015-05-22 15:42:15 -0600489 eth@10002000 {
490 compatible = "sandbox,eth";
491 reg = <0x10002000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500492 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass5b968632015-05-22 15:42:15 -0600493 };
494
495 eth_5: eth@10003000 {
496 compatible = "sandbox,eth";
497 reg = <0x10003000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500498 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass5b968632015-05-22 15:42:15 -0600499 };
500
Bin Meng04a11cb2015-08-27 22:25:53 -0700501 eth_3: sbe5 {
502 compatible = "sandbox,eth";
503 reg = <0x10005000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500504 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng04a11cb2015-08-27 22:25:53 -0700505 };
506
Simon Glass5b968632015-05-22 15:42:15 -0600507 eth@10004000 {
508 compatible = "sandbox,eth";
509 reg = <0x10004000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500510 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass5b968632015-05-22 15:42:15 -0600511 };
512
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800513 dsa_eth0: dsa-test-eth {
514 compatible = "sandbox,eth";
515 reg = <0x10006000 0x1000>;
516 fake-host-hwaddr = [00 00 66 44 22 66];
517 };
518
519 dsa-test {
520 compatible = "sandbox,dsa";
521
522 ports {
523 #address-cells = <1>;
524 #size-cells = <0>;
525 swp_0: port@0 {
526 reg = <0>;
527 label = "lan0";
528 phy-mode = "rgmii-rxid";
529
530 fixed-link {
531 speed = <100>;
532 full-duplex;
533 };
534 };
535
536 swp_1: port@1 {
537 reg = <1>;
538 label = "lan1";
539 phy-mode = "rgmii-txid";
Bin Meng381ed972021-03-14 20:14:58 +0800540 fixed-link = <0 1 100 0 0>;
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800541 };
542
543 port@2 {
544 reg = <2>;
545 ethernet = <&dsa_eth0>;
546
547 fixed-link {
548 speed = <1000>;
549 full-duplex;
550 };
551 };
552 };
553 };
554
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700555 firmware {
556 sandbox_firmware: sandbox-firmware {
557 compatible = "sandbox,firmware";
558 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200559
560 sandbox-scmi-agent@0 {
561 compatible = "sandbox,scmi-agent";
562 #address-cells = <1>;
563 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200564
565 clk_scmi0: protocol@14 {
566 reg = <0x14>;
567 #clock-cells = <1>;
568 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200569
570 reset_scmi0: protocol@16 {
571 reg = <0x16>;
572 #reset-cells = <1>;
573 };
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100574
575 protocol@17 {
576 reg = <0x17>;
577
578 regulators {
579 #address-cells = <1>;
580 #size-cells = <0>;
581
582 regul0_scmi0: reg@0 {
583 reg = <0>;
584 regulator-name = "sandbox-voltd0";
585 regulator-min-microvolt = <1100000>;
586 regulator-max-microvolt = <3300000>;
587 };
588 regul1_scmi0: reg@1 {
589 reg = <0x1>;
590 regulator-name = "sandbox-voltd1";
591 regulator-min-microvolt = <1800000>;
592 };
593 };
594 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200595 };
596
597 sandbox-scmi-agent@1 {
598 compatible = "sandbox,scmi-agent";
599 #address-cells = <1>;
600 #size-cells = <0>;
601
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200602 clk_scmi1: protocol@14 {
603 reg = <0x14>;
604 #clock-cells = <1>;
605 };
606
Etienne Carriere02fd1262020-09-09 18:44:00 +0200607 protocol@10 {
608 reg = <0x10>;
609 };
610 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700611 };
612
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100613 pinctrl-gpio {
614 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700615
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100616 gpio_a: base-gpios {
617 compatible = "sandbox,gpio";
618 gpio-controller;
619 #gpio-cells = <1>;
620 gpio-bank-name = "a";
621 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200622 hog_input_active_low {
623 gpio-hog;
624 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200625 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200626 };
627 hog_input_active_high {
628 gpio-hog;
629 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200630 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200631 };
632 hog_output_low {
633 gpio-hog;
634 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200635 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200636 };
637 hog_output_high {
638 gpio-hog;
639 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200640 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200641 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100642 };
643
644 gpio_b: extra-gpios {
645 compatible = "sandbox,gpio";
646 gpio-controller;
647 #gpio-cells = <5>;
648 gpio-bank-name = "b";
649 sandbox,gpio-count = <10>;
650 };
Simon Glass25348a42014-10-13 23:42:11 -0600651
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100652 gpio_c: pinmux-gpios {
653 compatible = "sandbox,gpio";
654 gpio-controller;
655 #gpio-cells = <2>;
656 gpio-bank-name = "c";
657 sandbox,gpio-count = <10>;
658 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100659 };
660
Simon Glass7df766e2014-12-10 08:55:55 -0700661 i2c@0 {
662 #address-cells = <1>;
663 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600664 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700665 compatible = "sandbox,i2c";
666 clock-frequency = <100000>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200667 pinctrl-names = "default";
668 pinctrl-0 = <&pinmux_i2c0_pins>;
669
Simon Glass7df766e2014-12-10 08:55:55 -0700670 eeprom@2c {
671 reg = <0x2c>;
672 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700673 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200674 partitions {
675 compatible = "fixed-partitions";
676 #address-cells = <1>;
677 #size-cells = <1>;
678 bootcount_i2c: bootcount@10 {
679 reg = <10 2>;
680 };
681 };
Simon Glass7df766e2014-12-10 08:55:55 -0700682 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200683
Simon Glass336b2952015-05-22 15:42:17 -0600684 rtc_0: rtc@43 {
685 reg = <0x43>;
686 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700687 sandbox,emul = <&emul0>;
Simon Glass336b2952015-05-22 15:42:17 -0600688 };
689
690 rtc_1: rtc@61 {
691 reg = <0x61>;
692 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700693 sandbox,emul = <&emul1>;
694 };
695
696 i2c_emul: emul {
697 reg = <0xff>;
698 compatible = "sandbox,i2c-emul-parent";
699 emul_eeprom: emul-eeprom {
700 compatible = "sandbox,i2c-eeprom";
701 sandbox,filename = "i2c.bin";
702 sandbox,size = <256>;
703 };
704 emul0: emul0 {
Simon Glass98af3742021-02-03 06:01:17 -0700705 compatible = "sandbox,i2c-rtc-emul";
Simon Glass17b56f62018-11-18 08:14:34 -0700706 };
707 emul1: emull {
Simon Glass98af3742021-02-03 06:01:17 -0700708 compatible = "sandbox,i2c-rtc-emul";
Simon Glass336b2952015-05-22 15:42:17 -0600709 };
710 };
711
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200712 sandbox_pmic: sandbox_pmic {
713 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700714 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200715 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200716
717 mc34708: pmic@41 {
718 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700719 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200720 };
Simon Glass7df766e2014-12-10 08:55:55 -0700721 };
722
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100723 bootcount@0 {
724 compatible = "u-boot,bootcount-rtc";
725 rtc = <&rtc_1>;
726 offset = <0x13>;
727 };
728
Michal Simek4f18f922020-05-28 11:48:55 +0200729 bootcount {
730 compatible = "u-boot,bootcount-i2c-eeprom";
731 i2c-eeprom = <&bootcount_i2c>;
732 };
733
Nandor Han88895812021-06-10 15:40:38 +0300734 bootcount_4@0 {
735 compatible = "u-boot,bootcount-syscon";
736 syscon = <&syscon0>;
737 reg = <0x0 0x04>, <0x0 0x04>;
738 reg-names = "syscon_reg", "offset";
739 };
740
741 bootcount_2@0 {
742 compatible = "u-boot,bootcount-syscon";
743 syscon = <&syscon0>;
744 reg = <0x0 0x04>, <0x0 0x02> ;
745 reg-names = "syscon_reg", "offset";
746 };
747
Marek Szyprowskiad398592021-02-18 11:33:18 +0100748 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100749 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100750 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100751 vdd-supply = <&buck2>;
752 vss-microvolts = <0>;
753 };
754
Simon Glass515dcff2020-02-06 09:55:00 -0700755 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700756 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700757 interrupt-controller;
758 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700759 };
760
Simon Glass90b6fef2016-01-18 19:52:26 -0700761 lcd {
762 u-boot,dm-pre-reloc;
763 compatible = "sandbox,lcd-sdl";
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200764 pinctrl-names = "default";
765 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass90b6fef2016-01-18 19:52:26 -0700766 xres = <1366>;
767 yres = <768>;
768 };
769
Simon Glassd783eb32015-07-06 12:54:34 -0600770 leds {
771 compatible = "gpio-leds";
772
773 iracibble {
774 gpios = <&gpio_a 1 0>;
775 label = "sandbox:red";
776 };
777
778 martinet {
779 gpios = <&gpio_a 2 0>;
780 label = "sandbox:green";
781 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200782
783 default_on {
784 gpios = <&gpio_a 5 0>;
785 label = "sandbox:default_on";
786 default-state = "on";
787 };
788
789 default_off {
790 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -0400791 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200792 default-state = "off";
793 };
Simon Glassd783eb32015-07-06 12:54:34 -0600794 };
795
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200796 gpio-wdt {
797 gpios = <&gpio_a 7 0>;
798 compatible = "linux,wdt-gpio";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +0200799 hw_margin_ms = <100>;
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200800 always-running;
801 };
802
Stephen Warren62f2c902016-05-16 17:41:37 -0600803 mbox: mbox {
804 compatible = "sandbox,mbox";
805 #mbox-cells = <1>;
806 };
807
808 mbox-test {
809 compatible = "sandbox,mbox-test";
810 mboxes = <&mbox 100>, <&mbox 1>;
811 mbox-names = "other", "test";
812 };
813
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900814 cpus {
Sean Anderson79d3bba2020-09-28 10:52:23 -0400815 timebase-frequency = <2000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900816 cpu-test1 {
Sean Anderson79d3bba2020-09-28 10:52:23 -0400817 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900818 compatible = "sandbox,cpu_sandbox";
819 u-boot,dm-pre-reloc;
820 };
Mario Sixdea5df72018-08-06 10:23:44 +0200821
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900822 cpu-test2 {
823 compatible = "sandbox,cpu_sandbox";
824 u-boot,dm-pre-reloc;
825 };
Mario Sixdea5df72018-08-06 10:23:44 +0200826
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900827 cpu-test3 {
828 compatible = "sandbox,cpu_sandbox";
829 u-boot,dm-pre-reloc;
830 };
Mario Sixdea5df72018-08-06 10:23:44 +0200831 };
832
Dave Gerlach75dbdfc2020-07-15 23:39:58 -0500833 chipid: chipid {
834 compatible = "sandbox,soc";
835 };
836
Simon Glassc953aaf2018-12-10 10:37:34 -0700837 i2s: i2s {
838 compatible = "sandbox,i2s";
839 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700840 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700841 };
842
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200843 nop-test_0 {
844 compatible = "sandbox,nop_sandbox1";
845 nop-test_1 {
846 compatible = "sandbox,nop_sandbox2";
847 bind = "True";
848 };
849 nop-test_2 {
850 compatible = "sandbox,nop_sandbox2";
851 bind = "False";
852 };
853 };
854
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200855 misc-test {
856 compatible = "sandbox,misc_sandbox";
857 };
858
Simon Glasse4fef742017-04-23 20:02:07 -0600859 mmc2 {
860 compatible = "sandbox,mmc";
Simon Glass965cd402021-07-05 16:32:58 -0600861 non-removable;
Simon Glasse4fef742017-04-23 20:02:07 -0600862 };
863
864 mmc1 {
865 compatible = "sandbox,mmc";
866 };
867
868 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600869 compatible = "sandbox,mmc";
870 };
871
Simon Glass53a68b32019-02-16 20:24:50 -0700872 pch {
873 compatible = "sandbox,pch";
874 };
875
Tom Rini4a3ca482020-02-11 12:41:23 -0500876 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700877 compatible = "sandbox,pci";
878 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500879 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700880 #address-cells = <3>;
881 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -0600882 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -0700883 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700884 pci@0,0 {
885 compatible = "pci-generic";
886 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600887 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700888 };
Alex Margineanf1274432019-06-07 11:24:24 +0300889 pci@1,0 {
890 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600891 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
892 reg = <0x02000814 0 0 0 0
893 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600894 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +0300895 };
Simon Glass937bb472019-12-06 21:41:57 -0700896 p2sb-pci@2,0 {
897 compatible = "sandbox,p2sb";
898 reg = <0x02001010 0 0 0 0>;
899 sandbox,emul = <&p2sb_emul>;
900
901 adder {
902 intel,p2sb-port-id = <3>;
903 compatible = "sandbox,adder";
904 };
905 };
Simon Glass8c501022019-12-06 21:41:54 -0700906 pci@1e,0 {
907 compatible = "sandbox,pmc";
908 reg = <0xf000 0 0 0 0>;
909 sandbox,emul = <&pmc_emul1e>;
910 acpi-base = <0x400>;
911 gpe0-dwx-mask = <0xf>;
912 gpe0-dwx-shift-base = <4>;
913 gpe0-dw = <6 7 9>;
914 gpe0-sts = <0x20>;
915 gpe0-en = <0x30>;
916 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700917 pci@1f,0 {
918 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600919 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
920 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600921 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700922 };
923 };
924
Simon Glassb98ba4c2019-09-25 08:56:10 -0600925 pci-emul0 {
926 compatible = "sandbox,pci-emul-parent";
927 swap_case_emul0_0: emul0@0,0 {
928 compatible = "sandbox,swap-case";
929 };
930 swap_case_emul0_1: emul0@1,0 {
931 compatible = "sandbox,swap-case";
932 use-ea;
933 };
934 swap_case_emul0_1f: emul0@1f,0 {
935 compatible = "sandbox,swap-case";
936 };
Simon Glass937bb472019-12-06 21:41:57 -0700937 p2sb_emul: emul@2,0 {
938 compatible = "sandbox,p2sb-emul";
939 };
Simon Glass8c501022019-12-06 21:41:54 -0700940 pmc_emul1e: emul@1e,0 {
941 compatible = "sandbox,pmc-emul";
942 };
Simon Glassb98ba4c2019-09-25 08:56:10 -0600943 };
944
Tom Rini4a3ca482020-02-11 12:41:23 -0500945 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -0700946 compatible = "sandbox,pci";
947 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500948 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -0700949 #address-cells = <3>;
950 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -0700951 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
952 0x02000000 0 0x31000000 0x31000000 0 0x2000 // MEM1
953 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -0700954 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +0200955 0x0c 0x00 0x1234 0x5678
956 0x10 0x00 0x1234 0x5678>;
957 pci@10,0 {
958 reg = <0x8000 0 0 0 0>;
959 };
Bin Meng408e5902018-08-03 01:14:41 -0700960 };
961
Tom Rini4a3ca482020-02-11 12:41:23 -0500962 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -0700963 compatible = "sandbox,pci";
964 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500965 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -0700966 #address-cells = <3>;
967 #size-cells = <2>;
968 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
969 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
970 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
971 pci@1f,0 {
972 compatible = "pci-generic";
973 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600974 sandbox,emul = <&swap_case_emul2_1f>;
975 };
976 };
977
978 pci-emul2 {
979 compatible = "sandbox,pci-emul-parent";
980 swap_case_emul2_1f: emul2@1f,0 {
981 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -0700982 };
983 };
984
Ramon Friedc64f19b2019-04-27 11:15:23 +0300985 pci_ep: pci_ep {
986 compatible = "sandbox,pci_ep";
987 };
988
Simon Glass9c433fe2017-04-23 20:10:44 -0600989 probing {
990 compatible = "simple-bus";
991 test1 {
992 compatible = "denx,u-boot-probe-test";
993 };
994
995 test2 {
996 compatible = "denx,u-boot-probe-test";
997 };
998
999 test3 {
1000 compatible = "denx,u-boot-probe-test";
1001 };
1002
1003 test4 {
1004 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001005 first-syscon = <&syscon0>;
1006 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +01001007 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -06001008 };
1009 };
1010
Stephen Warren92c67fa2016-07-13 13:45:31 -06001011 pwrdom: power-domain {
1012 compatible = "sandbox,power-domain";
1013 #power-domain-cells = <1>;
1014 };
1015
1016 power-domain-test {
1017 compatible = "sandbox,power-domain-test";
1018 power-domains = <&pwrdom 2>;
1019 };
1020
Simon Glass5620cf82018-10-01 12:22:40 -06001021 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -06001022 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001023 #pwm-cells = <2>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001024 pinctrl-names = "default";
1025 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001026 };
1027
1028 pwm2 {
1029 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001030 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001031 };
1032
Simon Glass3d355e62015-07-06 12:54:31 -06001033 ram {
1034 compatible = "sandbox,ram";
1035 };
1036
Simon Glassd860f222015-07-06 12:54:29 -06001037 reset@0 {
1038 compatible = "sandbox,warm-reset";
1039 };
1040
1041 reset@1 {
1042 compatible = "sandbox,reset";
1043 };
1044
Stephen Warren6488e642016-06-17 09:43:59 -06001045 resetc: reset-ctl {
1046 compatible = "sandbox,reset-ctl";
1047 #reset-cells = <1>;
1048 };
1049
1050 reset-ctl-test {
1051 compatible = "sandbox,reset-ctl-test";
Neil Armstrong9b4cdef2021-04-20 10:42:25 +02001052 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1053 reset-names = "other", "test", "test2", "test3";
Stephen Warren6488e642016-06-17 09:43:59 -06001054 };
1055
Sughosh Ganu23e37512019-12-28 23:58:31 +05301056 rng {
1057 compatible = "sandbox,sandbox-rng";
1058 };
1059
Nishanth Menonedf85812015-09-17 15:42:41 -05001060 rproc_1: rproc@1 {
1061 compatible = "sandbox,test-processor";
1062 remoteproc-name = "remoteproc-test-dev1";
1063 };
1064
1065 rproc_2: rproc@2 {
1066 compatible = "sandbox,test-processor";
1067 internal-memory-mapped;
1068 remoteproc-name = "remoteproc-test-dev2";
1069 };
1070
Simon Glass5620cf82018-10-01 12:22:40 -06001071 panel {
1072 compatible = "simple-panel";
1073 backlight = <&backlight 0 100>;
1074 };
1075
Ramon Fried26ed32e2018-07-02 02:57:59 +03001076 smem@0 {
1077 compatible = "sandbox,smem";
1078 };
1079
Simon Glass76072ac2018-12-10 10:37:36 -07001080 sound {
1081 compatible = "sandbox,sound";
1082 cpu {
1083 sound-dai = <&i2s 0>;
1084 };
1085
1086 codec {
1087 sound-dai = <&audio 0>;
1088 };
1089 };
1090
Simon Glass25348a42014-10-13 23:42:11 -06001091 spi@0 {
1092 #address-cells = <1>;
1093 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -06001094 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -06001095 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +02001096 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001097 pinctrl-names = "default";
1098 pinctrl-0 = <&pinmux_spi0_pins>;
1099
Simon Glass25348a42014-10-13 23:42:11 -06001100 spi.bin@0 {
1101 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +00001102 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -06001103 spi-max-frequency = <40000000>;
1104 sandbox,filename = "spi.bin";
1105 };
Ovidiu Panaitae734732020-12-14 19:06:47 +02001106 spi.bin@1 {
1107 reg = <1>;
1108 compatible = "spansion,m25p16", "jedec,spi-nor";
1109 spi-max-frequency = <50000000>;
1110 sandbox,filename = "spi.bin";
1111 spi-cpol;
1112 spi-cpha;
1113 };
Simon Glass25348a42014-10-13 23:42:11 -06001114 };
1115
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001116 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -06001117 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +02001118 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -06001119 };
1120
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001121 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -06001122 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -06001123 reg = <0x20 5
1124 0x28 6
1125 0x30 7
1126 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001127 };
1128
Patrick Delaunayee010432019-03-07 09:57:13 +01001129 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001130 compatible = "simple-mfd", "syscon";
1131 reg = <0x40 5
1132 0x48 6
1133 0x50 7
1134 0x58 8>;
1135 };
1136
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301137 syscon3: syscon@3 {
1138 compatible = "simple-mfd", "syscon";
1139 reg = <0x000100 0x10>;
1140
1141 muxcontroller0: a-mux-controller {
1142 compatible = "mmio-mux";
1143 #mux-control-cells = <1>;
1144
1145 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1146 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1147 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1148 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1149 u-boot,mux-autoprobe;
1150 };
1151 };
1152
1153 muxcontroller1: emul-mux-controller {
1154 compatible = "mux-emul";
1155 #mux-control-cells = <0>;
1156 u-boot,mux-autoprobe;
1157 idle-state = <0xabcd>;
1158 };
1159
Simon Glass791a17f2020-12-16 21:20:27 -07001160 testfdtm0 {
1161 compatible = "denx,u-boot-fdtm-test";
1162 };
1163
1164 testfdtm1: testfdtm1 {
1165 compatible = "denx,u-boot-fdtm-test";
1166 };
1167
1168 testfdtm2 {
1169 compatible = "denx,u-boot-fdtm-test";
1170 };
1171
Sean Anderson79d3bba2020-09-28 10:52:23 -04001172 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001173 compatible = "sandbox,timer";
1174 clock-frequency = <1000000>;
1175 };
1176
Sean Anderson79d3bba2020-09-28 10:52:23 -04001177 timer@1 {
1178 compatible = "sandbox,timer";
1179 sandbox,timebase-frequency-fallback;
1180 };
1181
Miquel Raynal80938c12018-05-15 11:57:27 +02001182 tpm2 {
1183 compatible = "sandbox,tpm2";
1184 };
1185
Simon Glass5b968632015-05-22 15:42:15 -06001186 uart0: serial {
1187 compatible = "sandbox,serial";
1188 u-boot,dm-pre-reloc;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001189 pinctrl-names = "default";
1190 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershberger4c197242015-03-22 17:09:15 -05001191 };
1192
Simon Glass31680482015-03-25 12:23:05 -06001193 usb_0: usb@0 {
1194 compatible = "sandbox,usb";
1195 status = "disabled";
1196 hub {
1197 compatible = "sandbox,usb-hub";
1198 #address-cells = <1>;
1199 #size-cells = <0>;
1200 flash-stick {
1201 reg = <0>;
1202 compatible = "sandbox,usb-flash";
1203 };
1204 };
1205 };
1206
1207 usb_1: usb@1 {
1208 compatible = "sandbox,usb";
1209 hub {
1210 compatible = "usb-hub";
1211 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001212 #address-cells = <1>;
1213 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001214 hub-emul {
1215 compatible = "sandbox,usb-hub";
1216 #address-cells = <1>;
1217 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001218 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001219 reg = <0>;
1220 compatible = "sandbox,usb-flash";
1221 sandbox,filepath = "testflash.bin";
1222 };
1223
Simon Glass4700fe52015-11-08 23:48:01 -07001224 flash-stick@1 {
1225 reg = <1>;
1226 compatible = "sandbox,usb-flash";
1227 sandbox,filepath = "testflash1.bin";
1228 };
1229
1230 flash-stick@2 {
1231 reg = <2>;
1232 compatible = "sandbox,usb-flash";
1233 sandbox,filepath = "testflash2.bin";
1234 };
1235
Simon Glassc0ccc722015-11-08 23:48:08 -07001236 keyb@3 {
1237 reg = <3>;
1238 compatible = "sandbox,usb-keyb";
1239 };
1240
Simon Glass31680482015-03-25 12:23:05 -06001241 };
Michael Walle7c961322020-06-02 01:47:07 +02001242
1243 usbstor@1 {
1244 reg = <1>;
1245 };
1246 usbstor@3 {
1247 reg = <3>;
1248 };
Simon Glass31680482015-03-25 12:23:05 -06001249 };
1250 };
1251
1252 usb_2: usb@2 {
1253 compatible = "sandbox,usb";
1254 status = "disabled";
1255 };
1256
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001257 spmi: spmi@0 {
1258 compatible = "sandbox,spmi";
1259 #address-cells = <0x1>;
1260 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001261 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001262 pm8916@0 {
1263 compatible = "qcom,spmi-pmic";
1264 reg = <0x0 0x1>;
1265 #address-cells = <0x1>;
1266 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001267 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001268
1269 spmi_gpios: gpios@c000 {
1270 compatible = "qcom,pm8916-gpio";
1271 reg = <0xc000 0x400>;
1272 gpio-controller;
1273 gpio-count = <4>;
1274 #gpio-cells = <2>;
1275 gpio-bank-name="spmi";
1276 };
1277 };
1278 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001279
1280 wdt0: wdt@0 {
1281 compatible = "sandbox,wdt";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001282 hw_margin_ms = <200>;
maxims@google.comdaea6d42017-04-17 12:00:21 -07001283 };
Rob Clarka471b672018-01-10 11:33:30 +01001284
Mario Six95922152018-08-09 14:51:19 +02001285 axi: axi@0 {
1286 compatible = "sandbox,axi";
1287 #address-cells = <0x1>;
1288 #size-cells = <0x1>;
1289 store@0 {
1290 compatible = "sandbox,sandbox_store";
1291 reg = <0x0 0x400>;
1292 };
1293 };
1294
Rob Clarka471b672018-01-10 11:33:30 +01001295 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001296 #address-cells = <1>;
1297 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001298 setting = "sunrise ohoka";
1299 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001300 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001301 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarka471b672018-01-10 11:33:30 +01001302 chosen-test {
1303 compatible = "denx,u-boot-fdt-test";
1304 reg = <9 1>;
1305 };
1306 };
Mario Six35616ef2018-03-12 14:53:33 +01001307
1308 translation-test@8000 {
1309 compatible = "simple-bus";
1310 reg = <0x8000 0x4000>;
1311
1312 #address-cells = <0x2>;
1313 #size-cells = <0x1>;
1314
1315 ranges = <0 0x0 0x8000 0x1000
1316 1 0x100 0x9000 0x1000
1317 2 0x200 0xA000 0x1000
1318 3 0x300 0xB000 0x1000
1319 >;
1320
Fabien Dessenne22236e02019-05-31 15:11:30 +02001321 dma-ranges = <0 0x000 0x10000000 0x1000
1322 1 0x100 0x20000000 0x1000
1323 >;
1324
Mario Six35616ef2018-03-12 14:53:33 +01001325 dev@0,0 {
1326 compatible = "denx,u-boot-fdt-dummy";
1327 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +01001328 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001329 };
1330
1331 dev@1,100 {
1332 compatible = "denx,u-boot-fdt-dummy";
1333 reg = <1 0x100 0x1000>;
1334
1335 };
1336
1337 dev@2,200 {
1338 compatible = "denx,u-boot-fdt-dummy";
1339 reg = <2 0x200 0x1000>;
1340 };
1341
1342
1343 noxlatebus@3,300 {
1344 compatible = "simple-bus";
1345 reg = <3 0x300 0x1000>;
1346
1347 #address-cells = <0x1>;
1348 #size-cells = <0x0>;
1349
1350 dev@42 {
1351 compatible = "denx,u-boot-fdt-dummy";
1352 reg = <0x42>;
1353 };
1354 };
1355 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001356
1357 osd {
1358 compatible = "sandbox,sandbox_osd";
1359 };
Tom Rinib93eea72018-09-30 18:16:51 -04001360
Jens Wiklander86afaa62018-09-25 16:40:16 +02001361 sandbox_tee {
1362 compatible = "sandbox,tee";
1363 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001364
1365 sandbox_virtio1 {
1366 compatible = "sandbox,virtio1";
1367 };
1368
1369 sandbox_virtio2 {
1370 compatible = "sandbox,virtio2";
1371 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001372
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001373 sandbox_scmi {
1374 compatible = "sandbox,scmi-devices";
1375 clocks = <&clk_scmi0 7>, <&clk_scmi0 3>, <&clk_scmi1 1>;
Etienne Carriere8b9b6892020-09-09 18:44:07 +02001376 resets = <&reset_scmi0 3>;
Etienne Carriereb8f15cd2021-03-08 22:38:07 +01001377 regul0-supply = <&regul0_scmi0>;
1378 regul1-supply = <&regul1_scmi0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001379 };
1380
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001381 pinctrl {
1382 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001383
Sean Anderson3438e3b2020-09-14 11:01:57 -04001384 pinctrl-names = "default", "alternate";
1385 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1386 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001387
Sean Anderson3438e3b2020-09-14 11:01:57 -04001388 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001389 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001390 pins = "P5";
1391 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001392 bias-pull-up;
1393 input-disable;
1394 };
1395 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001396 pins = "P6";
1397 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001398 output-high;
1399 drive-open-drain;
1400 };
1401 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001402 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001403 bias-pull-down;
1404 input-enable;
1405 };
1406 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001407 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001408 bias-disable;
1409 };
1410 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001411
1412 pinctrl_i2c: i2c {
1413 groups {
1414 groups = "I2C_UART";
1415 function = "I2C";
1416 };
1417
1418 pins {
1419 pins = "P0", "P1";
1420 drive-open-drain;
1421 };
1422 };
1423
1424 pinctrl_i2s: i2s {
1425 groups = "SPI_I2S";
1426 function = "I2S";
1427 };
1428
1429 pinctrl_spi: spi {
1430 groups = "SPI_I2S";
1431 function = "SPI";
1432
1433 cs {
1434 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1435 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1436 };
1437 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001438 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001439
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001440 pinctrl-single-no-width {
1441 compatible = "pinctrl-single";
1442 reg = <0x0000 0x238>;
1443 #pinctrl-cells = <1>;
1444 pinctrl-single,function-mask = <0x7f>;
1445 };
1446
1447 pinctrl-single-pins {
1448 compatible = "pinctrl-single";
1449 reg = <0x0000 0x238>;
1450 #pinctrl-cells = <1>;
1451 pinctrl-single,register-width = <32>;
1452 pinctrl-single,function-mask = <0x7f>;
1453
1454 pinmux_pwm_pins: pinmux_pwm_pins {
1455 pinctrl-single,pins = < 0x48 0x06 >;
1456 };
1457
1458 pinmux_spi0_pins: pinmux_spi0_pins {
1459 pinctrl-single,pins = <
1460 0x190 0x0c
1461 0x194 0x0c
1462 0x198 0x23
1463 0x19c 0x0c
1464 >;
1465 };
1466
1467 pinmux_uart0_pins: pinmux_uart0_pins {
1468 pinctrl-single,pins = <
1469 0x70 0x30
1470 0x74 0x00
1471 >;
1472 };
1473 };
1474
1475 pinctrl-single-bits {
1476 compatible = "pinctrl-single";
1477 reg = <0x0000 0x50>;
1478 #pinctrl-cells = <2>;
1479 pinctrl-single,bit-per-mux;
1480 pinctrl-single,register-width = <32>;
1481 pinctrl-single,function-mask = <0xf>;
1482
1483 pinmux_i2c0_pins: pinmux_i2c0_pins {
1484 pinctrl-single,bits = <
1485 0x10 0x00002200 0x0000ff00
1486 >;
1487 };
1488
1489 pinmux_lcd_pins: pinmux_lcd_pins {
1490 pinctrl-single,bits = <
1491 0x40 0x22222200 0xffffff00
1492 0x44 0x22222222 0xffffffff
1493 0x48 0x00000022 0x000000ff
1494 0x48 0x02000000 0x0f000000
1495 0x4c 0x02000022 0x0f0000ff
1496 >;
1497 };
1498 };
1499
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001500 hwspinlock@0 {
1501 compatible = "sandbox,hwspinlock";
1502 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001503
1504 dma: dma {
1505 compatible = "sandbox,dma";
1506 #dma-cells = <1>;
1507
1508 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1509 dma-names = "m2m", "tx0", "rx0";
1510 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001511
Alex Marginean0649be52019-07-12 10:13:53 +03001512 /*
1513 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1514 * end of the test. If parent mdio is removed first, clean-up of the
1515 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1516 * active at the end of the test. That it turn doesn't allow the mdio
1517 * class to be destroyed, triggering an error.
1518 */
1519 mdio-mux-test {
1520 compatible = "sandbox,mdio-mux";
1521 #address-cells = <1>;
1522 #size-cells = <0>;
1523 mdio-parent-bus = <&mdio>;
1524
1525 mdio-ch-test@0 {
1526 reg = <0>;
1527 };
1528 mdio-ch-test@1 {
1529 reg = <1>;
1530 };
1531 };
1532
1533 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001534 compatible = "sandbox,mdio";
1535 };
Sean Andersonb7860542020-06-24 06:41:12 -04001536
1537 pm-bus-test {
1538 compatible = "simple-pm-bus";
1539 clocks = <&clk_sandbox 4>;
1540 power-domains = <&pwrdom 1>;
1541 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001542
1543 resetc2: syscon-reset {
1544 compatible = "syscon-reset";
1545 #reset-cells = <1>;
1546 regmap = <&syscon0>;
1547 offset = <1>;
1548 mask = <0x27FFFFFF>;
1549 assert-high = <0>;
1550 };
1551
1552 syscon-reset-test {
1553 compatible = "sandbox,misc_sandbox";
1554 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1555 reset-names = "valid", "no_mask", "out_of_range";
1556 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301557
Simon Glass458b66a2020-11-05 06:32:05 -07001558 sysinfo {
1559 compatible = "sandbox,sysinfo-sandbox";
1560 };
1561
Sean Anderson1c830672021-04-20 10:50:58 -04001562 sysinfo-gpio {
1563 compatible = "gpio-sysinfo";
1564 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1565 revisions = <19>, <5>;
1566 names = "rev_a", "foo";
1567 };
1568
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301569 some_regmapped-bus {
1570 #address-cells = <0x1>;
1571 #size-cells = <0x1>;
1572
1573 ranges = <0x0 0x0 0x10>;
1574 compatible = "simple-bus";
1575
1576 regmap-test_0 {
1577 reg = <0 0x10>;
1578 compatible = "sandbox,regmap_test";
1579 };
1580 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001581};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001582
1583#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01001584#include "cros-ec-keyboard.dtsi"