Adam Ford | 4e96ff8 | 2018-04-15 13:51:26 -0400 | [diff] [blame] | 1 | menuconfig SPI |
| 2 | bool "SPI Support" |
Jagan Teki | 38d91fe | 2019-10-16 18:04:13 +0530 | [diff] [blame] | 3 | help |
| 4 | The "Serial Peripheral Interface" is a low level synchronous |
| 5 | protocol. Chips that support SPI can have data transfer rates |
| 6 | up to several tens of Mbit/sec. Chips are addressed with a |
| 7 | controller and a chipselect. Most SPI slaves don't support |
| 8 | dynamic device discovery; some are even write-only or read-only. |
| 9 | |
| 10 | SPI is widely used by microcontrollers to talk with sensors, |
| 11 | eeprom and flash memory, codecs and various other controller |
| 12 | chips, analog to digital (and d-to-a) converters, and more. |
| 13 | MMC and SD cards can be accessed using SPI protocol; and for |
| 14 | DataFlash cards used in MMC sockets, SPI must always be used. |
| 15 | |
| 16 | SPI is one of a family of similar protocols using a four wire |
| 17 | interface (select, clock, data in, data out) including Microwire |
| 18 | (half duplex), SSP, SSI, and PSP. This driver framework should |
| 19 | work with most such devices and controllers. |
Adam Ford | 4e96ff8 | 2018-04-15 13:51:26 -0400 | [diff] [blame] | 20 | |
| 21 | if SPI |
Jagan Teki | bfd3f8b | 2015-06-27 22:35:14 +0530 | [diff] [blame] | 22 | |
Masahiro Yamada | 57ad8ee | 2014-10-23 22:26:09 +0900 | [diff] [blame] | 23 | config DM_SPI |
| 24 | bool "Enable Driver Model for SPI drivers" |
| 25 | depends on DM |
| 26 | help |
Simon Glass | d8b771d | 2015-02-05 21:41:35 -0700 | [diff] [blame] | 27 | Enable driver model for SPI. The SPI slave interface |
| 28 | (spi_setup_slave(), spi_xfer(), etc.) is then implemented by |
| 29 | the SPI uclass. Drivers provide methods to access the SPI |
| 30 | buses that they control. The uclass interface is defined in |
| 31 | include/spi.h. The existing spi_slave structure is attached |
| 32 | as 'parent data' to every slave on each bus. Slaves |
| 33 | typically use driver-private data instead of extending the |
| 34 | spi_slave structure. |
Simon Glass | 4b322d3 | 2015-03-06 13:19:05 -0700 | [diff] [blame] | 35 | |
Boris Brezillon | 32473fe | 2018-08-16 17:30:11 +0200 | [diff] [blame] | 36 | config SPI_MEM |
| 37 | bool "SPI memory extension" |
| 38 | help |
| 39 | Enable this option if you want to enable the SPI memory extension. |
| 40 | This extension is meant to simplify interaction with SPI memories |
| 41 | by providing an high-level interface to send memory-like commands. |
| 42 | |
Vignesh R | 4e341d3 | 2019-02-05 11:29:15 +0530 | [diff] [blame] | 43 | if DM_SPI |
| 44 | |
Thomas Chou | c589954 | 2015-10-14 08:33:34 +0800 | [diff] [blame] | 45 | config ALTERA_SPI |
| 46 | bool "Altera SPI driver" |
| 47 | help |
| 48 | Enable the Altera SPI driver. This driver can be used to |
| 49 | access the SPI NOR flash on platforms embedding this Altera |
| 50 | IP core. Please find details on the "Embedded Peripherals IP |
| 51 | User Guide" of Altera. |
| 52 | |
Jagan Teki | 353dffb | 2018-03-07 10:33:33 +0530 | [diff] [blame] | 53 | config ATCSPI200_SPI |
| 54 | bool "Andestech ATCSPI200 SPI driver" |
| 55 | help |
| 56 | Enable the Andestech ATCSPI200 SPI driver. This driver can be |
| 57 | used to access the SPI flash on AE3XX and AE250 platforms embedding |
| 58 | this Andestech IP core. |
| 59 | |
Wills Wang | f502148 | 2016-03-16 16:59:58 +0800 | [diff] [blame] | 60 | config ATH79_SPI |
| 61 | bool "Atheros SPI driver" |
| 62 | depends on ARCH_ATH79 |
| 63 | help |
| 64 | Enable the Atheros ar7xxx/ar9xxx SoC SPI driver, it was used |
| 65 | to access SPI NOR flash and other SPI peripherals. This driver |
| 66 | uses driver model and requires a device tree binding to operate. |
| 67 | please refer to doc/device-tree-bindings/spi/spi-ath79.txt. |
| 68 | |
Tudor Ambarus | 88151bb | 2019-06-18 08:51:50 +0000 | [diff] [blame] | 69 | config ATMEL_QSPI |
| 70 | bool "Atmel Quad SPI Controller" |
| 71 | depends on ARCH_AT91 |
| 72 | help |
| 73 | Enable the Atmel Quad SPI controller in master mode. This driver |
| 74 | does not support generic SPI. The implementation supports only the |
| 75 | spi-mem interface. |
| 76 | |
Wenyou Yang | da8ee98 | 2016-10-28 14:17:49 +0800 | [diff] [blame] | 77 | config ATMEL_SPI |
| 78 | bool "Atmel SPI driver" |
Jagan Teki | 1d831b6 | 2018-03-14 18:46:44 +0530 | [diff] [blame] | 79 | default y if ARCH_AT91 |
Wenyou Yang | da8ee98 | 2016-10-28 14:17:49 +0800 | [diff] [blame] | 80 | help |
| 81 | This enables driver for the Atmel SPI Controller, present on |
Andy Shevchenko | 8cb5cdd | 2017-07-05 16:25:22 +0300 | [diff] [blame] | 82 | many AT91 (ARM) chips. This driver can be used to access |
| 83 | the SPI Flash, such as AT25DF321. |
Wenyou Yang | da8ee98 | 2016-10-28 14:17:49 +0800 | [diff] [blame] | 84 | |
Álvaro Fernández Rojas | 55d96ec | 2018-01-20 02:13:38 +0100 | [diff] [blame] | 85 | config BCM63XX_HSSPI |
| 86 | bool "BCM63XX HSSPI driver" |
Philippe Reynes | e14c085 | 2020-01-07 20:14:12 +0100 | [diff] [blame] | 87 | depends on (ARCH_BMIPS || ARCH_BCM68360 || \ |
| 88 | ARCH_BCM6858 || ARCH_BCM63158) |
Álvaro Fernández Rojas | 55d96ec | 2018-01-20 02:13:38 +0100 | [diff] [blame] | 89 | help |
| 90 | Enable the BCM6328 HSSPI driver. This driver can be used to |
| 91 | access the SPI NOR flash on platforms embedding this Broadcom |
| 92 | SPI core. |
| 93 | |
Álvaro Fernández Rojas | cc243c6 | 2018-01-23 17:14:58 +0100 | [diff] [blame] | 94 | config BCM63XX_SPI |
| 95 | bool "BCM6348 SPI driver" |
| 96 | depends on ARCH_BMIPS |
| 97 | help |
| 98 | Enable the BCM6348/BCM6358 SPI driver. This driver can be used to |
| 99 | access the SPI NOR flash on platforms embedding these Broadcom |
| 100 | SPI cores. |
| 101 | |
Thomas Fitzsimmons | 919646d | 2018-06-08 17:59:45 -0400 | [diff] [blame] | 102 | config BCMSTB_SPI |
| 103 | bool "BCMSTB SPI driver" |
| 104 | help |
| 105 | Enable the Broadcom set-top box SPI driver. This driver can |
| 106 | be used to access the SPI flash on platforms embedding this |
| 107 | Broadcom SPI core. |
| 108 | |
Jagan Teki | 15a932c | 2015-06-27 22:37:00 +0530 | [diff] [blame] | 109 | config CADENCE_QSPI |
| 110 | bool "Cadence QSPI driver" |
| 111 | help |
| 112 | Enable the Cadence Quad-SPI (QSPI) driver. This driver can be |
| 113 | used to access the SPI NOR flash on platforms embedding this |
| 114 | Cadence IP core. |
| 115 | |
Angelo Dureghello | 72e9be3 | 2019-03-13 21:46:46 +0100 | [diff] [blame] | 116 | config CF_SPI |
| 117 | bool "ColdFire SPI driver" |
| 118 | help |
| 119 | Enable the ColdFire SPI driver. This driver can be used on |
| 120 | some m68k SoCs. |
| 121 | |
Jagan Teki | 97c18ed | 2020-05-26 13:34:26 +0530 | [diff] [blame] | 122 | config DAVINCI_SPI |
| 123 | bool "Davinci & Keystone SPI driver" |
| 124 | depends on ARCH_DAVINCI || ARCH_KEYSTONE |
| 125 | help |
| 126 | Enable the Davinci SPI driver |
| 127 | |
Jagan Teki | 15a932c | 2015-06-27 22:37:00 +0530 | [diff] [blame] | 128 | config DESIGNWARE_SPI |
| 129 | bool "Designware SPI driver" |
| 130 | help |
| 131 | Enable the Designware SPI driver. This driver can be used to |
| 132 | access the SPI NOR flash on platforms embedding this Designware |
| 133 | IP core. |
| 134 | |
Jagan Teki | 6274bf9 | 2015-06-27 15:32:19 +0530 | [diff] [blame] | 135 | config EXYNOS_SPI |
| 136 | bool "Samsung Exynos SPI driver" |
| 137 | help |
| 138 | Enable the Samsung Exynos SPI driver. This driver can be used to |
| 139 | access the SPI NOR flash on platforms embedding this Samsung |
| 140 | Exynos IP core. |
| 141 | |
Jagan Teki | ae30c02 | 2015-06-27 14:17:06 +0530 | [diff] [blame] | 142 | config FSL_DSPI |
| 143 | bool "Freescale DSPI driver" |
| 144 | help |
| 145 | Enable the Freescale DSPI driver. This driver can be used to |
| 146 | access the SPI NOR flash and SPI Data flash on platforms embedding |
| 147 | this Freescale DSPI IP core. LS102xA and Colibri VF50/VF61 platforms |
| 148 | use this driver. |
| 149 | |
Jagan Teki | 72cedd4 | 2020-05-26 00:24:19 +0530 | [diff] [blame] | 150 | config FSL_QSPI |
| 151 | bool "Freescale QSPI driver" |
| 152 | imply SPI_FLASH_BAR |
| 153 | help |
| 154 | Enable the Freescale Quad-SPI (QSPI) driver. This driver can be |
| 155 | used to access the SPI NOR flash on platforms embedding this |
| 156 | Freescale IP core. |
| 157 | |
Ye Li | d7e3c9a | 2020-06-09 00:59:06 -0700 | [diff] [blame] | 158 | config FSL_QSPI_AHB_FULL_MAP |
| 159 | bool "Use full AHB memory map space" |
| 160 | depends on FSL_QSPI |
| 161 | default y if ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_IMX8M |
| 162 | help |
| 163 | Enable the Freescale QSPI driver to use full AHB memory map space for |
| 164 | flash access. |
| 165 | |
Jagan Teki | 3872b7c | 2015-06-27 15:43:27 +0530 | [diff] [blame] | 166 | config ICH_SPI |
| 167 | bool "Intel ICH SPI driver" |
| 168 | help |
| 169 | Enable the Intel ICH SPI driver. This driver can be used to |
| 170 | access the SPI NOR flash on platforms embedding this Intel |
| 171 | ICH IP core. |
| 172 | |
Bhargav Shah | 83a2631 | 2020-06-18 23:15:13 +0530 | [diff] [blame] | 173 | config KIRKWOOD_SPI |
| 174 | bool "Marvell Kirkwood SPI Driver" |
| 175 | help |
| 176 | Enable support for SPI on various Marvell SoCs, such as |
| 177 | Kirkwood and Armada 375. |
| 178 | |
Neil Armstrong | 5c16217 | 2018-11-22 11:01:05 +0100 | [diff] [blame] | 179 | config MESON_SPIFC |
| 180 | bool "Amlogic Meson SPI Flash Controller driver" |
| 181 | depends on ARCH_MESON |
| 182 | help |
| 183 | Enable the Amlogic Meson SPI Flash Controller SPIFC) driver. |
| 184 | This driver can be used to access the SPI NOR flash chips on |
| 185 | Amlogic Meson SoCs. |
| 186 | |
Christophe Leroy | 847362b | 2018-11-21 08:51:57 +0000 | [diff] [blame] | 187 | config MPC8XX_SPI |
| 188 | bool "MPC8XX SPI Driver" |
| 189 | depends on MPC8xx |
| 190 | help |
| 191 | Enable support for SPI on MPC8XX |
| 192 | |
Jagan Teki | 52515d5 | 2019-04-29 01:58:53 +0530 | [diff] [blame] | 193 | config MPC8XXX_SPI |
| 194 | bool "MPC8XXX SPI Driver" |
| 195 | help |
| 196 | Enable support for SPI on the MPC8XXX PowerPC SoCs. |
| 197 | |
Jagan Teki | 72cedd4 | 2020-05-26 00:24:19 +0530 | [diff] [blame] | 198 | config MSCC_BB_SPI |
| 199 | bool "MSCC bitbang SPI driver" |
| 200 | depends on SOC_VCOREIII |
| 201 | help |
| 202 | Enable MSCC bitbang SPI driver. This driver can be used on |
| 203 | MSCC SOCs. |
| 204 | |
Stefan Roese | 8adb8cb | 2018-08-16 10:48:48 +0200 | [diff] [blame] | 205 | config MT7621_SPI |
| 206 | bool "MediaTek MT7621 SPI driver" |
developer | 89f051b | 2019-04-30 11:13:58 +0800 | [diff] [blame] | 207 | depends on SOC_MT7628 |
Stefan Roese | 8adb8cb | 2018-08-16 10:48:48 +0200 | [diff] [blame] | 208 | help |
| 209 | Enable the MT7621 SPI driver. This driver can be used to access |
| 210 | the SPI NOR flash on platforms embedding this Ralink / MediaTek |
| 211 | SPI core, like MT7621/7628/7688. |
| 212 | |
developer | 8a78b4d | 2019-07-22 17:09:01 +0530 | [diff] [blame] | 213 | config MTK_SNFI_SPI |
| 214 | bool "Mediatek SPI memory controller driver" |
| 215 | depends on SPI_MEM |
| 216 | help |
| 217 | Enable the Mediatek SPI memory controller driver. This driver is |
| 218 | originally based on the MediaTek SNFI IP core. It can only be |
| 219 | used to access SPI memory devices like SPI-NOR or SPI-NAND on |
| 220 | platforms embedding this IP core, like MT7622/M7629. |
| 221 | |
Stefan Roese | 9ec1c78 | 2016-05-19 15:56:44 +0200 | [diff] [blame] | 222 | config MVEBU_A3700_SPI |
| 223 | bool "Marvell Armada 3700 SPI driver" |
Marek Behún | 0afd934 | 2018-04-24 17:21:26 +0200 | [diff] [blame] | 224 | select CLK_ARMADA_3720 |
Stefan Roese | 9ec1c78 | 2016-05-19 15:56:44 +0200 | [diff] [blame] | 225 | help |
| 226 | Enable the Marvell Armada 3700 SPI driver. This driver can be |
| 227 | used to access the SPI NOR flash on platforms embedding this |
| 228 | Marvell IP core. |
| 229 | |
Jagan Teki | 2174d85 | 2020-05-25 23:24:23 +0530 | [diff] [blame] | 230 | config MXS_SPI |
| 231 | bool "MXS SPI Driver" |
| 232 | help |
| 233 | Enable the MXS SPI controller driver. This driver can be used |
| 234 | on the i.MX23 and i.MX28 SoCs. |
| 235 | |
Michael Walle | d3967f3 | 2019-12-18 00:09:58 +0100 | [diff] [blame] | 236 | config NXP_FSPI |
| 237 | bool "NXP FlexSPI driver" |
| 238 | depends on SPI_MEM |
| 239 | help |
| 240 | Enable the NXP FlexSPI (FSPI) driver. This driver can be used to |
| 241 | access the SPI NOR flash on platforms embedding this NXP IP core. |
| 242 | |
Suneel Garapati | 4171777 | 2020-07-30 13:56:18 +0200 | [diff] [blame] | 243 | config OCTEON_SPI |
| 244 | bool "Octeon SPI driver" |
| 245 | depends on DM_PCI && (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) |
| 246 | help |
| 247 | Enable the Octeon SPI driver. This driver can be used to |
| 248 | access the SPI NOR flash on Octeon II/III and OcteonTX/TX2 |
| 249 | SoC platforms. |
| 250 | |
Jagan Teki | 99899c5 | 2020-05-27 18:26:36 +0530 | [diff] [blame] | 251 | config OMAP3_SPI |
| 252 | bool "McSPI driver for OMAP" |
| 253 | help |
| 254 | SPI master controller for OMAP24XX and later Multichannel SPI |
| 255 | (McSPI). This driver be used to access SPI chips on platforms |
| 256 | embedding this OMAP3 McSPI IP core. |
| 257 | |
Purna Chandra Mandal | ffa5442 | 2016-06-02 14:26:08 +0530 | [diff] [blame] | 258 | config PIC32_SPI |
| 259 | bool "Microchip PIC32 SPI driver" |
| 260 | depends on MACH_PIC32 |
| 261 | help |
| 262 | Enable the Microchip PIC32 SPI driver. This driver can be used |
| 263 | to access the SPI NOR flash, MMC-over-SPI on platforms based on |
| 264 | Microchip PIC32 family devices. |
| 265 | |
Quentin Schulz | 3add62d | 2018-08-31 16:28:29 +0200 | [diff] [blame] | 266 | config PL022_SPI |
| 267 | bool "ARM AMBA PL022 SSP controller driver" |
| 268 | depends on ARM |
| 269 | help |
| 270 | This selects the ARM(R) AMBA(R) PrimeCell PL022 SSP |
| 271 | controller. If you have an embedded system with an AMBA(R) |
| 272 | bus and a PL022 controller, say Y or M here. |
| 273 | |
Robert Marko | e4b17a7 | 2020-10-08 22:05:09 +0200 | [diff] [blame] | 274 | config SPI_QUP |
| 275 | bool "Qualcomm SPI controller with QUP interface" |
| 276 | depends on ARCH_IPQ40XX |
| 277 | help |
| 278 | Qualcomm Universal Peripheral (QUP) core is an AHB slave that |
| 279 | provides a common data path (an output FIFO and an input FIFO) |
| 280 | for serial peripheral interface (SPI) mini-core. SPI in master |
| 281 | mode supports up to 50MHz, up to four chip selects, programmable |
| 282 | data path from 4 bits to 32 bits and numerous protocol variants. |
| 283 | |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 284 | config RENESAS_RPC_SPI |
| 285 | bool "Renesas RPC SPI driver" |
Marek Vasut | f9db3b3 | 2019-05-04 18:52:33 +0200 | [diff] [blame] | 286 | depends on RCAR_GEN3 || RZA1 |
Vignesh R | 1f66bca | 2019-02-05 11:29:28 +0530 | [diff] [blame] | 287 | imply SPI_FLASH_BAR |
Marek Vasut | 6ca967b | 2017-11-29 06:29:46 +0100 | [diff] [blame] | 288 | help |
| 289 | Enable the Renesas RPC SPI driver, used to access SPI NOR flash |
| 290 | on Renesas RCar Gen3 SoCs. This uses driver model and requires a |
| 291 | device tree binding to operate. |
| 292 | |
Simon Glass | d1c1377 | 2015-09-01 19:19:37 -0600 | [diff] [blame] | 293 | config ROCKCHIP_SPI |
| 294 | bool "Rockchip SPI driver" |
| 295 | help |
| 296 | Enable the Rockchip SPI driver, used to access SPI NOR flash and |
| 297 | other SPI peripherals (such as the Chrome OS EC) on Rockchip SoCs. |
| 298 | This uses driver model and requires a device tree binding to |
| 299 | operate. |
| 300 | |
Simon Glass | 4b322d3 | 2015-03-06 13:19:05 -0700 | [diff] [blame] | 301 | config SANDBOX_SPI |
| 302 | bool "Sandbox SPI driver" |
| 303 | depends on SANDBOX && DM |
| 304 | help |
| 305 | Enable SPI support for sandbox. This is an emulation of a real SPI |
| 306 | bus. Devices can be attached to the bus using the device tree |
| 307 | which specifies the driver to use. As an example, see this device |
| 308 | tree fragment from sandbox.dts. It shows that the SPI bus has a |
| 309 | single flash device on chip select 0 which is emulated by the driver |
| 310 | for "sandbox,spi-flash", which is in drivers/mtd/spi/sandbox.c. |
| 311 | |
| 312 | spi@0 { |
| 313 | #address-cells = <1>; |
| 314 | #size-cells = <0>; |
| 315 | reg = <0>; |
| 316 | compatible = "sandbox,spi"; |
| 317 | cs-gpios = <0>, <&gpio_a 0>; |
| 318 | flash@0 { |
| 319 | reg = <0>; |
Simon Glass | 7e36868 | 2019-05-18 11:59:49 -0600 | [diff] [blame] | 320 | compatible = "spansion,m25p16", "jedec,spi-nor"; |
Simon Glass | 4b322d3 | 2015-03-06 13:19:05 -0700 | [diff] [blame] | 321 | spi-max-frequency = <40000000>; |
| 322 | sandbox,filename = "spi.bin"; |
| 323 | }; |
Jagan Teki | 15a932c | 2015-06-27 22:37:00 +0530 | [diff] [blame] | 324 | }; |
Jagan Teki | dd32f51 | 2015-06-27 04:41:11 +0530 | [diff] [blame] | 325 | |
Bhargav Shah | 3c34f75 | 2019-07-17 04:23:43 +0000 | [diff] [blame] | 326 | config SPI_SIFIVE |
| 327 | bool "SiFive SPI driver" |
| 328 | help |
| 329 | This driver supports the SiFive SPI IP. If unsure say N. |
| 330 | Enable the SiFive SPI controller driver. |
| 331 | |
| 332 | The SiFive SPI controller driver is found on various SiFive SoCs. |
| 333 | |
Jagan Teki | e576244 | 2020-05-26 08:34:37 +0530 | [diff] [blame] | 334 | config SOFT_SPI |
| 335 | bool "Soft SPI driver" |
| 336 | help |
| 337 | Enable Soft SPI driver. This driver is to use GPIO simulate |
| 338 | the SPI protocol. |
| 339 | |
Jagan Teki | 7b68ef4 | 2019-02-27 20:02:13 +0530 | [diff] [blame] | 340 | config SPI_SUNXI |
| 341 | bool "Allwinner SoC SPI controllers" |
Jagan Teki | 9f6eafd | 2019-10-16 18:05:56 +0530 | [diff] [blame] | 342 | default ARCH_SUNXI |
Jagan Teki | 7b68ef4 | 2019-02-27 20:02:13 +0530 | [diff] [blame] | 343 | help |
| 344 | Enable the Allwinner SoC SPi controller driver. |
| 345 | |
| 346 | Same controller driver can reuse in all Allwinner SoC variants. |
| 347 | |
Michael Kurz | 337ff2a | 2017-01-22 16:04:30 +0100 | [diff] [blame] | 348 | config STM32_QSPI |
| 349 | bool "STM32F7 QSPI driver" |
Patrice Chotard | d43c496 | 2019-04-30 16:09:18 +0200 | [diff] [blame] | 350 | depends on STM32F4 || STM32F7 || ARCH_STM32MP |
Michael Kurz | 337ff2a | 2017-01-22 16:04:30 +0100 | [diff] [blame] | 351 | help |
| 352 | Enable the STM32F7 Quad-SPI (QSPI) driver. This driver can be |
| 353 | used to access the SPI NOR flash chips on platforms embedding |
| 354 | this ST IP core. |
| 355 | |
Patrice Chotard | 0b08bf8 | 2019-04-30 18:08:28 +0200 | [diff] [blame] | 356 | config STM32_SPI |
| 357 | bool "STM32 SPI driver" |
| 358 | depends on ARCH_STM32MP |
| 359 | help |
| 360 | Enable the STM32 Serial Peripheral Interface (SPI) driver for STM32MP |
| 361 | SoCs. This uses driver model and requires a device tree binding to |
| 362 | operate. |
| 363 | |
Jagan Teki | 7977d66 | 2015-06-27 15:57:53 +0530 | [diff] [blame] | 364 | config TEGRA114_SPI |
| 365 | bool "nVidia Tegra114 SPI driver" |
| 366 | help |
| 367 | Enable the nVidia Tegra114 SPI driver. This driver can be used to |
| 368 | access the SPI NOR flash on platforms embedding this nVidia Tegra114 |
| 369 | IP core. |
| 370 | |
| 371 | This controller is different than the older SoCs SPI controller and |
| 372 | also register interface get changed with this controller. |
| 373 | |
Jagan Teki | a900d40 | 2015-06-27 16:04:05 +0530 | [diff] [blame] | 374 | config TEGRA20_SFLASH |
| 375 | bool "nVidia Tegra20 Serial Flash controller driver" |
| 376 | help |
| 377 | Enable the nVidia Tegra20 Serial Flash controller driver. This driver |
| 378 | can be used to access the SPI NOR flash on platforms embedding this |
| 379 | nVidia Tegra20 IP core. |
| 380 | |
Jagan Teki | 271aa56 | 2015-06-27 16:07:54 +0530 | [diff] [blame] | 381 | config TEGRA20_SLINK |
| 382 | bool "nVidia Tegra20/Tegra30 SLINK driver" |
| 383 | help |
| 384 | Enable the nVidia Tegra20/Tegra30 SLINK driver. This driver can |
| 385 | be used to access the SPI NOR flash on platforms embedding this |
| 386 | nVidia Tegra20/Tegra30 IP cores. |
| 387 | |
Tom Warren | 5fb0c84 | 2015-10-12 14:50:54 -0700 | [diff] [blame] | 388 | config TEGRA210_QSPI |
| 389 | bool "nVidia Tegra210 QSPI driver" |
| 390 | help |
| 391 | Enable the Tegra Quad-SPI (QSPI) driver for T210. This driver |
| 392 | be used to access SPI chips on platforms embedding this |
| 393 | NVIDIA Tegra210 IP core. |
| 394 | |
Vignesh Raghavendra | f3603b8 | 2019-04-16 21:31:59 +0530 | [diff] [blame] | 395 | config TI_QSPI |
| 396 | bool "TI QSPI driver" |
| 397 | imply TI_EDMA3 |
| 398 | help |
| 399 | Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms. |
| 400 | This driver support spi flash single, quad and memory reads. |
| 401 | |
Kunihiko Hayashi | 7a40ec0 | 2019-07-05 10:03:18 +0900 | [diff] [blame] | 402 | config UNIPHIER_SPI |
| 403 | bool "Socionext UniPhier SPI driver" |
| 404 | depends on ARCH_UNIPHIER |
| 405 | help |
| 406 | Enable the Socionext UniPhier SPI driver. This driver can |
| 407 | be used to access SPI chips on platforms embedding this |
| 408 | UniPhier IP core. |
| 409 | |
Jagan Teki | cd70d7d | 2015-06-27 04:32:43 +0530 | [diff] [blame] | 410 | config XILINX_SPI |
| 411 | bool "Xilinx SPI driver" |
Jagan Teki | cd70d7d | 2015-06-27 04:32:43 +0530 | [diff] [blame] | 412 | help |
| 413 | Enable the Xilinx SPI driver from the Xilinx EDK. This SPI |
| 414 | controller support 8 bit SPI transfers only, with or w/o FIFO. |
| 415 | For more info on Xilinx SPI Register Definitions and Overview |
| 416 | see driver file - drivers/spi/xilinx_spi.c |
| 417 | |
Jagan Teki | cad526f | 2015-06-27 00:51:38 +0530 | [diff] [blame] | 418 | config ZYNQ_SPI |
| 419 | bool "Zynq SPI driver" |
Jagan Teki | cad526f | 2015-06-27 00:51:38 +0530 | [diff] [blame] | 420 | help |
| 421 | Enable the Zynq SPI driver. This driver can be used to |
| 422 | access the SPI NOR flash on platforms embedding this Zynq |
| 423 | SPI IP core. |
Jagan Teki | bfd3f8b | 2015-06-27 22:35:14 +0530 | [diff] [blame] | 424 | |
Jagan Teki | f2e1c41 | 2015-08-16 00:19:38 +0530 | [diff] [blame] | 425 | config ZYNQ_QSPI |
| 426 | bool "Zynq QSPI driver" |
Vignesh R | 1f66bca | 2019-02-05 11:29:28 +0530 | [diff] [blame] | 427 | imply SPI_FLASH_BAR |
Jagan Teki | f2e1c41 | 2015-08-16 00:19:38 +0530 | [diff] [blame] | 428 | help |
| 429 | Enable the Zynq Quad-SPI (QSPI) driver. This driver can be |
| 430 | used to access the SPI NOR flash on platforms embedding this |
| 431 | Zynq QSPI IP core. This IP is used to connect the flash in |
| 432 | 4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel. |
| 433 | |
Siva Durga Prasad Paladugu | 7659738 | 2018-07-04 17:31:23 +0530 | [diff] [blame] | 434 | config ZYNQMP_GQSPI |
| 435 | bool "Configure ZynqMP Generic QSPI" |
Siva Durga Prasad Paladugu | 7659738 | 2018-07-04 17:31:23 +0530 | [diff] [blame] | 436 | help |
| 437 | This option is used to enable ZynqMP QSPI controller driver which |
| 438 | is used to communicate with qspi flash devices. |
| 439 | |
Jagan Teki | 15a932c | 2015-06-27 22:37:00 +0530 | [diff] [blame] | 440 | endif # if DM_SPI |
| 441 | |
Jagan Teki | a0497a3 | 2015-06-27 15:21:36 +0530 | [diff] [blame] | 442 | config FSL_ESPI |
| 443 | bool "Freescale eSPI driver" |
Xiaowei Bao | 72817cd | 2019-10-31 14:34:40 +0800 | [diff] [blame] | 444 | imply SPI_FLASH_BAR |
Jagan Teki | a0497a3 | 2015-06-27 15:21:36 +0530 | [diff] [blame] | 445 | help |
| 446 | Enable the Freescale eSPI driver. This driver can be used to |
| 447 | access the SPI interface and SPI NOR flash on platforms embedding |
| 448 | this Freescale eSPI IP core. |
| 449 | |
Tuomas Tynkkynen | fa8fdfd | 2018-02-07 02:42:17 +0200 | [diff] [blame] | 450 | config SH_QSPI |
| 451 | bool "Renesas Quad SPI driver" |
| 452 | help |
| 453 | Enable the Renesas Quad SPI controller driver. This driver can be |
| 454 | used on Renesas SoCs. |
| 455 | |
Tuomas Tynkkynen | d395879 | 2018-02-07 02:42:19 +0200 | [diff] [blame] | 456 | config MXC_SPI |
| 457 | bool "MXC SPI Driver" |
| 458 | help |
| 459 | Enable the MXC SPI controller driver. This driver can be used |
| 460 | on various i.MX SoCs such as i.MX31/35/51/6/7. |
| 461 | |
Adam Ford | 4e96ff8 | 2018-04-15 13:51:26 -0400 | [diff] [blame] | 462 | endif # menu "SPI Support" |