| Jagan Teki | bfd3f8b | 2015-06-27 22:35:14 +0530 | [diff] [blame] | 1 | menu "SPI Support" |
| 2 | |
| Masahiro Yamada | 57ad8ee | 2014-10-23 22:26:09 +0900 | [diff] [blame] | 3 | config DM_SPI |
| 4 | bool "Enable Driver Model for SPI drivers" |
| 5 | depends on DM |
| 6 | help |
| Simon Glass | d8b771d | 2015-02-05 21:41:35 -0700 | [diff] [blame] | 7 | Enable driver model for SPI. The SPI slave interface |
| 8 | (spi_setup_slave(), spi_xfer(), etc.) is then implemented by |
| 9 | the SPI uclass. Drivers provide methods to access the SPI |
| 10 | buses that they control. The uclass interface is defined in |
| 11 | include/spi.h. The existing spi_slave structure is attached |
| 12 | as 'parent data' to every slave on each bus. Slaves |
| 13 | typically use driver-private data instead of extending the |
| 14 | spi_slave structure. |
| Simon Glass | 4b322d3 | 2015-03-06 13:19:05 -0700 | [diff] [blame] | 15 | |
| 16 | config SANDBOX_SPI |
| 17 | bool "Sandbox SPI driver" |
| 18 | depends on SANDBOX && DM |
| 19 | help |
| 20 | Enable SPI support for sandbox. This is an emulation of a real SPI |
| 21 | bus. Devices can be attached to the bus using the device tree |
| 22 | which specifies the driver to use. As an example, see this device |
| 23 | tree fragment from sandbox.dts. It shows that the SPI bus has a |
| 24 | single flash device on chip select 0 which is emulated by the driver |
| 25 | for "sandbox,spi-flash", which is in drivers/mtd/spi/sandbox.c. |
| 26 | |
| 27 | spi@0 { |
| 28 | #address-cells = <1>; |
| 29 | #size-cells = <0>; |
| 30 | reg = <0>; |
| 31 | compatible = "sandbox,spi"; |
| 32 | cs-gpios = <0>, <&gpio_a 0>; |
| 33 | flash@0 { |
| 34 | reg = <0>; |
| 35 | compatible = "spansion,m25p16", "sandbox,spi-flash"; |
| 36 | spi-max-frequency = <40000000>; |
| 37 | sandbox,filename = "spi.bin"; |
| 38 | }; |
| 39 | }; |
| Marek Vasut | 4562556 | 2015-03-04 23:12:45 +0100 | [diff] [blame] | 40 | |
| 41 | config DESIGNWARE_SPI |
| 42 | bool "Designware SPI driver" |
| 43 | depends on DM_SPI |
| 44 | help |
| 45 | Enable the Designware SPI driver. This driver can be used to |
| 46 | access the SPI NOR flash on platforms embedding this Designware |
| 47 | IP core. |
| Marek Vasut | 14be9b3 | 2015-03-04 23:13:48 +0100 | [diff] [blame] | 48 | |
| 49 | config CADENCE_QSPI |
| 50 | bool "Cadence QSPI driver" |
| 51 | depends on DM_SPI |
| 52 | help |
| 53 | Enable the Cadence Quad-SPI (QSPI) driver. This driver can be |
| 54 | used to access the SPI NOR flash on platforms embedding this |
| 55 | Cadence IP core. |
| Jagan Teki | cad526f | 2015-06-27 00:51:38 +0530 | [diff] [blame] | 56 | |
| Jagan Teki | cd70d7d | 2015-06-27 04:32:43 +0530 | [diff] [blame^] | 57 | config XILINX_SPI |
| 58 | bool "Xilinx SPI driver" |
| 59 | depends on DM_SPI |
| 60 | help |
| 61 | Enable the Xilinx SPI driver from the Xilinx EDK. This SPI |
| 62 | controller support 8 bit SPI transfers only, with or w/o FIFO. |
| 63 | For more info on Xilinx SPI Register Definitions and Overview |
| 64 | see driver file - drivers/spi/xilinx_spi.c |
| 65 | |
| Jagan Teki | cad526f | 2015-06-27 00:51:38 +0530 | [diff] [blame] | 66 | config ZYNQ_SPI |
| 67 | bool "Zynq SPI driver" |
| 68 | depends on DM_SPI && (ARCH_ZYNQ || TARGET_XILINX_ZYNQMP) |
| 69 | help |
| 70 | Enable the Zynq SPI driver. This driver can be used to |
| 71 | access the SPI NOR flash on platforms embedding this Zynq |
| 72 | SPI IP core. |
| Jagan Teki | bfd3f8b | 2015-06-27 22:35:14 +0530 | [diff] [blame] | 73 | |
| 74 | endmenu # menu "SPI Support" |