blob: 7277bbdc3c5f5ee2a46459f66f705bc52b2315c3 [file] [log] [blame]
Jagan Tekibfd3f8b2015-06-27 22:35:14 +05301menu "SPI Support"
2
Masahiro Yamada57ad8ee2014-10-23 22:26:09 +09003config DM_SPI
4 bool "Enable Driver Model for SPI drivers"
5 depends on DM
6 help
Simon Glassd8b771d2015-02-05 21:41:35 -07007 Enable driver model for SPI. The SPI slave interface
8 (spi_setup_slave(), spi_xfer(), etc.) is then implemented by
9 the SPI uclass. Drivers provide methods to access the SPI
10 buses that they control. The uclass interface is defined in
11 include/spi.h. The existing spi_slave structure is attached
12 as 'parent data' to every slave on each bus. Slaves
13 typically use driver-private data instead of extending the
14 spi_slave structure.
Simon Glass4b322d32015-03-06 13:19:05 -070015
Jagan Teki15a932c2015-06-27 22:37:00 +053016if DM_SPI
17
18config CADENCE_QSPI
19 bool "Cadence QSPI driver"
20 help
21 Enable the Cadence Quad-SPI (QSPI) driver. This driver can be
22 used to access the SPI NOR flash on platforms embedding this
23 Cadence IP core.
24
25config DESIGNWARE_SPI
26 bool "Designware SPI driver"
27 help
28 Enable the Designware SPI driver. This driver can be used to
29 access the SPI NOR flash on platforms embedding this Designware
30 IP core.
31
Simon Glass4b322d32015-03-06 13:19:05 -070032config SANDBOX_SPI
33 bool "Sandbox SPI driver"
34 depends on SANDBOX && DM
35 help
36 Enable SPI support for sandbox. This is an emulation of a real SPI
37 bus. Devices can be attached to the bus using the device tree
38 which specifies the driver to use. As an example, see this device
39 tree fragment from sandbox.dts. It shows that the SPI bus has a
40 single flash device on chip select 0 which is emulated by the driver
41 for "sandbox,spi-flash", which is in drivers/mtd/spi/sandbox.c.
42
43 spi@0 {
44 #address-cells = <1>;
45 #size-cells = <0>;
46 reg = <0>;
47 compatible = "sandbox,spi";
48 cs-gpios = <0>, <&gpio_a 0>;
49 flash@0 {
50 reg = <0>;
51 compatible = "spansion,m25p16", "sandbox,spi-flash";
52 spi-max-frequency = <40000000>;
53 sandbox,filename = "spi.bin";
54 };
Jagan Teki15a932c2015-06-27 22:37:00 +053055 };
Jagan Tekidd32f512015-06-27 04:41:11 +053056
Jagan Tekicd70d7d2015-06-27 04:32:43 +053057config XILINX_SPI
58 bool "Xilinx SPI driver"
Jagan Tekicd70d7d2015-06-27 04:32:43 +053059 help
60 Enable the Xilinx SPI driver from the Xilinx EDK. This SPI
61 controller support 8 bit SPI transfers only, with or w/o FIFO.
62 For more info on Xilinx SPI Register Definitions and Overview
63 see driver file - drivers/spi/xilinx_spi.c
64
Jagan Tekicad526f2015-06-27 00:51:38 +053065config ZYNQ_SPI
66 bool "Zynq SPI driver"
Jagan Teki15a932c2015-06-27 22:37:00 +053067 depends on ARCH_ZYNQ || TARGET_XILINX_ZYNQMP
Jagan Tekicad526f2015-06-27 00:51:38 +053068 help
69 Enable the Zynq SPI driver. This driver can be used to
70 access the SPI NOR flash on platforms embedding this Zynq
71 SPI IP core.
Jagan Tekibfd3f8b2015-06-27 22:35:14 +053072
Jagan Teki15a932c2015-06-27 22:37:00 +053073endif # if DM_SPI
74
75config TI_QSPI
76 bool "TI QSPI driver"
77 help
78 Enable the TI Quad-SPI (QSPI) driver for DRA7xx and AM43xx evms.
79 This driver support spi flash single, quad and memory reads.
80
Jagan Tekibfd3f8b2015-06-27 22:35:14 +053081endmenu # menu "SPI Support"