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Masahiro Yamadacc85b7b2015-07-26 02:46:26 +09001#
2# Multifunction miscellaneous devices
3#
4
5menu "Multifunction device drivers"
6
Thomas Choub1ed6862015-10-07 20:20:51 +08007config MISC
8 bool "Enable Driver Model for Misc drivers"
9 depends on DM
10 help
11 Enable driver model for miscellaneous devices. This class is
12 used only for those do not fit other more general classes. A
13 set of generic read, write and ioctl methods may be used to
14 access the device.
15
Simon Glass605931c2018-11-18 08:14:27 -070016config SPL_MISC
17 bool "Enable Driver Model for Misc drivers in SPL"
18 depends on SPL_DM
Sean Anderson63c318f2022-04-22 16:11:37 -040019 default MISC
Simon Glass605931c2018-11-18 08:14:27 -070020 help
21 Enable driver model for miscellaneous devices. This class is
22 used only for those do not fit other more general classes. A
23 set of generic read, write and ioctl methods may be used to
24 access the device.
25
26config TPL_MISC
27 bool "Enable Driver Model for Misc drivers in TPL"
28 depends on TPL_DM
Sean Anderson63c318f2022-04-22 16:11:37 -040029 default MISC
30 help
31 Enable driver model for miscellaneous devices. This class is
32 used only for those do not fit other more general classes. A
33 set of generic read, write and ioctl methods may be used to
34 access the device.
35
36config VPL_MISC
37 bool "Enable Driver Model for Misc drivers in VPL"
38 depends on VPL_DM
39 default MISC
Simon Glass605931c2018-11-18 08:14:27 -070040 help
41 Enable driver model for miscellaneous devices. This class is
42 used only for those do not fit other more general classes. A
43 set of generic read, write and ioctl methods may be used to
44 access the device.
45
Sean Anderson77c66292022-05-05 13:11:39 -040046config NVMEM
47 bool "NVMEM support"
48 help
49 This adds support for a common interface to different types of
50 non-volatile memory. Consumers can use nvmem-cells properties to look
51 up hardware configuration data such as MAC addresses and calibration
52 settings.
53
54config SPL_NVMEM
55 bool "NVMEM support in SPL"
56 help
57 This adds support for a common interface to different types of
58 non-volatile memory. Consumers can use nvmem-cells properties to look
59 up hardware configuration data such as MAC addresses and calibration
60 settings.
61
Thomas Chou36b9c9a2015-10-14 08:43:31 +080062config ALTERA_SYSID
63 bool "Altera Sysid support"
64 depends on MISC
65 help
66 Select this to enable a sysid for Altera devices. Please find
67 details on the "Embedded Peripherals IP User Guide" of Altera.
68
Marek Behúnef2b6b12017-06-09 19:28:44 +020069config ATSHA204A
70 bool "Support for Atmel ATSHA204A module"
Pali Rohár2e269302022-04-12 11:20:44 +020071 select BITREVERSE
Marek Behúnef2b6b12017-06-09 19:28:44 +020072 depends on MISC
73 help
74 Enable support for I2C connected Atmel's ATSHA204A
75 CryptoAuthentication module found for example on the Turris Omnia
76 board.
77
Tim Harveyb8204602022-03-07 16:24:04 -080078config GATEWORKS_SC
79 bool "Gateworks System Controller Support"
80 depends on MISC
81 help
82 Enable access for the Gateworks System Controller used on Gateworks
83 boards to provide a boot watchdog, power control, temperature monitor,
84 voltage ADCs, and EEPROM.
85
Philipp Tomsichfcc1d632017-05-05 19:21:38 +020086config ROCKCHIP_EFUSE
87 bool "Rockchip e-fuse support"
88 depends on MISC
89 help
90 Enable (read-only) access for the e-fuse block found in Rockchip
91 SoCs: accesses can either be made using byte addressing and a length
92 or through child-nodes that are generated based on the e-fuse map
93 retrieved from the DTS.
94
Finley Xiao20d52a02019-09-25 17:57:49 +020095config ROCKCHIP_OTP
96 bool "Rockchip OTP Support"
97 depends on MISC
98 help
99 Enable (read-only) access for the one-time-programmable memory block
100 found in Rockchip SoCs: accesses can either be made using byte
101 addressing and a length or through child-nodes that are generated
102 based on the e-fuse map retrieved from the DTS.
103
Jonas Karlmana937c3d2023-08-21 22:30:28 +0000104config ROCKCHIP_IODOMAIN
105 bool "Rockchip IO-domain driver support"
106 depends on DM_REGULATOR && ARCH_ROCKCHIP
Chen-Yu Tsaic1b7c852025-04-29 21:28:40 +0800107 default y if ROCKCHIP_PX30
108 default y if ROCKCHIP_RK3308
109 default y if ROCKCHIP_RK3328
110 default y if ROCKCHIP_RK3399
111 default y if ROCKCHIP_RK3568
Jonas Karlmana937c3d2023-08-21 22:30:28 +0000112 help
113 Enable support for IO-domains in Rockchip SoCs. It is necessary
114 for the IO-domain setting of the SoC to match the voltage supplied
115 by the regulators.
116
Justin Klaassena66e03b2025-05-23 16:53:38 +0000117config SPL_ROCKCHIP_IODOMAIN
118 bool "Rockchip IO-domain driver support in SPL"
119 depends on SPL_MISC && SPL_DM_REGULATOR && ARCH_ROCKCHIP
120 help
121 Enable support for IO-domains in Rockchip SoCs in SPL. It is necessary
122 for the IO-domain setting of the SoC to match the voltage supplied
123 by the regulators.
124
Pragnesh Patel6e9661f2020-05-29 11:33:21 +0530125config SIFIVE_OTP
126 bool "SiFive eMemory OTP driver"
127 depends on MISC
128 help
129 Enable support for reading and writing the eMemory OTP on the
130 SiFive SoCs.
131
Tom Rini035e8722022-11-19 18:45:33 -0500132config SMSC_LPC47M
133 bool "LPC47M SMSC driver"
134
135config SMSC_SIO1007
136 bool "SIO1007 SMSC driver"
137
Liviu Dudau688db7f2018-09-28 13:43:31 +0100138config VEXPRESS_CONFIG
139 bool "Enable support for Arm Versatile Express config bus"
140 depends on MISC
141 help
142 If you say Y here, you will get support for accessing the
143 configuration bus on the Arm Versatile Express boards via
144 a sysreg driver.
145
Simon Glass036ca142023-09-10 13:13:02 -0600146config CBMEM_CONSOLE
147 bool "Write console output to coreboot cbmem"
148 depends on X86
149 help
150 Enables console output to the cbmem console, which is a memory
151 region set up by coreboot to hold a record of all console output.
152 Enable this only if booting from coreboot.
153
Simon Glass5b79bb22015-02-13 12:20:47 -0700154config CMD_CROS_EC
155 bool "Enable crosec command"
156 depends on CROS_EC
157 help
158 Enable command-line access to the Chrome OS EC (Embedded
159 Controller). This provides the 'crosec' command which has
160 a number of sub-commands for performing EC tasks such as
161 updating its flash, accessing a small saved context area
162 and talking to the I2C bus behind the EC (if there is one).
163
164config CROS_EC
165 bool "Enable Chrome OS EC"
166 help
167 Enable access to the Chrome OS EC. This is a separate
168 microcontroller typically available on a SPI bus on Chromebooks. It
169 provides access to the keyboard, some internal storage and may
170 control access to the battery and main PMIC depending on the
171 device. You can use the 'crosec' command to access it.
172
Simon Glass605931c2018-11-18 08:14:27 -0700173config SPL_CROS_EC
174 bool "Enable Chrome OS EC in SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400175 depends on SPL_MISC
Simon Glass605931c2018-11-18 08:14:27 -0700176 help
177 Enable access to the Chrome OS EC in SPL. This is a separate
178 microcontroller typically available on a SPI bus on Chromebooks. It
179 provides access to the keyboard, some internal storage and may
180 control access to the battery and main PMIC depending on the
181 device. You can use the 'crosec' command to access it.
182
183config TPL_CROS_EC
184 bool "Enable Chrome OS EC in TPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400185 depends on TPL_MISC
Simon Glass605931c2018-11-18 08:14:27 -0700186 help
187 Enable access to the Chrome OS EC in TPL. This is a separate
188 microcontroller typically available on a SPI bus on Chromebooks. It
189 provides access to the keyboard, some internal storage and may
190 control access to the battery and main PMIC depending on the
191 device. You can use the 'crosec' command to access it.
192
Simon Glasse7ca7da2022-04-30 00:56:53 -0600193config VPL_CROS_EC
194 bool "Enable Chrome OS EC in VPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400195 depends on VPL_MISC
Simon Glasse7ca7da2022-04-30 00:56:53 -0600196 help
197 Enable access to the Chrome OS EC in VPL. This is a separate
198 microcontroller typically available on a SPI bus on Chromebooks. It
199 provides access to the keyboard, some internal storage and may
200 control access to the battery and main PMIC depending on the
201 device. You can use the 'crosec' command to access it.
202
Simon Glass5b79bb22015-02-13 12:20:47 -0700203config CROS_EC_I2C
204 bool "Enable Chrome OS EC I2C driver"
205 depends on CROS_EC
206 help
207 Enable I2C access to the Chrome OS EC. This is used on older
208 ARM Chromebooks such as snow and spring before the standard bus
209 changed to SPI. The EC will accept commands across the I2C using
210 a special message protocol, and provide responses.
211
212config CROS_EC_LPC
213 bool "Enable Chrome OS EC LPC driver"
214 depends on CROS_EC
215 help
216 Enable I2C access to the Chrome OS EC. This is used on x86
217 Chromebooks such as link and falco. The keyboard is provided
218 through a legacy port interface, so on x86 machines the main
219 function of the EC is power and thermal management.
220
Simon Glass605931c2018-11-18 08:14:27 -0700221config SPL_CROS_EC_LPC
222 bool "Enable Chrome OS EC LPC driver in SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400223 depends on CROS_EC && SPL_MISC
Simon Glass605931c2018-11-18 08:14:27 -0700224 help
225 Enable I2C access to the Chrome OS EC. This is used on x86
226 Chromebooks such as link and falco. The keyboard is provided
227 through a legacy port interface, so on x86 machines the main
228 function of the EC is power and thermal management.
229
230config TPL_CROS_EC_LPC
231 bool "Enable Chrome OS EC LPC driver in TPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400232 depends on CROS_EC && TPL_MISC
Simon Glass605931c2018-11-18 08:14:27 -0700233 help
234 Enable I2C access to the Chrome OS EC. This is used on x86
235 Chromebooks such as link and falco. The keyboard is provided
236 through a legacy port interface, so on x86 machines the main
237 function of the EC is power and thermal management.
238
Simon Glasse7ca7da2022-04-30 00:56:53 -0600239config VPL_CROS_EC_LPC
240 bool "Enable Chrome OS EC LPC driver in VPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400241 depends on CROS_EC && VPL_MISC
Simon Glasse7ca7da2022-04-30 00:56:53 -0600242 help
243 Enable I2C access to the Chrome OS EC. This is used on x86
244 Chromebooks such as link and falco. The keyboard is provided
245 through a legacy port interface, so on x86 machines the main
246 function of the EC is power and thermal management.
247
Simon Glassc6e06692015-03-26 09:29:40 -0600248config CROS_EC_SANDBOX
249 bool "Enable Chrome OS EC sandbox driver"
250 depends on CROS_EC && SANDBOX
251 help
252 Enable a sandbox emulation of the Chrome OS EC. This supports
253 keyboard (use the -l flag to enable the LCD), verified boot context,
254 EC flash read/write/erase support and a few other things. It is
255 enough to perform a Chrome OS verified boot on sandbox.
256
Simon Glass605931c2018-11-18 08:14:27 -0700257config SPL_CROS_EC_SANDBOX
258 bool "Enable Chrome OS EC sandbox driver in SPL"
259 depends on SPL_CROS_EC && SANDBOX
260 help
261 Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
262 keyboard (use the -l flag to enable the LCD), verified boot context,
263 EC flash read/write/erase support and a few other things. It is
264 enough to perform a Chrome OS verified boot on sandbox.
265
266config TPL_CROS_EC_SANDBOX
267 bool "Enable Chrome OS EC sandbox driver in TPL"
268 depends on TPL_CROS_EC && SANDBOX
269 help
270 Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
271 keyboard (use the -l flag to enable the LCD), verified boot context,
272 EC flash read/write/erase support and a few other things. It is
273 enough to perform a Chrome OS verified boot on sandbox.
274
Simon Glasse7ca7da2022-04-30 00:56:53 -0600275config VPL_CROS_EC_SANDBOX
276 bool "Enable Chrome OS EC sandbox driver in VPL"
277 depends on VPL_CROS_EC && SANDBOX
278 help
279 Enable a sandbox emulation of the Chrome OS EC in VPL. This supports
280 keyboard (use the -l flag to enable the LCD), verified boot context,
281 EC flash read/write/erase support and a few other things. It is
282 enough to perform a Chrome OS verified boot on sandbox.
283
Simon Glass5b79bb22015-02-13 12:20:47 -0700284config CROS_EC_SPI
285 bool "Enable Chrome OS EC SPI driver"
286 depends on CROS_EC
287 help
288 Enable SPI access to the Chrome OS EC. This is used on newer
289 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
290 provides a faster and more robust interface than I2C but the bugs
291 are less interesting.
292
Simon Glass58ed3222017-05-17 03:25:02 -0600293config DS4510
294 bool "Enable support for DS4510 CPU supervisor"
295 help
296 Enable support for the Maxim DS4510 CPU supervisor. It has an
297 integrated 64-byte EEPROM, four programmable non-volatile I/O pins
298 and a configurable timer for the supervisor function. The device is
299 connected over I2C.
300
Tom Rini66fa77a2022-11-19 18:45:11 -0500301config FSL_IIM
302 bool "Enable FSL IC Identification Module (IIM) driver"
303 depends on ARCH_MX31 || ARCH_MX5
304
Peng Fanfb6166a2015-08-26 15:41:33 +0800305config FSL_SEC_MON
gaurav rana9aaea442015-02-27 09:44:22 +0530306 bool "Enable FSL SEC_MON Driver"
307 help
308 Freescale Security Monitor block is responsible for monitoring
309 system states.
310 Security Monitor can be transitioned on any security failures,
311 like software violations or hardware security violations.
Stefan Roese04b22752015-03-12 11:22:46 +0100312
Tom Rini0b58c2e2022-06-16 14:04:39 -0400313choice
314 prompt "Security monitor interaction endianess"
315 depends on FSL_SEC_MON
316 default SYS_FSL_SEC_MON_BE if PPC
317 default SYS_FSL_SEC_MON_LE
318
319config SYS_FSL_SEC_MON_LE
320 bool "Security monitor interactions are little endian"
321
322config SYS_FSL_SEC_MON_BE
323 bool "Security monitor interactions are big endian"
324
325endchoice
326
Simon Glassff418d92019-12-06 21:41:58 -0700327config IRQ
Wasim Khan55c9b9c2021-03-08 16:48:13 +0100328 bool "Interrupt controller"
Simon Glassff418d92019-12-06 21:41:58 -0700329 help
Wasim Khan55c9b9c2021-03-08 16:48:13 +0100330 This enables support for interrupt controllers, including ITSS.
Simon Glassff418d92019-12-06 21:41:58 -0700331 Some devices have extra features, such as Apollo Lake. The
332 device has its own uclass since there are several operations
333 involved.
334
Paul Burton738d8a82018-12-16 19:25:19 -0300335config JZ4780_EFUSE
336 bool "Ingenic JZ4780 eFUSE support"
337 depends on ARCH_JZ47XX
338 help
339 This selects support for the eFUSE on Ingenic JZ4780 SoCs.
340
Sean Anderson6b39d352022-04-22 14:34:18 -0400341config LS2_SFP
342 bool "Layerscape Security Fuse Processor"
343 depends on FSL_LSCH2 || ARCH_LS1021A
344 depends on MISC
345 imply DM_REGULATOR
346 help
347 This adds support for the Security Fuse Processor found on Layerscape
348 SoCs. It contains various fuses related to secure boot, including the
349 Super Root Key hash, One-Time-Programmable Master Key, Debug
350 Challenge/Response values, and others. Fuses are numbered according
351 to their four-byte offset from the start of the bank.
352
353 If you don't need to read/program fuses, say 'n'.
354
Peng Fane1872252015-08-27 14:49:05 +0800355config MXC_OCOTP
356 bool "Enable MXC OCOTP Driver"
Peng Fanc45a81a2019-07-22 01:24:55 +0000357 depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
Marcel Ziswilerf2213142019-03-25 17:24:57 +0100358 default y
Peng Fane1872252015-08-27 14:49:05 +0800359 help
360 If you say Y here, you will get support for the One Time
361 Programmable memory pages that are stored on the some
362 Freescale i.MX processors.
363
Tom Rini5a0f9d82022-11-19 18:45:28 -0500364config MXS_OCOTP
365 bool "Enable MXS OCOTP Driver"
366 depends on ARCH_MX23 || ARCH_MX28
367 help
368 If you say Y here, you will get support for the One Time
369 Programmable memory pages that are stored on the
370 Freescale i.MXS family of processors.
371
Jim Liucce4eed2022-06-24 16:24:37 +0800372config NPCM_HOST
373 bool "Enable support espi or LPC for Host"
374 depends on REGMAP && SYSCON
375 help
376 Enable NPCM BMC espi or LPC support for Host reading and writing.
377
Michael Scott92676142021-09-25 19:49:28 +0300378config SPL_MXC_OCOTP
379 bool "Enable MXC OCOTP driver in SPL"
Jean-Marie Lemetayerf17d43d2023-02-13 14:12:25 +0100380 depends on SPL_DRIVERS_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
Michael Scott92676142021-09-25 19:49:28 +0300381 default y
382 help
383 If you say Y here, you will get support for the One Time
384 Programmable memory pages, that are stored on some
385 Freescale i.MX processors, in SPL.
386
Jim Liufab2eff2022-06-07 16:33:54 +0800387config NPCM_OTP
388 bool "Nnvoton NPCM BMC On-Chip OTP Memory Support"
389 depends on (ARM && ARCH_NPCM)
Jim Liufab2eff2022-06-07 16:33:54 +0800390 help
391 Support NPCM BMC OTP memory (fuse).
392 To compile this driver as a module, choose M here: the module
393 will be called npcm_otp.
394
Peng Fand5c31832023-06-15 18:09:05 +0800395config IMX_ELE
396 bool "Enable i.MX EdgeLock Enclave MU driver and API"
Ye Lic408ed32022-07-26 16:40:49 +0800397 depends on MISC && (ARCH_IMX9 || ARCH_IMX8ULP)
398 help
399 If you say Y here to enable Message Unit driver to work with
400 Sentinel core on some NXP i.MX processors.
401
Stefan Roese4a269f22016-07-19 07:45:46 +0200402config NUVOTON_NCT6102D
403 bool "Enable Nuvoton NCT6102D Super I/O driver"
404 help
405 If you say Y here, you will get support for the Nuvoton
406 NCT6102D Super I/O driver. This can be used to enable or
407 disable the legacy UART, the watchdog or other devices
408 in the Nuvoton Super IO chips on X86 platforms.
409
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700410config P2SB
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200411 bool "Intel Primary to Sideband Bridge"
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700412 depends on X86 || SANDBOX
413 help
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200414 This enables support for the Intel Primary to Sideband Bridge,
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700415 abbreviated to P2SB. The P2SB is used to access various peripherals
416 such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
417 space. The space is segmented into different channels and peripherals
418 are accessed by device-specific means within those channels. Devices
419 should be added in the device tree as subnodes of the P2SB. A
420 Peripheral Channel Register? (PCR) API is provided to access those
421 devices - see pcr_readl(), etc.
422
423config SPL_P2SB
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200424 bool "Intel Primary to Sideband Bridge in SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400425 depends on SPL_MISC && (X86 || SANDBOX)
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700426 help
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200427 The Primary to Sideband Bridge is used to access various peripherals
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700428 through memory-mapped I/O in a large chunk of PCI space. The space is
429 segmented into different channels and peripherals are accessed by
430 device-specific means within those channels. Devices should be added
431 in the device tree as subnodes of the p2sb.
432
433config TPL_P2SB
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200434 bool "Intel Primary to Sideband Bridge in TPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400435 depends on TPL_MISC && (X86 || SANDBOX)
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700436 help
Wolfgang Wallnerf43b0832020-07-01 13:37:23 +0200437 The Primary to Sideband Bridge is used to access various peripherals
Simon Glass2ee1f6a2019-12-06 21:41:55 -0700438 through memory-mapped I/O in a large chunk of PCI space. The space is
439 segmented into different channels and peripherals are accessed by
440 device-specific means within those channels. Devices should be added
441 in the device tree as subnodes of the p2sb.
442
Simon Glassc9795172016-01-21 19:43:31 -0700443config PWRSEQ
444 bool "Enable power-sequencing drivers"
445 depends on DM
446 help
447 Power-sequencing drivers provide support for controlling power for
448 devices. They are typically referenced by a phandle from another
449 device. When the device is started up, its power sequence can be
450 initiated.
451
452config SPL_PWRSEQ
453 bool "Enable power-sequencing drivers for SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400454 depends on SPL_MISC && PWRSEQ
Simon Glassc9795172016-01-21 19:43:31 -0700455 help
456 Power-sequencing drivers provide support for controlling power for
457 devices. They are typically referenced by a phandle from another
458 device. When the device is started up, its power sequence can be
459 initiated.
460
Stefan Roese04b22752015-03-12 11:22:46 +0100461config PCA9551_LED
462 bool "Enable PCA9551 LED driver"
463 help
464 Enable driver for PCA9551 LED controller. This controller
465 is connected via I2C. So I2C needs to be enabled.
466
467config PCA9551_I2C_ADDR
468 hex "I2C address of PCA9551 LED controller"
469 depends on PCA9551_LED
470 default 0x60
471 help
472 The I2C address of the PCA9551 LED controller.
Simon Glass14000862015-06-23 15:39:13 -0600473
Patrick Delaunay0c4656b2018-05-17 15:24:06 +0200474config STM32MP_FUSE
475 bool "Enable STM32MP fuse wrapper providing the fuse API"
476 depends on ARCH_STM32MP && MISC
477 default y if CMD_FUSE
478 help
479 If you say Y here, you will get support for the fuse API (OTP)
480 for STM32MP architecture.
481 This API is needed for CMD_FUSE.
482
Harsha Vardhan V Mcc7e7fd2025-03-19 14:17:13 +0530483config K3_FUSE
484 bool "Enable TI K3 fuse wrapper providing the fuse API"
485 depends on MISC && CMD_FUSE && CMD_FUSE_WRITEBUFF
486 help
487 If you say Y here, you will get support for the fuse API (OTP)
488 for TI K3 architecture.
489
Christophe Kerello275f7062017-09-13 18:00:08 +0200490config STM32_RCC
491 bool "Enable RCC driver for the STM32 SoC's family"
Trevor Woerner2bcc1ed2020-05-06 08:02:42 -0400492 depends on (ARCH_STM32 || ARCH_STM32MP) && MISC
Christophe Kerello275f7062017-09-13 18:00:08 +0200493 help
494 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
495 block) is responsible of the management of the clock and reset
496 generation.
497 This driver is similar to an MFD driver in the Linux kernel.
498
Stephen Warrenf6417002016-09-13 10:45:57 -0600499config TEGRA_CAR
500 bool "Enable support for the Tegra CAR driver"
501 depends on TEGRA_NO_BPMP
502 help
503 The Tegra CAR (Clock and Reset Controller) is a HW module that
504 controls almost all clocks and resets in a Tegra SoC.
505
Stephen Warrena2148922016-08-08 09:41:34 -0600506config TEGRA186_BPMP
507 bool "Enable support for the Tegra186 BPMP driver"
508 depends on TEGRA186
509 help
510 The Tegra BPMP (Boot and Power Management Processor) is a separate
511 auxiliary CPU embedded into Tegra to perform power management work,
512 and controls related features such as clocks, resets, power domains,
513 PMIC I2C bus, etc. This driver provides the core low-level
514 communication path by which feature-specific drivers (such as clock)
515 can make requests to the BPMP. This driver is similar to an MFD
516 driver in the Linux kernel.
517
Simon Glass4bf89722020-12-23 08:11:18 -0700518config TEST_DRV
519 bool "Enable support for test drivers"
520 default y if SANDBOX
521 help
522 This enables drivers and uclasses that provides a way of testing the
523 operations of memory allocation and driver/uclass methods in driver
524 model. This should only be enabled for testing as it is not useful for
525 anything else.
526
Marek Behúnea51ee52024-04-04 09:51:03 +0200527config TURRIS_OMNIA_MCU
528 bool "Enable Turris Omnia MCU driver"
529 depends on DM_I2C
530 depends on DM_GPIO
Marek Behún4f552fe2024-04-04 09:51:06 +0200531 depends on DM_RNG
Marek Behúnea51ee52024-04-04 09:51:03 +0200532 depends on SYSRESET
533 default y if TARGET_TURRIS_OMNIA
534 help
535 This enables support for Turris Omnia MCU connected GPIOs and
536 board power off.
537
Marek Vasut16637b42022-04-10 06:27:14 +0200538config USB_HUB_USB251XB
539 tristate "USB251XB Hub Controller Configuration Driver"
540 depends on I2C
541 help
542 This option enables support for configuration via SMBus of the
543 Microchip USB251x/xBi USB 2.0 Hub Controller series. Configuration
544 parameters may be set in devicetree or platform data.
545 Say Y or M here if you need to configure such a device via SMBus.
546
Adam Fordc8cdce72018-08-06 14:26:50 -0500547config TWL4030_LED
548 bool "Enable TWL4030 LED controller"
549 help
550 Enable this to add support for the TWL4030 LED controller.
551
Stefan Roeseba019ed2016-01-19 14:05:10 +0100552config WINBOND_W83627
553 bool "Enable Winbond Super I/O driver"
554 help
555 If you say Y here, you will get support for the Winbond
556 W83627 Super I/O driver. This can be used to enable the
557 legacy UART or other devices in the Winbond Super IO chips
558 on X86 platforms.
559
Miao Yan4fcd7f22016-05-22 19:37:14 -0700560config QFW
561 bool
562 help
Asherah Connor4ffa95d2021-03-19 18:21:40 +1100563 Hidden option to enable QEMU fw_cfg interface and uclass. This will
564 be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
565
Heinrich Schuchardt223605f2023-12-19 16:04:00 +0100566config QFW_ACPI
567 bool
568 default y
569 depends on QFW && GENERATE_ACPI_TABLE && !SANDBOX
570 help
571 Hidden option to read ACPI tables from QEMU.
572
Asherah Connor4ffa95d2021-03-19 18:21:40 +1100573config QFW_PIO
574 bool
575 depends on QFW
576 help
577 Hidden option to enable PIO QEMU fw_cfg interface. This will be
578 selected by the appropriate QEMU board.
Miao Yan4fcd7f22016-05-22 19:37:14 -0700579
Asherah Connorf0c0e542021-03-19 18:21:42 +1100580config QFW_MMIO
581 bool
582 depends on QFW
583 help
584 Hidden option to enable MMIO QEMU fw_cfg interface. This will be
585 selected by the appropriate QEMU board.
586
Heinrich Schuchardt08d931a2023-12-23 02:03:34 +0100587config QFW_SMBIOS
588 bool
589 default y
Raymond Maoc83c3762024-12-06 14:54:27 -0800590 depends on QFW && SMBIOS && !SANDBOX && !SYSINFO_SMBIOS
Heinrich Schuchardte191ead2025-04-07 08:44:24 +0200591 select BLOBLIST
Heinrich Schuchardt08d931a2023-12-23 02:03:34 +0100592 help
593 Hidden option to read SMBIOS tables from QEMU.
594
mario.six@gdsys.cc7559ac42016-06-22 15:14:16 +0200595config I2C_EEPROM
596 bool "Enable driver for generic I2C-attached EEPROMs"
597 depends on MISC
598 help
599 Enable a generic driver for EEPROMs attached via I2C.
Adam Ford5664f832017-08-13 09:00:28 -0500600
Wenyou Yangf791d562017-09-06 13:08:14 +0800601
602config SPL_I2C_EEPROM
603 bool "Enable driver for generic I2C-attached EEPROMs for SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400604 depends on SPL_MISC
Wenyou Yangf791d562017-09-06 13:08:14 +0800605 help
606 This option is an SPL-variant of the I2C_EEPROM option.
607 See the help of I2C_EEPROM for details.
608
Adam Ford5664f832017-08-13 09:00:28 -0500609config SYS_I2C_EEPROM_ADDR
610 hex "Chip address of the EEPROM device"
Tom Rinifaed5672021-08-17 17:59:45 -0400611 depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
Tom Rinif18679c2023-08-02 11:09:43 -0400612 default 0x0
Adam Ford5664f832017-08-13 09:00:28 -0500613
Tom Rinifaed5672021-08-17 17:59:45 -0400614if I2C_EEPROM
Adam Ford5664f832017-08-13 09:00:28 -0500615
616config SYS_I2C_EEPROM_ADDR_OVERFLOW
617 hex "EEPROM Address Overflow"
Tom Rinif0599552021-12-11 14:55:47 -0500618 default 0x0
Adam Ford5664f832017-08-13 09:00:28 -0500619 help
620 EEPROM chips that implement "address overflow" are ones
621 like Catalyst 24WC04/08/16 which has 9/10/11 bits of
622 address and the extra bits end up in the "chip address" bit
623 slots. This makes a 24WC08 (1Kbyte) chip look like four 256
624 byte chips.
625
626endif
627
Mario Six7f504a02018-04-27 14:53:33 +0200628config GDSYS_RXAUI_CTRL
629 bool "Enable gdsys RXAUI control driver"
630 depends on MISC
631 help
632 Support gdsys FPGA's RXAUI control.
Mario Six0cafb652018-07-31 14:24:15 +0200633
634config GDSYS_IOEP
635 bool "Enable gdsys IOEP driver"
636 depends on MISC
637 help
638 Support gdsys FPGA's IO endpoint driver.
Mario Six7fdcf282018-08-06 10:23:46 +0200639
640config MPC83XX_SERDES
641 bool "Enable MPC83xx serdes driver"
642 depends on MISC
643 help
644 Support for serdes found on MPC83xx SoCs.
645
Tien Fong Chee5ca878b2018-07-06 16:28:03 +0800646config FS_LOADER
647 bool "Enable loader driver for file system"
648 help
649 This is file system generic loader which can be used to load
650 the file image from the storage into target such as memory.
651
652 The consumer driver would then use this loader to program whatever,
653 ie. the FPGA device.
654
Keerthyfe8f6092022-01-27 13:16:53 +0100655config SPL_FS_LOADER
Alexander Gendin1c1a8842023-11-20 20:21:51 +0000656 bool "Enable loader driver for file system in SPL"
Tom Rini0f311f22022-05-10 12:51:47 -0400657 depends on SPL
Keerthyfe8f6092022-01-27 13:16:53 +0100658 help
659 This is file system generic loader which can be used to load
660 the file image from the storage into target such as memory.
661
662 The consumer driver would then use this loader to program whatever,
663 ie. the FPGA device.
664
Mario Six8862f452018-10-04 09:00:54 +0200665config GDSYS_SOC
666 bool "Enable gdsys SOC driver"
667 depends on MISC
668 help
669 Support for gdsys IHS SOC, a simple bus associated with each gdsys
670 IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
671 register maps are contained within the FPGA's register map.
672
Mario Six1a9d43f2018-10-04 09:00:55 +0200673config IHS_FPGA
674 bool "Enable IHS FPGA driver"
675 depends on MISC
676 help
677 Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
678 gdsys devices, which supply the majority of the functionality offered
679 by the devices. This driver supports both CON and CPU variants of the
680 devices, depending on the device tree entry.
Tero Kristof81f4cd2020-02-14 11:18:15 +0200681config ESM_K3
682 bool "Enable K3 ESM driver"
683 depends on ARCH_K3
684 help
685 Support ESM (Error Signaling Module) on TI K3 SoCs.
Mario Six1a9d43f2018-10-04 09:00:55 +0200686
Eugen Hristev3bd56102019-10-09 09:23:39 +0000687config MICROCHIP_FLEXCOM
688 bool "Enable Microchip Flexcom driver"
689 depends on MISC
690 help
691 The Atmel Flexcom is just a wrapper which embeds a SPI controller,
692 an I2C controller and an USART.
693 Only one function can be used at a time and is chosen at boot time
694 according to the device tree.
695
Tero Kristo887dde52019-10-24 15:00:46 +0530696config K3_AVS0
697 depends on ARCH_K3 && SPL_DM_REGULATOR
698 bool "AVS class 0 support for K3 devices"
699 help
700 K3 devices have the optimized voltage values for the main voltage
701 domains stored in efuse within the VTM IP. This driver reads the
702 optimized voltage from the efuse, so that it can be programmed
703 to the PMIC on board.
704
Tero Kristo1444e112020-02-14 11:18:16 +0200705config ESM_PMIC
706 bool "Enable PMIC ESM driver"
707 depends on DM_PMIC
708 help
709 Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
710 typically to reboot the board in error condition.
711
Tom Rini05b419e2021-12-11 14:55:49 -0500712config FSL_IFC
713 bool
714
Michael Walle2184cc62022-02-25 18:06:24 +0530715config SL28CPLD
716 bool "Enable Kontron sl28cpld multi-function driver"
717 depends on DM_I2C
718 help
719 Support for the Kontron sl28cpld management controller. This is
720 the base driver which provides common access methods for the
721 sub-drivers.
722
Wan Yee Laue249d542024-02-05 11:47:16 +0800723config SPL_SOCFPGA_DT_REG
724 bool "Enable register setting from device tree in SPL"
725 depends on SPL
726 help
727 Enable register setting from device tree. This also
728 provides user a clean interface and all register settings are
729 centralized in one place, device tree.
Masahiro Yamadacc85b7b2015-07-26 02:46:26 +0900730endmenu