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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * Cirrus Logic CS8900A Ethernet
3 *
wdenk4fc95692003-02-28 00:49:47 +00004 * (C) 2003 Wolfgang Denk, wd@denx.de
5 * Extension to synchronize ethaddr environment variable
6 * against value in EEPROM
7 *
wdenkc6097192002-11-03 00:24:07 +00008 * (C) Copyright 2002
9 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
10 * Marius Groeger <mgroeger@sysgo.de>
11 *
12 * Copyright (C) 1999 Ben Williamson <benw@pobox.com>
13 *
14 * See file CREDITS for list of people who contributed to this
15 * project.
16 *
17 * This program is loaded into SRAM in bootstrap mode, where it waits
18 * for commands on UART1 to read and write memory, jump to code etc.
19 * A design goal for this program is to be entirely independent of the
20 * target board. Anything with a CL-PS7111 or EP7211 should be able to run
21 * this code in bootstrap mode. All the board specifics can be handled on
22 * the host.
23 *
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License as published by
26 * the Free Software Foundation; either version 2 of the License, or
27 * (at your option) any later version.
28 *
29 * This program is distributed in the hope that it will be useful,
30 * but WITHOUT ANY WARRANTY; without even the implied warranty of
31 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
32 * GNU General Public License for more details.
33 *
34 * You should have received a copy of the GNU General Public License
35 * along with this program; if not, write to the Free Software
36 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
37 */
38
39#include <common.h>
40#include <command.h>
41#include "cs8900.h"
42#include <net.h>
43
44#ifdef CONFIG_DRIVER_CS8900
45
46#if (CONFIG_COMMANDS & CFG_CMD_NET)
47
wdenk4ea537d2003-12-07 18:32:37 +000048#undef DEBUG
wdenkc6097192002-11-03 00:24:07 +000049
50/* packet page register access functions */
51
52#ifdef CS8900_BUS32
53/* we don't need 16 bit initialisation on 32 bit bus */
54#define get_reg_init_bus(x) get_reg((x))
55#else
wdenk4fc95692003-02-28 00:49:47 +000056static unsigned short get_reg_init_bus (int regno)
wdenkc6097192002-11-03 00:24:07 +000057{
wdenk4fc95692003-02-28 00:49:47 +000058 /* force 16 bit busmode */
59 volatile unsigned char c;
60
61 c = CS8900_BUS16_0;
62 c = CS8900_BUS16_1;
63 c = CS8900_BUS16_0;
64 c = CS8900_BUS16_1;
65 c = CS8900_BUS16_0;
wdenkc6097192002-11-03 00:24:07 +000066
wdenk4fc95692003-02-28 00:49:47 +000067 CS8900_PPTR = regno;
68 return (unsigned short) CS8900_PDATA;
wdenkc6097192002-11-03 00:24:07 +000069}
70#endif
71
wdenk4fc95692003-02-28 00:49:47 +000072static unsigned short get_reg (int regno)
wdenkc6097192002-11-03 00:24:07 +000073{
wdenk4fc95692003-02-28 00:49:47 +000074 CS8900_PPTR = regno;
75 return (unsigned short) CS8900_PDATA;
wdenkc6097192002-11-03 00:24:07 +000076}
77
78
wdenk4fc95692003-02-28 00:49:47 +000079static void put_reg (int regno, unsigned short val)
wdenkc6097192002-11-03 00:24:07 +000080{
wdenk4fc95692003-02-28 00:49:47 +000081 CS8900_PPTR = regno;
82 CS8900_PDATA = val;
wdenkc6097192002-11-03 00:24:07 +000083}
84
wdenk4fc95692003-02-28 00:49:47 +000085static void eth_reset (void)
wdenkc6097192002-11-03 00:24:07 +000086{
wdenk4fc95692003-02-28 00:49:47 +000087 int tmo;
88 unsigned short us;
wdenkc6097192002-11-03 00:24:07 +000089
wdenk4fc95692003-02-28 00:49:47 +000090 /* reset NIC */
91 put_reg (PP_SelfCTL, get_reg (PP_SelfCTL) | PP_SelfCTL_Reset);
wdenkc6097192002-11-03 00:24:07 +000092
wdenk4fc95692003-02-28 00:49:47 +000093 /* wait for 200ms */
94 udelay (200000);
95 /* Wait until the chip is reset */
wdenkc6097192002-11-03 00:24:07 +000096
wdenk4fc95692003-02-28 00:49:47 +000097 tmo = get_timer (0) + 1 * CFG_HZ;
98 while ((((us = get_reg_init_bus (PP_SelfSTAT)) & PP_SelfSTAT_InitD) == 0)
99 && tmo < get_timer (0))
100 /*NOP*/;
wdenkc6097192002-11-03 00:24:07 +0000101}
102
wdenk4ea537d2003-12-07 18:32:37 +0000103static void eth_reginit (void)
104{
105 /* receive only error free packets addressed to this card */
106 put_reg (PP_RxCTL, PP_RxCTL_IA | PP_RxCTL_Broadcast | PP_RxCTL_RxOK);
107 /* do not generate any interrupts on receive operations */
108 put_reg (PP_RxCFG, 0);
109 /* do not generate any interrupts on transmit operations */
110 put_reg (PP_TxCFG, 0);
111 /* do not generate any interrupts on buffer operations */
112 put_reg (PP_BufCFG, 0);
113 /* enable transmitter/receiver mode */
114 put_reg (PP_LineCTL, PP_LineCTL_Rx | PP_LineCTL_Tx);
115}
116
wdenk4fc95692003-02-28 00:49:47 +0000117void cs8900_get_enetaddr (uchar * addr)
wdenkc6097192002-11-03 00:24:07 +0000118{
wdenk4fc95692003-02-28 00:49:47 +0000119 int i;
120 unsigned char env_enetaddr[6];
121 char *tmp = getenv ("ethaddr");
122 char *end;
123
124 for (i=0; i<6; i++) {
125 env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
126 if (tmp)
127 tmp = (*end) ? end+1 : end;
128 }
129
130 /* verify chip id */
131 if (get_reg_init_bus (PP_ChipID) != 0x630e)
132 return;
133 eth_reset ();
134 if ((get_reg (PP_SelfST) & (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) ==
135 (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) {
136
137 /* Load the MAC from EEPROM */
138 for (i = 0; i < 6 / 2; i++) {
139 unsigned int Addr;
140
141 Addr = get_reg (PP_IA + i * 2);
142 addr[i * 2] = Addr & 0xFF;
143 addr[i * 2 + 1] = Addr >> 8;
144 }
145
146 if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6) != 0 &&
147 memcmp(env_enetaddr, addr, 6) != 0) {
148 printf ("\nWarning: MAC addresses don't match:\n");
149 printf ("\tHW MAC address: "
150 "%02X:%02X:%02X:%02X:%02X:%02X\n",
151 addr[0], addr[1],
152 addr[2], addr[3],
153 addr[4], addr[5] );
154 printf ("\t\"ethaddr\" value: "
155 "%02X:%02X:%02X:%02X:%02X:%02X\n",
156 env_enetaddr[0], env_enetaddr[1],
157 env_enetaddr[2], env_enetaddr[3],
158 env_enetaddr[4], env_enetaddr[5]) ;
159 debug ("### Set MAC addr from environment\n");
160 memcpy (addr, env_enetaddr, 6);
161 }
162 if (!tmp) {
163 char ethaddr[20];
164 sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
165 addr[0], addr[1],
166 addr[2], addr[3],
167 addr[4], addr[5]) ;
168 debug ("### Set environment from HW MAC addr = \"%s\"\n", ethaddr);
169 setenv ("ethaddr", ethaddr);
170 }
171
wdenkc6097192002-11-03 00:24:07 +0000172 }
wdenkc6097192002-11-03 00:24:07 +0000173}
174
wdenk4fc95692003-02-28 00:49:47 +0000175void eth_halt (void)
wdenkc6097192002-11-03 00:24:07 +0000176{
wdenk4fc95692003-02-28 00:49:47 +0000177 /* disable transmitter/receiver mode */
178 put_reg (PP_LineCTL, 0);
wdenkc6097192002-11-03 00:24:07 +0000179
wdenk4fc95692003-02-28 00:49:47 +0000180 /* "shutdown" to show ChipID or kernel wouldn't find he cs8900 ... */
181 get_reg_init_bus (PP_ChipID);
wdenkc6097192002-11-03 00:24:07 +0000182}
183
wdenk4fc95692003-02-28 00:49:47 +0000184int eth_init (bd_t * bd)
wdenkc6097192002-11-03 00:24:07 +0000185{
186
wdenk4fc95692003-02-28 00:49:47 +0000187 /* verify chip id */
188 if (get_reg_init_bus (PP_ChipID) != 0x630e) {
189 printf ("CS8900 Ethernet chip not found?!\n");
190 return 0;
191 }
wdenkc6097192002-11-03 00:24:07 +0000192
wdenk4fc95692003-02-28 00:49:47 +0000193 eth_reset ();
194 /* set the ethernet address */
195 put_reg (PP_IA + 0, bd->bi_enetaddr[0] | (bd->bi_enetaddr[1] << 8));
196 put_reg (PP_IA + 2, bd->bi_enetaddr[2] | (bd->bi_enetaddr[3] << 8));
197 put_reg (PP_IA + 4, bd->bi_enetaddr[4] | (bd->bi_enetaddr[5] << 8));
wdenkc6097192002-11-03 00:24:07 +0000198
wdenk4ea537d2003-12-07 18:32:37 +0000199 eth_reginit ();
wdenk4fc95692003-02-28 00:49:47 +0000200 return 0;
wdenkc6097192002-11-03 00:24:07 +0000201}
202
203/* Get a data block via Ethernet */
wdenk4fc95692003-02-28 00:49:47 +0000204extern int eth_rx (void)
wdenkc6097192002-11-03 00:24:07 +0000205{
wdenk4fc95692003-02-28 00:49:47 +0000206 int i;
207 unsigned short rxlen;
208 unsigned short *addr;
209 unsigned short status;
wdenkc6097192002-11-03 00:24:07 +0000210
wdenk4fc95692003-02-28 00:49:47 +0000211 status = get_reg (PP_RER);
wdenkc6097192002-11-03 00:24:07 +0000212
wdenk4fc95692003-02-28 00:49:47 +0000213 if ((status & PP_RER_RxOK) == 0)
214 return 0;
wdenkc6097192002-11-03 00:24:07 +0000215
wdenk4fc95692003-02-28 00:49:47 +0000216 status = CS8900_RTDATA; /* stat */
217 rxlen = CS8900_RTDATA; /* len */
wdenkc6097192002-11-03 00:24:07 +0000218
wdenk4ea537d2003-12-07 18:32:37 +0000219#ifdef DEBUG
wdenk4fc95692003-02-28 00:49:47 +0000220 if (rxlen > PKTSIZE_ALIGN + PKTALIGN)
221 printf ("packet too big!\n");
wdenk4ea537d2003-12-07 18:32:37 +0000222#endif
wdenk4fc95692003-02-28 00:49:47 +0000223 for (addr = (unsigned short *) NetRxPackets[0], i = rxlen >> 1; i > 0;
224 i--)
225 *addr++ = CS8900_RTDATA;
226 if (rxlen & 1)
227 *addr++ = CS8900_RTDATA;
wdenkc6097192002-11-03 00:24:07 +0000228
wdenk4fc95692003-02-28 00:49:47 +0000229 /* Pass the packet up to the protocol layers. */
230 NetReceive (NetRxPackets[0], rxlen);
wdenkc6097192002-11-03 00:24:07 +0000231
wdenk4fc95692003-02-28 00:49:47 +0000232 return rxlen;
wdenkc6097192002-11-03 00:24:07 +0000233}
234
235/* Send a data block via Ethernet. */
wdenk4fc95692003-02-28 00:49:47 +0000236extern int eth_send (volatile void *packet, int length)
wdenkc6097192002-11-03 00:24:07 +0000237{
wdenk4fc95692003-02-28 00:49:47 +0000238 volatile unsigned short *addr;
239 int tmo;
240 unsigned short s;
wdenkc6097192002-11-03 00:24:07 +0000241
242retry:
wdenk4fc95692003-02-28 00:49:47 +0000243 /* initiate a transmit sequence */
244 CS8900_TxCMD = PP_TxCmd_TxStart_Full;
245 CS8900_TxLEN = length;
wdenkc6097192002-11-03 00:24:07 +0000246
wdenk4fc95692003-02-28 00:49:47 +0000247 /* Test to see if the chip has allocated memory for the packet */
248 if ((get_reg (PP_BusSTAT) & PP_BusSTAT_TxRDY) == 0) {
249 /* Oops... this should not happen! */
wdenk4ea537d2003-12-07 18:32:37 +0000250#ifdef DEBUG
wdenk4fc95692003-02-28 00:49:47 +0000251 printf ("cs: unable to send packet; retrying...\n");
wdenk4ea537d2003-12-07 18:32:37 +0000252#endif
wdenk4fc95692003-02-28 00:49:47 +0000253 for (tmo = get_timer (0) + 5 * CFG_HZ; get_timer (0) < tmo;)
254 /*NOP*/;
255 eth_reset ();
wdenk4ea537d2003-12-07 18:32:37 +0000256 eth_reginit ();
wdenk4fc95692003-02-28 00:49:47 +0000257 goto retry;
258 }
wdenkc6097192002-11-03 00:24:07 +0000259
wdenk4fc95692003-02-28 00:49:47 +0000260 /* Write the contents of the packet */
261 /* assume even number of bytes */
262 for (addr = packet; length > 0; length -= 2)
263 CS8900_RTDATA = *addr++;
wdenkc6097192002-11-03 00:24:07 +0000264
wdenk4fc95692003-02-28 00:49:47 +0000265 /* wait for transfer to succeed */
266 tmo = get_timer (0) + 5 * CFG_HZ;
267 while ((s = get_reg (PP_TER) & ~0x1F) == 0) {
268 if (get_timer (0) >= tmo)
269 break;
270 }
wdenkc6097192002-11-03 00:24:07 +0000271
wdenk4fc95692003-02-28 00:49:47 +0000272 /* nothing */ ;
273 if ((s & (PP_TER_CRS | PP_TER_TxOK)) != PP_TER_TxOK) {
wdenk4ea537d2003-12-07 18:32:37 +0000274#ifdef DEBUG
wdenk4fc95692003-02-28 00:49:47 +0000275 printf ("\ntransmission error %#x\n", s);
wdenk4ea537d2003-12-07 18:32:37 +0000276#endif
wdenk4fc95692003-02-28 00:49:47 +0000277 }
wdenkc6097192002-11-03 00:24:07 +0000278
wdenk4fc95692003-02-28 00:49:47 +0000279 return 0;
wdenkc6097192002-11-03 00:24:07 +0000280}
281
wdenk1fe2c702003-03-06 21:55:29 +0000282static void cs8900_e2prom_ready(void)
283{
284 while(get_reg(PP_SelfST) & SI_BUSY);
285}
286
287/***********************************************************/
288/* read a 16-bit word out of the EEPROM */
289/***********************************************************/
290
291int cs8900_e2prom_read(unsigned char addr, unsigned short *value)
292{
293 cs8900_e2prom_ready();
294 put_reg(PP_EECMD, EEPROM_READ_CMD | addr);
295 cs8900_e2prom_ready();
296 *value = get_reg(PP_EEData);
297
298 return 0;
299}
300
301
302/***********************************************************/
303/* write a 16-bit word into the EEPROM */
304/***********************************************************/
305
wdenk6b58f332003-03-14 20:47:52 +0000306int cs8900_e2prom_write(unsigned char addr, unsigned short value)
wdenk1fe2c702003-03-06 21:55:29 +0000307{
308 cs8900_e2prom_ready();
309 put_reg(PP_EECMD, EEPROM_WRITE_EN);
310 cs8900_e2prom_ready();
311 put_reg(PP_EEData, value);
312 put_reg(PP_EECMD, EEPROM_WRITE_CMD | addr);
313 cs8900_e2prom_ready();
314 put_reg(PP_EECMD, EEPROM_WRITE_DIS);
315 cs8900_e2prom_ready();
316
wdenk6b58f332003-03-14 20:47:52 +0000317 return 0;
wdenk1fe2c702003-03-06 21:55:29 +0000318}
319
wdenk4fc95692003-02-28 00:49:47 +0000320#endif /* COMMANDS & CFG_NET */
wdenkc6097192002-11-03 00:24:07 +0000321
wdenk4fc95692003-02-28 00:49:47 +0000322#endif /* CONFIG_DRIVER_CS8900 */