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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * Cirrus Logic CS8900A Ethernet
3 *
wdenk4fc95692003-02-28 00:49:47 +00004 * (C) 2003 Wolfgang Denk, wd@denx.de
5 * Extension to synchronize ethaddr environment variable
6 * against value in EEPROM
7 *
wdenkc6097192002-11-03 00:24:07 +00008 * (C) Copyright 2002
9 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
10 * Marius Groeger <mgroeger@sysgo.de>
11 *
12 * Copyright (C) 1999 Ben Williamson <benw@pobox.com>
13 *
14 * See file CREDITS for list of people who contributed to this
15 * project.
16 *
17 * This program is loaded into SRAM in bootstrap mode, where it waits
18 * for commands on UART1 to read and write memory, jump to code etc.
19 * A design goal for this program is to be entirely independent of the
20 * target board. Anything with a CL-PS7111 or EP7211 should be able to run
21 * this code in bootstrap mode. All the board specifics can be handled on
22 * the host.
23 *
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License as published by
26 * the Free Software Foundation; either version 2 of the License, or
27 * (at your option) any later version.
28 *
29 * This program is distributed in the hope that it will be useful,
30 * but WITHOUT ANY WARRANTY; without even the implied warranty of
31 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
32 * GNU General Public License for more details.
33 *
34 * You should have received a copy of the GNU General Public License
35 * along with this program; if not, write to the Free Software
36 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
37 */
38
39#include <common.h>
40#include <command.h>
41#include "cs8900.h"
42#include <net.h>
43
44#ifdef CONFIG_DRIVER_CS8900
45
46#if (CONFIG_COMMANDS & CFG_CMD_NET)
47
48
49/* packet page register access functions */
50
51#ifdef CS8900_BUS32
52/* we don't need 16 bit initialisation on 32 bit bus */
53#define get_reg_init_bus(x) get_reg((x))
54#else
wdenk4fc95692003-02-28 00:49:47 +000055static unsigned short get_reg_init_bus (int regno)
wdenkc6097192002-11-03 00:24:07 +000056{
wdenk4fc95692003-02-28 00:49:47 +000057 /* force 16 bit busmode */
58 volatile unsigned char c;
59
60 c = CS8900_BUS16_0;
61 c = CS8900_BUS16_1;
62 c = CS8900_BUS16_0;
63 c = CS8900_BUS16_1;
64 c = CS8900_BUS16_0;
wdenkc6097192002-11-03 00:24:07 +000065
wdenk4fc95692003-02-28 00:49:47 +000066 CS8900_PPTR = regno;
67 return (unsigned short) CS8900_PDATA;
wdenkc6097192002-11-03 00:24:07 +000068}
69#endif
70
wdenk4fc95692003-02-28 00:49:47 +000071static unsigned short get_reg (int regno)
wdenkc6097192002-11-03 00:24:07 +000072{
wdenk4fc95692003-02-28 00:49:47 +000073 CS8900_PPTR = regno;
74 return (unsigned short) CS8900_PDATA;
wdenkc6097192002-11-03 00:24:07 +000075}
76
77
wdenk4fc95692003-02-28 00:49:47 +000078static void put_reg (int regno, unsigned short val)
wdenkc6097192002-11-03 00:24:07 +000079{
wdenk4fc95692003-02-28 00:49:47 +000080 CS8900_PPTR = regno;
81 CS8900_PDATA = val;
wdenkc6097192002-11-03 00:24:07 +000082}
83
wdenk4fc95692003-02-28 00:49:47 +000084static void eth_reset (void)
wdenkc6097192002-11-03 00:24:07 +000085{
wdenk4fc95692003-02-28 00:49:47 +000086 int tmo;
87 unsigned short us;
wdenkc6097192002-11-03 00:24:07 +000088
wdenk4fc95692003-02-28 00:49:47 +000089 /* reset NIC */
90 put_reg (PP_SelfCTL, get_reg (PP_SelfCTL) | PP_SelfCTL_Reset);
wdenkc6097192002-11-03 00:24:07 +000091
wdenk4fc95692003-02-28 00:49:47 +000092 /* wait for 200ms */
93 udelay (200000);
94 /* Wait until the chip is reset */
wdenkc6097192002-11-03 00:24:07 +000095
wdenk4fc95692003-02-28 00:49:47 +000096 tmo = get_timer (0) + 1 * CFG_HZ;
97 while ((((us = get_reg_init_bus (PP_SelfSTAT)) & PP_SelfSTAT_InitD) == 0)
98 && tmo < get_timer (0))
99 /*NOP*/;
wdenkc6097192002-11-03 00:24:07 +0000100}
101
wdenk4fc95692003-02-28 00:49:47 +0000102void cs8900_get_enetaddr (uchar * addr)
wdenkc6097192002-11-03 00:24:07 +0000103{
wdenk4fc95692003-02-28 00:49:47 +0000104 int i;
105 unsigned char env_enetaddr[6];
106 char *tmp = getenv ("ethaddr");
107 char *end;
108
109 for (i=0; i<6; i++) {
110 env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
111 if (tmp)
112 tmp = (*end) ? end+1 : end;
113 }
114
115 /* verify chip id */
116 if (get_reg_init_bus (PP_ChipID) != 0x630e)
117 return;
118 eth_reset ();
119 if ((get_reg (PP_SelfST) & (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) ==
120 (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) {
121
122 /* Load the MAC from EEPROM */
123 for (i = 0; i < 6 / 2; i++) {
124 unsigned int Addr;
125
126 Addr = get_reg (PP_IA + i * 2);
127 addr[i * 2] = Addr & 0xFF;
128 addr[i * 2 + 1] = Addr >> 8;
129 }
130
131 if (memcmp(env_enetaddr, "\0\0\0\0\0\0", 6) != 0 &&
132 memcmp(env_enetaddr, addr, 6) != 0) {
133 printf ("\nWarning: MAC addresses don't match:\n");
134 printf ("\tHW MAC address: "
135 "%02X:%02X:%02X:%02X:%02X:%02X\n",
136 addr[0], addr[1],
137 addr[2], addr[3],
138 addr[4], addr[5] );
139 printf ("\t\"ethaddr\" value: "
140 "%02X:%02X:%02X:%02X:%02X:%02X\n",
141 env_enetaddr[0], env_enetaddr[1],
142 env_enetaddr[2], env_enetaddr[3],
143 env_enetaddr[4], env_enetaddr[5]) ;
144 debug ("### Set MAC addr from environment\n");
145 memcpy (addr, env_enetaddr, 6);
146 }
147 if (!tmp) {
148 char ethaddr[20];
149 sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
150 addr[0], addr[1],
151 addr[2], addr[3],
152 addr[4], addr[5]) ;
153 debug ("### Set environment from HW MAC addr = \"%s\"\n", ethaddr);
154 setenv ("ethaddr", ethaddr);
155 }
156
wdenkc6097192002-11-03 00:24:07 +0000157 }
wdenkc6097192002-11-03 00:24:07 +0000158}
159
wdenk4fc95692003-02-28 00:49:47 +0000160void eth_halt (void)
wdenkc6097192002-11-03 00:24:07 +0000161{
wdenk4fc95692003-02-28 00:49:47 +0000162 /* disable transmitter/receiver mode */
163 put_reg (PP_LineCTL, 0);
wdenkc6097192002-11-03 00:24:07 +0000164
wdenk4fc95692003-02-28 00:49:47 +0000165 /* "shutdown" to show ChipID or kernel wouldn't find he cs8900 ... */
166 get_reg_init_bus (PP_ChipID);
wdenkc6097192002-11-03 00:24:07 +0000167}
168
wdenk4fc95692003-02-28 00:49:47 +0000169int eth_init (bd_t * bd)
wdenkc6097192002-11-03 00:24:07 +0000170{
171
wdenk4fc95692003-02-28 00:49:47 +0000172 /* verify chip id */
173 if (get_reg_init_bus (PP_ChipID) != 0x630e) {
174 printf ("CS8900 Ethernet chip not found?!\n");
175 return 0;
176 }
wdenkc6097192002-11-03 00:24:07 +0000177
wdenk4fc95692003-02-28 00:49:47 +0000178 eth_reset ();
179 /* set the ethernet address */
180 put_reg (PP_IA + 0, bd->bi_enetaddr[0] | (bd->bi_enetaddr[1] << 8));
181 put_reg (PP_IA + 2, bd->bi_enetaddr[2] | (bd->bi_enetaddr[3] << 8));
182 put_reg (PP_IA + 4, bd->bi_enetaddr[4] | (bd->bi_enetaddr[5] << 8));
wdenkc6097192002-11-03 00:24:07 +0000183
wdenk4fc95692003-02-28 00:49:47 +0000184 /* receive only error free packets addressed to this card */
185 put_reg (PP_RxCTL, PP_RxCTL_IA | PP_RxCTL_Broadcast | PP_RxCTL_RxOK);
wdenkc6097192002-11-03 00:24:07 +0000186
wdenk4fc95692003-02-28 00:49:47 +0000187 /* do not generate any interrupts on receive operations */
188 put_reg (PP_RxCFG, 0);
wdenkc6097192002-11-03 00:24:07 +0000189
wdenk4fc95692003-02-28 00:49:47 +0000190 /* do not generate any interrupts on transmit operations */
191 put_reg (PP_TxCFG, 0);
wdenkc6097192002-11-03 00:24:07 +0000192
wdenk4fc95692003-02-28 00:49:47 +0000193 /* do not generate any interrupts on buffer operations */
194 put_reg (PP_BufCFG, 0);
wdenkc6097192002-11-03 00:24:07 +0000195
wdenk4fc95692003-02-28 00:49:47 +0000196 /* enable transmitter/receiver mode */
197 put_reg (PP_LineCTL, PP_LineCTL_Rx | PP_LineCTL_Tx);
wdenkc6097192002-11-03 00:24:07 +0000198
wdenk4fc95692003-02-28 00:49:47 +0000199 return 0;
wdenkc6097192002-11-03 00:24:07 +0000200}
201
202/* Get a data block via Ethernet */
wdenk4fc95692003-02-28 00:49:47 +0000203extern int eth_rx (void)
wdenkc6097192002-11-03 00:24:07 +0000204{
wdenk4fc95692003-02-28 00:49:47 +0000205 int i;
206 unsigned short rxlen;
207 unsigned short *addr;
208 unsigned short status;
wdenkc6097192002-11-03 00:24:07 +0000209
wdenk4fc95692003-02-28 00:49:47 +0000210 status = get_reg (PP_RER);
wdenkc6097192002-11-03 00:24:07 +0000211
wdenk4fc95692003-02-28 00:49:47 +0000212 if ((status & PP_RER_RxOK) == 0)
213 return 0;
wdenkc6097192002-11-03 00:24:07 +0000214
wdenk4fc95692003-02-28 00:49:47 +0000215 status = CS8900_RTDATA; /* stat */
216 rxlen = CS8900_RTDATA; /* len */
wdenkc6097192002-11-03 00:24:07 +0000217
wdenk4fc95692003-02-28 00:49:47 +0000218 if (rxlen > PKTSIZE_ALIGN + PKTALIGN)
219 printf ("packet too big!\n");
wdenkc6097192002-11-03 00:24:07 +0000220
wdenk4fc95692003-02-28 00:49:47 +0000221 for (addr = (unsigned short *) NetRxPackets[0], i = rxlen >> 1; i > 0;
222 i--)
223 *addr++ = CS8900_RTDATA;
224 if (rxlen & 1)
225 *addr++ = CS8900_RTDATA;
wdenkc6097192002-11-03 00:24:07 +0000226
wdenk4fc95692003-02-28 00:49:47 +0000227 /* Pass the packet up to the protocol layers. */
228 NetReceive (NetRxPackets[0], rxlen);
wdenkc6097192002-11-03 00:24:07 +0000229
wdenk4fc95692003-02-28 00:49:47 +0000230 return rxlen;
wdenkc6097192002-11-03 00:24:07 +0000231}
232
233/* Send a data block via Ethernet. */
wdenk4fc95692003-02-28 00:49:47 +0000234extern int eth_send (volatile void *packet, int length)
wdenkc6097192002-11-03 00:24:07 +0000235{
wdenk4fc95692003-02-28 00:49:47 +0000236 volatile unsigned short *addr;
237 int tmo;
238 unsigned short s;
wdenkc6097192002-11-03 00:24:07 +0000239
240retry:
wdenk4fc95692003-02-28 00:49:47 +0000241 /* initiate a transmit sequence */
242 CS8900_TxCMD = PP_TxCmd_TxStart_Full;
243 CS8900_TxLEN = length;
wdenkc6097192002-11-03 00:24:07 +0000244
wdenk4fc95692003-02-28 00:49:47 +0000245 /* Test to see if the chip has allocated memory for the packet */
246 if ((get_reg (PP_BusSTAT) & PP_BusSTAT_TxRDY) == 0) {
247 /* Oops... this should not happen! */
248 printf ("cs: unable to send packet; retrying...\n");
249 for (tmo = get_timer (0) + 5 * CFG_HZ; get_timer (0) < tmo;)
250 /*NOP*/;
251 eth_reset ();
252 goto retry;
253 }
wdenkc6097192002-11-03 00:24:07 +0000254
wdenk4fc95692003-02-28 00:49:47 +0000255 /* Write the contents of the packet */
256 /* assume even number of bytes */
257 for (addr = packet; length > 0; length -= 2)
258 CS8900_RTDATA = *addr++;
wdenkc6097192002-11-03 00:24:07 +0000259
wdenk4fc95692003-02-28 00:49:47 +0000260 /* wait for transfer to succeed */
261 tmo = get_timer (0) + 5 * CFG_HZ;
262 while ((s = get_reg (PP_TER) & ~0x1F) == 0) {
263 if (get_timer (0) >= tmo)
264 break;
265 }
wdenkc6097192002-11-03 00:24:07 +0000266
wdenk4fc95692003-02-28 00:49:47 +0000267 /* nothing */ ;
268 if ((s & (PP_TER_CRS | PP_TER_TxOK)) != PP_TER_TxOK) {
269 printf ("\ntransmission error %#x\n", s);
270 }
wdenkc6097192002-11-03 00:24:07 +0000271
wdenk4fc95692003-02-28 00:49:47 +0000272 return 0;
wdenkc6097192002-11-03 00:24:07 +0000273}
274
wdenk1fe2c702003-03-06 21:55:29 +0000275static void cs8900_e2prom_ready(void)
276{
277 while(get_reg(PP_SelfST) & SI_BUSY);
278}
279
280/***********************************************************/
281/* read a 16-bit word out of the EEPROM */
282/***********************************************************/
283
284int cs8900_e2prom_read(unsigned char addr, unsigned short *value)
285{
286 cs8900_e2prom_ready();
287 put_reg(PP_EECMD, EEPROM_READ_CMD | addr);
288 cs8900_e2prom_ready();
289 *value = get_reg(PP_EEData);
290
291 return 0;
292}
293
294
295/***********************************************************/
296/* write a 16-bit word into the EEPROM */
297/***********************************************************/
298
299void cs8900_e2prom_write(unsigned char addr, unsigned short value)
300{
301 cs8900_e2prom_ready();
302 put_reg(PP_EECMD, EEPROM_WRITE_EN);
303 cs8900_e2prom_ready();
304 put_reg(PP_EEData, value);
305 put_reg(PP_EECMD, EEPROM_WRITE_CMD | addr);
306 cs8900_e2prom_ready();
307 put_reg(PP_EECMD, EEPROM_WRITE_DIS);
308 cs8900_e2prom_ready();
309
310 return 0;
311}
312
wdenk4fc95692003-02-28 00:49:47 +0000313#endif /* COMMANDS & CFG_NET */
wdenkc6097192002-11-03 00:24:07 +0000314
wdenk4fc95692003-02-28 00:49:47 +0000315#endif /* CONFIG_DRIVER_CS8900 */