Tom Rini | 8b0c8a1 | 2018-05-06 18:27:01 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ |
Patrick Delaunay | 8eb3b1e | 2018-03-12 10:46:18 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2018, STMicroelectronics - All Rights Reserved |
| 4 | * |
| 5 | * Configuration settings for the STM32MP15x CPU |
Patrick Delaunay | 8eb3b1e | 2018-03-12 10:46:18 +0100 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __CONFIG_H |
| 9 | #define __CONFIG_H |
| 10 | #include <linux/sizes.h> |
| 11 | #include <asm/arch/stm32.h> |
| 12 | |
Patrick Delaunay | 8eb3b1e | 2018-03-12 10:46:18 +0100 | [diff] [blame] | 13 | /* |
| 14 | * Number of clock ticks in 1 sec |
| 15 | */ |
| 16 | #define CONFIG_SYS_HZ 1000 |
Patrick Delaunay | 8eb3b1e | 2018-03-12 10:46:18 +0100 | [diff] [blame] | 17 | |
Patrick Delaunay | 5d06141 | 2019-02-12 11:44:39 +0100 | [diff] [blame] | 18 | #ifndef CONFIG_STM32MP1_TRUSTED |
Patrick Delaunay | e020737 | 2018-04-16 10:13:24 +0200 | [diff] [blame] | 19 | /* PSCI support */ |
| 20 | #define CONFIG_ARMV7_PSCI_1_0 |
| 21 | #define CONFIG_ARMV7_SECURE_BASE STM32_SYSRAM_BASE |
| 22 | #define CONFIG_ARMV7_SECURE_MAX_SIZE STM32_SYSRAM_SIZE |
Patrick Delaunay | 5d06141 | 2019-02-12 11:44:39 +0100 | [diff] [blame] | 23 | #endif |
Patrick Delaunay | e020737 | 2018-04-16 10:13:24 +0200 | [diff] [blame] | 24 | |
Patrick Delaunay | 8eb3b1e | 2018-03-12 10:46:18 +0100 | [diff] [blame] | 25 | /* |
Patrick Delaunay | 8eb3b1e | 2018-03-12 10:46:18 +0100 | [diff] [blame] | 26 | * Configuration of the external SRAM memory used by U-Boot |
| 27 | */ |
| 28 | #define CONFIG_SYS_SDRAM_BASE STM32_DDR_BASE |
| 29 | #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE |
| 30 | |
Patrick Delaunay | 8eb3b1e | 2018-03-12 10:46:18 +0100 | [diff] [blame] | 31 | /* |
| 32 | * Console I/O buffer size |
| 33 | */ |
| 34 | #define CONFIG_SYS_CBSIZE SZ_1K |
| 35 | |
| 36 | /* |
| 37 | * Needed by "loadb" |
| 38 | */ |
| 39 | #define CONFIG_SYS_LOAD_ADDR STM32_DDR_BASE |
| 40 | |
Patrice Chotard | de326e4 | 2019-05-07 18:39:22 +0200 | [diff] [blame] | 41 | #if defined(CONFIG_ENV_IS_IN_UBI) |
| 42 | #define CONFIG_ENV_UBI_VOLUME_REDUND "uboot_config_r" |
| 43 | #endif |
| 44 | |
Patrice Chotard | 0980d9c | 2019-01-24 11:33:29 +0100 | [diff] [blame] | 45 | #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) |
| 46 | #define CONFIG_ENV_SECT_SIZE SZ_256K |
| 47 | #define CONFIG_ENV_OFFSET 0x00280000 |
| 48 | #endif |
| 49 | |
Patrick Delaunay | 8eb3b1e | 2018-03-12 10:46:18 +0100 | [diff] [blame] | 50 | /* ATAGs */ |
| 51 | #define CONFIG_CMDLINE_TAG |
| 52 | #define CONFIG_SETUP_MEMORY_TAGS |
| 53 | #define CONFIG_INITRD_TAG |
| 54 | |
Patrick Delaunay | 80e17eb | 2019-02-27 17:01:21 +0100 | [diff] [blame] | 55 | /* Extend size of kernel image for uncompression */ |
| 56 | #define CONFIG_SYS_BOOTM_LEN SZ_32M |
| 57 | |
Patrick Delaunay | 8eb3b1e | 2018-03-12 10:46:18 +0100 | [diff] [blame] | 58 | /* SPL support */ |
| 59 | #ifdef CONFIG_SPL |
| 60 | /* BOOTROM load address */ |
Patrick Delaunay | 8eb3b1e | 2018-03-12 10:46:18 +0100 | [diff] [blame] | 61 | /* SPL use DDR */ |
| 62 | #define CONFIG_SPL_BSS_START_ADDR 0xC0200000 |
| 63 | #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 |
| 64 | #define CONFIG_SYS_SPL_MALLOC_START 0xC0300000 |
| 65 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 |
| 66 | |
| 67 | /* limit SYSRAM usage to first 128 KB */ |
| 68 | #define CONFIG_SPL_MAX_SIZE 0x00020000 |
| 69 | #define CONFIG_SPL_STACK (STM32_SYSRAM_BASE + \ |
| 70 | STM32_SYSRAM_SIZE) |
| 71 | #endif /* #ifdef CONFIG_SPL */ |
| 72 | |
Patrick Delaunay | a9a3694 | 2019-02-27 17:01:22 +0100 | [diff] [blame] | 73 | #define CONFIG_SYS_MEMTEST_START STM32_DDR_BASE |
| 74 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_64M) |
| 75 | #define CONFIG_SYS_MEMTEST_SCRATCH (CONFIG_SYS_MEMTEST_END + 4) |
| 76 | |
Patrick Delaunay | 8eb3b1e | 2018-03-12 10:46:18 +0100 | [diff] [blame] | 77 | /*MMC SD*/ |
| 78 | #define CONFIG_SYS_MMC_MAX_DEVICE 3 |
Patrick Delaunay | 8eb3b1e | 2018-03-12 10:46:18 +0100 | [diff] [blame] | 79 | |
Patrick Delaunay | f2a7b87 | 2019-02-27 17:01:18 +0100 | [diff] [blame] | 80 | /*****************************************************************************/ |
| 81 | #ifdef CONFIG_DISTRO_DEFAULTS |
| 82 | /*****************************************************************************/ |
| 83 | |
| 84 | #if !defined(CONFIG_SPL_BUILD) |
Patrick Delaunay | 8eb3b1e | 2018-03-12 10:46:18 +0100 | [diff] [blame] | 85 | |
Patrick Delaunay | e0188ac | 2019-04-08 15:30:52 +0200 | [diff] [blame] | 86 | /* NAND support */ |
| 87 | #define CONFIG_SYS_NAND_ONFI_DETECTION |
| 88 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
Patrick Delaunay | 8eb3b1e | 2018-03-12 10:46:18 +0100 | [diff] [blame] | 89 | #define BOOT_TARGET_DEVICES(func) \ |
| 90 | func(MMC, mmc, 1) \ |
| 91 | func(MMC, mmc, 0) \ |
| 92 | func(MMC, mmc, 2) |
Patrick Delaunay | f2a7b87 | 2019-02-27 17:01:18 +0100 | [diff] [blame] | 93 | /* |
| 94 | * bootcmd for stm32mp1: |
| 95 | * for serial/usb: execute the stm32prog command |
| 96 | * for mmc boot (eMMC, SD card), boot only on the same device |
| 97 | * for nand boot, boot with on ubifs partition on nand |
| 98 | * for nor boot, use the default order |
| 99 | */ |
Patrick Delaunay | f2a7b87 | 2019-02-27 17:01:18 +0100 | [diff] [blame] | 100 | #define STM32MP_BOOTCMD "bootcmd_stm32mp=" \ |
| 101 | "echo \"Boot over ${boot_device}${boot_instance}!\";" \ |
| 102 | "if test ${boot_device} = serial || test ${boot_device} = usb;" \ |
| 103 | "then stm32prog ${boot_device} ${boot_instance}; " \ |
| 104 | "else " \ |
| 105 | "if test ${boot_device} = mmc;" \ |
| 106 | "then env set boot_targets \"mmc${boot_instance}\"; fi;" \ |
| 107 | "if test ${boot_device} = nand;" \ |
| 108 | "then env set boot_targets ubifs0; fi;" \ |
| 109 | "run distro_bootcmd;" \ |
| 110 | "fi;\0" |
Patrick Delaunay | 8eb3b1e | 2018-03-12 10:46:18 +0100 | [diff] [blame] | 111 | |
Patrick Delaunay | f2a7b87 | 2019-02-27 17:01:18 +0100 | [diff] [blame] | 112 | #include <config_distro_bootcmd.h> |
Patrick Delaunay | fc69c68 | 2018-03-20 10:54:54 +0100 | [diff] [blame] | 113 | |
Patrice Chotard | 41443cf | 2019-05-02 18:07:14 +0200 | [diff] [blame] | 114 | #if defined(CONFIG_STM32_QSPI) || defined(CONFIG_NAND_STM32_FMC) |
| 115 | #define CONFIG_SYS_MTDPARTS_RUNTIME |
| 116 | #endif |
| 117 | |
| 118 | #define STM32MP_MTDPARTS \ |
Patrice Chotard | 0980d9c | 2019-01-24 11:33:29 +0100 | [diff] [blame] | 119 | "mtdparts_nor0=256k(fsbl1),256k(fsbl2),2m(ssbl),256k(u-boot-env),-(nor_user)\0" \ |
Patrice Chotard | 41443cf | 2019-05-02 18:07:14 +0200 | [diff] [blame] | 120 | "mtdparts_nand0=2m(fsbl),2m(ssbl1),2m(ssbl2),-(UBI)\0" |
| 121 | |
Patrick Delaunay | 80e17eb | 2019-02-27 17:01:21 +0100 | [diff] [blame] | 122 | /* |
| 123 | * memory layout for 32M uncompressed/compressed kernel, |
| 124 | * 1M fdt, 1M script, 1M pxe and 1M for splashimage |
| 125 | * and the ramdisk at the end. |
| 126 | */ |
Patrick Delaunay | 8eb3b1e | 2018-03-12 10:46:18 +0100 | [diff] [blame] | 127 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Patrick Delaunay | 80e17eb | 2019-02-27 17:01:21 +0100 | [diff] [blame] | 128 | "kernel_addr_r=0xc2000000\0" \ |
| 129 | "fdt_addr_r=0xc4000000\0" \ |
| 130 | "scriptaddr=0xc4100000\0" \ |
| 131 | "pxefile_addr_r=0xc4200000\0" \ |
| 132 | "splashimage=0xc4300000\0" \ |
| 133 | "ramdisk_addr_r=0xc4400000\0" \ |
Patrick Delaunay | 8eb3b1e | 2018-03-12 10:46:18 +0100 | [diff] [blame] | 134 | "fdt_high=0xffffffff\0" \ |
| 135 | "initrd_high=0xffffffff\0" \ |
Patrick Delaunay | f2a7b87 | 2019-02-27 17:01:18 +0100 | [diff] [blame] | 136 | STM32MP_BOOTCMD \ |
Patrice Chotard | 41443cf | 2019-05-02 18:07:14 +0200 | [diff] [blame] | 137 | STM32MP_MTDPARTS \ |
Patrick Delaunay | 8eb3b1e | 2018-03-12 10:46:18 +0100 | [diff] [blame] | 138 | BOOTENV |
| 139 | |
| 140 | #endif /* ifndef CONFIG_SPL_BUILD */ |
Patrick Delaunay | f2a7b87 | 2019-02-27 17:01:18 +0100 | [diff] [blame] | 141 | #endif /* ifdef CONFIG_DISTRO_DEFAULTS*/ |
Patrick Delaunay | 8eb3b1e | 2018-03-12 10:46:18 +0100 | [diff] [blame] | 142 | |
| 143 | #endif /* __CONFIG_H */ |