blob: ef029722b455d7c12012de2d6178d7a58e146dd6 [file] [log] [blame]
Jason Liudec11122011-11-25 00:18:02 +00001/*
2 * (C) Copyright 2007
3 * Sascha Hauer, Pengutronix
4 *
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Jason Liudec11122011-11-25 00:18:02 +00008 */
9
10#include <common.h>
Fabio Estevam13409292014-01-29 17:39:49 -020011#include <asm/armv7.h>
Jeroen Hofstee1abf3a12014-10-08 22:57:52 +020012#include <asm/bootm.h>
Fabio Estevam13409292014-01-29 17:39:49 -020013#include <asm/pl310.h>
Jason Liudec11122011-11-25 00:18:02 +000014#include <asm/errno.h>
15#include <asm/io.h>
16#include <asm/arch/imx-regs.h>
17#include <asm/arch/clock.h>
18#include <asm/arch/sys_proto.h>
Troy Kisky0ca618c2012-08-15 10:31:20 +000019#include <asm/imx-common/boot_mode.h>
Stefan Roese8338d1d2013-04-15 21:14:12 +000020#include <asm/imx-common/dma.h>
Fabio Estevam48e65b02013-02-07 06:45:23 +000021#include <stdbool.h>
Pardeep Kumar Singlac1fa1302013-07-25 12:12:13 -050022#include <asm/arch/mxc_hdmi.h>
23#include <asm/arch/crm_regs.h>
Eric Nelson357a4e42014-09-30 15:40:02 -070024#include <asm/bootm.h>
Ye.Lif19692c2014-11-20 21:14:14 +080025#include <dm.h>
26#include <imx_thermal.h>
Jason Liudec11122011-11-25 00:18:02 +000027
Fabio Estevama47ec522013-12-26 14:51:33 -020028enum ldo_reg {
29 LDO_ARM,
30 LDO_SOC,
31 LDO_PU,
32};
33
Troy Kisky58394932012-10-23 10:57:46 +000034struct scu_regs {
35 u32 ctrl;
36 u32 config;
37 u32 status;
38 u32 invalidate;
39 u32 fpga_rev;
40};
41
Ye.Lif19692c2014-11-20 21:14:14 +080042#if defined(CONFIG_IMX6_THERMAL)
43static const struct imx_thermal_plat imx6_thermal_plat = {
44 .regs = (void *)ANATOP_BASE_ADDR,
45 .fuse_bank = 1,
46 .fuse_word = 6,
47};
48
49U_BOOT_DEVICE(imx6_thermal) = {
50 .name = "imx_thermal",
51 .platdata = &imx6_thermal_plat,
52};
53#endif
54
Gabriel Huau170ceaf2014-07-26 11:35:43 -070055u32 get_nr_cpus(void)
56{
57 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
58 return readl(&scu->config) & 3;
59}
60
Jason Liudec11122011-11-25 00:18:02 +000061u32 get_cpu_rev(void)
62{
Fabio Estevam46e97332012-03-20 04:21:45 +000063 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
Troy Kisky58394932012-10-23 10:57:46 +000064 u32 reg = readl(&anatop->digprog_sololite);
65 u32 type = ((reg >> 16) & 0xff);
Fabio Estevam46e97332012-03-20 04:21:45 +000066
Troy Kisky58394932012-10-23 10:57:46 +000067 if (type != MXC_CPU_MX6SL) {
68 reg = readl(&anatop->digprog);
Fabio Estevamf3d5a2c2014-01-26 15:06:41 -020069 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
70 u32 cfg = readl(&scu->config) & 3;
Troy Kisky58394932012-10-23 10:57:46 +000071 type = ((reg >> 16) & 0xff);
72 if (type == MXC_CPU_MX6DL) {
Troy Kisky58394932012-10-23 10:57:46 +000073 if (!cfg)
74 type = MXC_CPU_MX6SOLO;
75 }
Fabio Estevamf3d5a2c2014-01-26 15:06:41 -020076
77 if (type == MXC_CPU_MX6Q) {
78 if (cfg == 1)
79 type = MXC_CPU_MX6D;
80 }
81
Troy Kisky58394932012-10-23 10:57:46 +000082 }
83 reg &= 0xff; /* mx6 silicon revision */
84 return (type << 12) | (reg + 0x10);
Jason Liudec11122011-11-25 00:18:02 +000085}
86
Fabio Estevam435998b2013-03-27 07:36:55 +000087#ifdef CONFIG_REVISION_TAG
88u32 __weak get_board_rev(void)
89{
90 u32 cpurev = get_cpu_rev();
91 u32 type = ((cpurev >> 12) & 0xff);
92 if (type == MXC_CPU_MX6SOLO)
93 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
94
Fabio Estevamf3d5a2c2014-01-26 15:06:41 -020095 if (type == MXC_CPU_MX6D)
96 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
97
Fabio Estevam435998b2013-03-27 07:36:55 +000098 return cpurev;
99}
100#endif
101
Jason Liudec11122011-11-25 00:18:02 +0000102void init_aips(void)
103{
Jason Liubb25e072012-01-10 00:52:59 +0000104 struct aipstz_regs *aips1, *aips2;
Fabio Estevam712ab882014-06-24 17:40:58 -0300105#ifdef CONFIG_MX6SX
106 struct aipstz_regs *aips3;
107#endif
Jason Liubb25e072012-01-10 00:52:59 +0000108
109 aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
110 aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
Fabio Estevam712ab882014-06-24 17:40:58 -0300111#ifdef CONFIG_MX6SX
Ye.Li00cce362015-01-14 17:18:12 +0800112 aips3 = (struct aipstz_regs *)AIPS3_CONFIG_BASE_ADDR;
Fabio Estevam712ab882014-06-24 17:40:58 -0300113#endif
Jason Liudec11122011-11-25 00:18:02 +0000114
115 /*
116 * Set all MPROTx to be non-bufferable, trusted for R/W,
117 * not forced to user-mode.
118 */
Jason Liubb25e072012-01-10 00:52:59 +0000119 writel(0x77777777, &aips1->mprot0);
120 writel(0x77777777, &aips1->mprot1);
121 writel(0x77777777, &aips2->mprot0);
122 writel(0x77777777, &aips2->mprot1);
Jason Liudec11122011-11-25 00:18:02 +0000123
Jason Liubb25e072012-01-10 00:52:59 +0000124 /*
125 * Set all OPACRx to be non-bufferable, not require
126 * supervisor privilege level for access,allow for
127 * write access and untrusted master access.
128 */
129 writel(0x00000000, &aips1->opacr0);
130 writel(0x00000000, &aips1->opacr1);
131 writel(0x00000000, &aips1->opacr2);
132 writel(0x00000000, &aips1->opacr3);
133 writel(0x00000000, &aips1->opacr4);
134 writel(0x00000000, &aips2->opacr0);
135 writel(0x00000000, &aips2->opacr1);
136 writel(0x00000000, &aips2->opacr2);
137 writel(0x00000000, &aips2->opacr3);
138 writel(0x00000000, &aips2->opacr4);
Fabio Estevam712ab882014-06-24 17:40:58 -0300139
140#ifdef CONFIG_MX6SX
141 /*
142 * Set all MPROTx to be non-bufferable, trusted for R/W,
143 * not forced to user-mode.
144 */
145 writel(0x77777777, &aips3->mprot0);
146 writel(0x77777777, &aips3->mprot1);
147
148 /*
149 * Set all OPACRx to be non-bufferable, not require
150 * supervisor privilege level for access,allow for
151 * write access and untrusted master access.
152 */
153 writel(0x00000000, &aips3->opacr0);
154 writel(0x00000000, &aips3->opacr1);
155 writel(0x00000000, &aips3->opacr2);
156 writel(0x00000000, &aips3->opacr3);
157 writel(0x00000000, &aips3->opacr4);
158#endif
Jason Liudec11122011-11-25 00:18:02 +0000159}
160
Fabio Estevamcf621ff2013-12-26 14:51:31 -0200161static void clear_ldo_ramp(void)
162{
163 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
164 int reg;
165
166 /* ROM may modify LDO ramp up time according to fuse setting, so in
167 * order to be in the safe side we neeed to reset these settings to
168 * match the reset value: 0'b00
169 */
170 reg = readl(&anatop->ana_misc2);
171 reg &= ~(0x3f << 24);
172 writel(reg, &anatop->ana_misc2);
173}
174
Dirk Behme8c465942012-05-02 02:12:17 +0000175/*
Fabio Estevam2e95fe12014-06-13 01:42:37 -0300176 * Set the PMU_REG_CORE register
Dirk Behme8c465942012-05-02 02:12:17 +0000177 *
Fabio Estevam2e95fe12014-06-13 01:42:37 -0300178 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
Dirk Behme8c465942012-05-02 02:12:17 +0000179 * Possible values are from 0.725V to 1.450V in steps of
180 * 0.025V (25mV).
181 */
Fabio Estevama47ec522013-12-26 14:51:33 -0200182static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
Dirk Behme8c465942012-05-02 02:12:17 +0000183{
184 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
Fabio Estevam99b370b2013-12-26 14:51:34 -0200185 u32 val, step, old, reg = readl(&anatop->reg_core);
Fabio Estevama47ec522013-12-26 14:51:33 -0200186 u8 shift;
Dirk Behme8c465942012-05-02 02:12:17 +0000187
188 if (mv < 725)
189 val = 0x00; /* Power gated off */
190 else if (mv > 1450)
191 val = 0x1F; /* Power FET switched full on. No regulation */
192 else
193 val = (mv - 700) / 25;
194
Fabio Estevamcf621ff2013-12-26 14:51:31 -0200195 clear_ldo_ramp();
196
Fabio Estevama47ec522013-12-26 14:51:33 -0200197 switch (ldo) {
198 case LDO_SOC:
199 shift = 18;
200 break;
201 case LDO_PU:
202 shift = 9;
203 break;
204 case LDO_ARM:
205 shift = 0;
206 break;
207 default:
208 return -EINVAL;
209 }
210
Fabio Estevam99b370b2013-12-26 14:51:34 -0200211 old = (reg & (0x1F << shift)) >> shift;
212 step = abs(val - old);
213 if (step == 0)
214 return 0;
215
Fabio Estevama47ec522013-12-26 14:51:33 -0200216 reg = (reg & ~(0x1F << shift)) | (val << shift);
Dirk Behme8c465942012-05-02 02:12:17 +0000217 writel(reg, &anatop->reg_core);
Fabio Estevama47ec522013-12-26 14:51:33 -0200218
Fabio Estevam99b370b2013-12-26 14:51:34 -0200219 /*
220 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
221 * step
222 */
223 udelay(3 * step);
224
Fabio Estevama47ec522013-12-26 14:51:33 -0200225 return 0;
Dirk Behme8c465942012-05-02 02:12:17 +0000226}
227
Fabio Estevam48e65b02013-02-07 06:45:23 +0000228static void imx_set_wdog_powerdown(bool enable)
229{
230 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
231 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
232
Peng Fancc844dc2015-01-15 14:22:33 +0800233#ifdef CONFIG_MX6SX
234 struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
235 writew(enable, &wdog3->wmcr);
236#endif
237
Fabio Estevam48e65b02013-02-07 06:45:23 +0000238 /* Write to the PDE (Power Down Enable) bit */
239 writew(enable, &wdog1->wmcr);
240 writew(enable, &wdog2->wmcr);
241}
242
Anson Huang05a464f2014-01-23 14:00:18 +0800243static void set_ahb_rate(u32 val)
244{
245 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
246 u32 reg, div;
247
248 div = get_periph_clk() / val - 1;
249 reg = readl(&mxc_ccm->cbcdr);
250
251 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
252 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
253}
254
Anson Huang9a149bc2014-01-23 14:00:19 +0800255static void clear_mmdc_ch_mask(void)
256{
257 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
258
259 /* Clear MMDC channel mask */
260 writel(0, &mxc_ccm->ccdr);
261}
262
Peng Fanc0e0ebf2015-01-15 14:22:32 +0800263static void init_bandgap(void)
264{
265 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
266 /*
267 * Ensure the bandgap has stabilized.
268 */
269 while (!(readl(&anatop->ana_misc0) & 0x80))
270 ;
271 /*
272 * For best noise performance of the analog blocks using the
273 * outputs of the bandgap, the reftop_selfbiasoff bit should
274 * be set.
275 */
276 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
277}
278
279
Ye.Li622dfbd2014-10-30 18:20:58 +0800280#ifdef CONFIG_MX6SL
281static void set_preclk_from_osc(void)
282{
283 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
284 u32 reg;
285
286 reg = readl(&mxc_ccm->cscmr1);
287 reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
288 writel(reg, &mxc_ccm->cscmr1);
289}
290#endif
291
Jason Liudec11122011-11-25 00:18:02 +0000292int arch_cpu_init(void)
293{
294 init_aips();
295
Anson Huang9a149bc2014-01-23 14:00:19 +0800296 /* Need to clear MMDC_CHx_MASK to make warm reset work. */
297 clear_mmdc_ch_mask();
298
Anson Huang05a464f2014-01-23 14:00:18 +0800299 /*
Peng Fanc0e0ebf2015-01-15 14:22:32 +0800300 * Disable self-bias circuit in the analog bandap.
301 * The self-bias circuit is used by the bandgap during startup.
302 * This bit should be set after the bandgap has initialized.
303 */
304 init_bandgap();
305
306 /*
Anson Huang05a464f2014-01-23 14:00:18 +0800307 * When low freq boot is enabled, ROM will not set AHB
308 * freq, so we need to ensure AHB freq is 132MHz in such
309 * scenario.
310 */
311 if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
312 set_ahb_rate(132000000);
313
Ye.Li622dfbd2014-10-30 18:20:58 +0800314 /* Set perclk to source from OSC 24MHz */
315#if defined(CONFIG_MX6SL)
316 set_preclk_from_osc();
317#endif
318
Fabio Estevam48e65b02013-02-07 06:45:23 +0000319 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
Stefan Roese8338d1d2013-04-15 21:14:12 +0000320
321#ifdef CONFIG_APBH_DMA
322 /* Start APBH DMA */
323 mxs_dma_init();
324#endif
325
Jason Liudec11122011-11-25 00:18:02 +0000326 return 0;
327}
Jason Liudec11122011-11-25 00:18:02 +0000328
Fabio Estevam99b370b2013-12-26 14:51:34 -0200329int board_postclk_init(void)
330{
331 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
332
333 return 0;
334}
335
Eric Nelsonc94ce4a2012-03-04 11:47:38 +0000336#ifndef CONFIG_SYS_DCACHE_OFF
337void enable_caches(void)
338{
Nitin Gargb1ce7012014-09-16 13:33:25 -0500339#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
340 enum dcache_option option = DCACHE_WRITETHROUGH;
341#else
342 enum dcache_option option = DCACHE_WRITEBACK;
343#endif
344
Frank Li40c41002013-11-14 00:58:46 +0800345 /* Avoid random hang when download by usb */
346 invalidate_dcache_all();
Nitin Gargb1ce7012014-09-16 13:33:25 -0500347
Eric Nelsonc94ce4a2012-03-04 11:47:38 +0000348 /* Enable D-cache. I-cache is already enabled in start.S */
349 dcache_enable();
Nitin Gargb1ce7012014-09-16 13:33:25 -0500350
351 /* Enable caching on OCRAM and ROM */
352 mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
353 ROMCP_ARB_END_ADDR,
354 option);
355 mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
356 IRAM_SIZE,
357 option);
Eric Nelsonc94ce4a2012-03-04 11:47:38 +0000358}
359#endif
360
Jason Liudec11122011-11-25 00:18:02 +0000361#if defined(CONFIG_FEC_MXC)
Fabio Estevam04fc1282011-12-20 05:46:31 +0000362void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
Jason Liudec11122011-11-25 00:18:02 +0000363{
Benoît Thébaudeaufa7e3952013-04-23 10:17:38 +0000364 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
365 struct fuse_bank *bank = &ocotp->bank[4];
Jason Liudec11122011-11-25 00:18:02 +0000366 struct fuse_bank4_regs *fuse =
367 (struct fuse_bank4_regs *)bank->fuse_regs;
368
Jason Liubf651aa2011-12-19 02:38:13 +0000369 u32 value = readl(&fuse->mac_addr_high);
370 mac[0] = (value >> 8);
371 mac[1] = value ;
Jason Liudec11122011-11-25 00:18:02 +0000372
Jason Liubf651aa2011-12-19 02:38:13 +0000373 value = readl(&fuse->mac_addr_low);
374 mac[2] = value >> 24 ;
375 mac[3] = value >> 16 ;
376 mac[4] = value >> 8 ;
377 mac[5] = value ;
Jason Liudec11122011-11-25 00:18:02 +0000378
379}
380#endif
Troy Kisky0ca618c2012-08-15 10:31:20 +0000381
382void boot_mode_apply(unsigned cfg_val)
383{
384 unsigned reg;
Eric Nelson7b8731a2012-09-18 15:26:32 +0000385 struct src *psrc = (struct src *)SRC_BASE_ADDR;
Troy Kisky0ca618c2012-08-15 10:31:20 +0000386 writel(cfg_val, &psrc->gpr9);
387 reg = readl(&psrc->gpr10);
388 if (cfg_val)
389 reg |= 1 << 28;
390 else
391 reg &= ~(1 << 28);
392 writel(reg, &psrc->gpr10);
393}
394/*
395 * cfg_val will be used for
396 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
Nikita Kiryanov9fba8422014-10-29 19:28:33 +0200397 * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
398 * instead of SBMR1 to determine the boot device.
Troy Kisky0ca618c2012-08-15 10:31:20 +0000399 */
400const struct boot_mode soc_boot_modes[] = {
401 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
402 /* reserved value should start rom usb */
403 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
404 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
Nikolay Dimitrov284d9012014-08-10 20:03:07 +0300405 {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
406 {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
407 {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
408 {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
Troy Kisky0ca618c2012-08-15 10:31:20 +0000409 /* 4 bit bus width */
410 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
411 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
412 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
413 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
414 {NULL, 0},
415};
Stephen Warren57ab23f2013-02-26 12:28:29 +0000416
417void s_init(void)
418{
Eric Nelson2c37d3b2013-08-29 12:41:46 -0700419 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
Ye.Li29876872014-09-09 10:17:00 +0800420 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
Eric Nelson2c37d3b2013-08-29 12:41:46 -0700421 u32 mask480;
422 u32 mask528;
Ye.Li29876872014-09-09 10:17:00 +0800423 u32 reg, periph1, periph2;
Fabio Estevam6633e3f2014-07-09 16:13:29 -0300424
425 if (is_cpu_type(MXC_CPU_MX6SX))
426 return;
427
Eric Nelson2c37d3b2013-08-29 12:41:46 -0700428 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
429 * to make sure PFD is working right, otherwise, PFDs may
430 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
431 * workaround in ROM code, as bus clock need it
432 */
433
434 mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
435 ANATOP_PFD_CLKGATE_MASK(1) |
436 ANATOP_PFD_CLKGATE_MASK(2) |
437 ANATOP_PFD_CLKGATE_MASK(3);
Ye.Li29876872014-09-09 10:17:00 +0800438 mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
Eric Nelson2c37d3b2013-08-29 12:41:46 -0700439 ANATOP_PFD_CLKGATE_MASK(3);
440
Ye.Li29876872014-09-09 10:17:00 +0800441 reg = readl(&ccm->cbcmr);
442 periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
443 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
444 periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
445 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
446
447 /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
448 if ((periph2 != 0x2) && (periph1 != 0x2))
449 mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
450
451 if ((periph2 != 0x1) && (periph1 != 0x1) &&
452 (periph2 != 0x3) && (periph1 != 0x3))
Eric Nelson2c37d3b2013-08-29 12:41:46 -0700453 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
Ye.Li29876872014-09-09 10:17:00 +0800454
Eric Nelson2c37d3b2013-08-29 12:41:46 -0700455 writel(mask480, &anatop->pfd_480_set);
456 writel(mask528, &anatop->pfd_528_set);
457 writel(mask480, &anatop->pfd_480_clr);
458 writel(mask528, &anatop->pfd_528_clr);
Stephen Warren57ab23f2013-02-26 12:28:29 +0000459}
Pardeep Kumar Singlac1fa1302013-07-25 12:12:13 -0500460
461#ifdef CONFIG_IMX_HDMI
462void imx_enable_hdmi_phy(void)
463{
464 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
465 u8 reg;
466 reg = readb(&hdmi->phy_conf0);
467 reg |= HDMI_PHY_CONF0_PDZ_MASK;
468 writeb(reg, &hdmi->phy_conf0);
469 udelay(3000);
470 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
471 writeb(reg, &hdmi->phy_conf0);
472 udelay(3000);
473 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
474 writeb(reg, &hdmi->phy_conf0);
475 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
476}
477
478void imx_setup_hdmi(void)
479{
480 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
481 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
482 int reg;
483
484 /* Turn on HDMI PHY clock */
485 reg = readl(&mxc_ccm->CCGR2);
486 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
487 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
488 writel(reg, &mxc_ccm->CCGR2);
489 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
490 reg = readl(&mxc_ccm->chsccdr);
491 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
492 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
493 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
494 reg |= (CHSCCDR_PODF_DIVIDE_BY_3
495 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
496 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
497 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
498 writel(reg, &mxc_ccm->chsccdr);
499}
500#endif
Fabio Estevam13409292014-01-29 17:39:49 -0200501
502#ifndef CONFIG_SYS_L2CACHE_OFF
503#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
504void v7_outer_cache_enable(void)
505{
506 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
507 unsigned int val;
508
509#if defined CONFIG_MX6SL
510 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
511 val = readl(&iomux->gpr[11]);
512 if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
513 /* L2 cache configured as OCRAM, reset it */
514 val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
515 writel(val, &iomux->gpr[11]);
516 }
517#endif
518
Ye.Lia3e539a2014-08-20 17:18:24 +0800519 /* Must disable the L2 before changing the latency parameters */
520 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
521
Fabio Estevam13409292014-01-29 17:39:49 -0200522 writel(0x132, &pl310->pl310_tag_latency_ctrl);
523 writel(0x132, &pl310->pl310_data_latency_ctrl);
524
525 val = readl(&pl310->pl310_prefetch_ctrl);
526
527 /* Turn on the L2 I/D prefetch */
528 val |= 0x30000000;
529
530 /*
531 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
532 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
533 * But according to ARM PL310 errata: 752271
534 * ID: 752271: Double linefill feature can cause data corruption
535 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
536 * Workaround: The only workaround to this erratum is to disable the
537 * double linefill feature. This is the default behavior.
538 */
539
540#ifndef CONFIG_MX6Q
541 val |= 0x40800000;
542#endif
543 writel(val, &pl310->pl310_prefetch_ctrl);
544
545 val = readl(&pl310->pl310_power_ctrl);
546 val |= L2X0_DYNAMIC_CLK_GATING_EN;
547 val |= L2X0_STNDBY_MODE_EN;
548 writel(val, &pl310->pl310_power_ctrl);
549
550 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
551}
552
553void v7_outer_cache_disable(void)
554{
555 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
556
557 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
558}
559#endif /* !CONFIG_SYS_L2CACHE_OFF */