Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 484df491fe884ed0a39e46adedc27052dbfc02e8 / . / drivers / usb / host / Kconfig
blob: 1a883babf4c24f04a5451e20fb50d366de95163e [file] [log] [blame]
Masahiro Yamada1b0a06b2014-11-07 18:48:31 +0900[diff] [blame]1#
2# USB Host Controller Drivers
3#
4comment "USB Host Controller Drivers"
5
Masahiro Yamada59cfdc02016-08-01 00:16:34 +0900[diff] [blame]6config USB_HOST
7 bool
Tom Rini5b9e6162021-07-09 10:11:56 -0400[diff] [blame]8 select DM_USB
Marek Vasut1d5c59c2023-05-06 16:42:37 +0200[diff] [blame]9 help
10 Enable access to USB (Universal Serial Bus) host devices so that
11 SPL can load U-Boot from a connected USB peripheral, such as a USB
12 flash stick. While USB takes a little longer to start up than most
13 buses, it is very flexible since many different types of storage
14 device can be attached.
15
16config SPL_USB_HOST
17 bool "Support USB host drivers"
18 depends on SPL
19 help
20 For detailed help see USB_HOST Kconfig symbol. This option enables
21 the drivers in drivers/usb/host as part of an SPL build.
Masahiro Yamada59cfdc02016-08-01 00:16:34 +0900[diff] [blame]22
Masahiro Yamada1b0a06b2014-11-07 18:48:31 +0900[diff] [blame]23config USB_XHCI_HCD
24 bool "xHCI HCD (USB 3.0) support"
Tom Rini5b9e6162021-07-09 10:11:56 -0400[diff] [blame]25 depends on DM && OF_CONTROL
Masahiro Yamada59cfdc02016-08-01 00:16:34 +0900[diff] [blame]26 select USB_HOST
Masahiro Yamada1b0a06b2014-11-07 18:48:31 +0900[diff] [blame]27 ---help---
28 The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0
29 "SuperSpeed" host controller hardware.
30
Masahiro Yamada1b0a06b2014-11-07 18:48:31 +0900[diff] [blame]31if USB_XHCI_HCD
32
Masahiro Yamadad3b72ca2016-06-04 07:35:04 +0900[diff] [blame]33config USB_XHCI_DWC3
34 bool "DesignWare USB3 DRD Core Support"
35 help
36 Say Y or if your system has a Dual Role SuperSpeed
37 USB controller based on the DesignWare USB3 IP Core.
38
Neil Armstrong069421e2018-04-11 17:08:00 +0200[diff] [blame]39config USB_XHCI_DWC3_OF_SIMPLE
40 bool "DesignWare USB3 DRD Generic OF Simple Glue Layer"
Jean-Jacques Hiblot74d9a9d2018-04-12 10:41:10 +0200[diff] [blame]41 depends on DM_USB
Mark Kettenis06ec9132019-06-30 18:01:54 +0200[diff] [blame]42 default y if ARCH_ROCKCHIP
Jean-Jacques Hiblot6c705f42018-04-12 10:41:11 +0200[diff] [blame]43 default y if DRA7XX
Neil Armstrong069421e2018-04-11 17:08:00 +0200[diff] [blame]44 help
45 Support USB2/3 functionality in simple SoC integrations with
46 USB controller based on the DesignWare USB3 IP Core.
47
Tom Rini6d772e52022-06-10 23:03:00 -0400[diff] [blame]48config USB_XHCI_EXYNOS
49 bool "Support for Samsung Exynos5 family on-chip xHCI USB controller"
50 depends on ARCH_EXYNOS5
51 default y
52 help
53 Enables support for he on-chip xHCI controller on Samsung Exynos5
54 SoCs.
55
developer507fc9b2020-05-02 11:35:18 +0200[diff] [blame]56config USB_XHCI_MTK
57 bool "Support for MediaTek on-chip xHCI USB controller"
developer4adcdca2022-05-20 11:22:56 +0800[diff] [blame]58 depends on ARCH_MEDIATEK || SOC_MT7621
developer507fc9b2020-05-02 11:35:18 +0200[diff] [blame]59 help
60 Enables support for the on-chip xHCI controller on MediaTek SoCs.
61
Stefan Roese07faf112016-07-14 11:39:20 +0200[diff] [blame]62config USB_XHCI_MVEBU
63 bool "MVEBU USB 3.0 support"
64 default y
65 depends on ARCH_MVEBU
Konstantin Porotchkin1b5ed4d2017-02-12 11:10:30 +0200[diff] [blame]66 select DM_REGULATOR
Stefan Roese07faf112016-07-14 11:39:20 +0200[diff] [blame]67 help
68 Choose this option to add support for USB 3.0 driver on mvebu
69 SoCs, which includes Armada8K, Armada3700 and other Armada
70 family SoCs.
71
Stefan Roesedf33b572020-08-24 13:04:38 +0200[diff] [blame]72config USB_XHCI_OCTEON
73 bool "Support for Marvell Octeon family on-chip xHCI USB controller"
74 depends on ARCH_OCTEON
75 default y
76 help
77 Enables support for the on-chip xHCI controller on Marvell Octeon
78 family SoCs. This is a driver for the dwc3 to provide the glue logic
79 to configure the controller.
80
Tom Riniebc1c842021-09-12 20:32:22 -0400[diff] [blame]81config USB_XHCI_OMAP
82 bool "Support for TI OMAP family xHCI USB controller"
83 depends on ARCH_OMAP2PLUS
84 help
85 Enables support for the on-chip xHCI controller found on some TI SoC
86 families. Note that some families have multiple contollers while
87 others only have something such as DesignWare-based controllers.
88 Consult the SoC documentation to determine if this option applies
89 to your hardware.
90
Bin Mengd34d6fc2017-07-19 21:50:08 +0800[diff] [blame]91config USB_XHCI_PCI
92 bool "Support for PCI-based xHCI USB controller"
Bin Meng7e8644d2017-07-19 21:51:07 +0800[diff] [blame]93 depends on DM_USB
Bin Mengd34d6fc2017-07-19 21:50:08 +0800[diff] [blame]94 default y if X86
95 help
96 Enables support for the PCI-based xHCI controller.
97
Marek Vasut24257272017-10-15 15:01:29 +0200[diff] [blame]98config USB_XHCI_RCAR
99 bool "Renesas RCar USB 3.0 support"
100 default y
101 depends on ARCH_RMOBILE
102 help
103 Choose this option to add support for USB 3.0 driver on Renesas
104 RCar Gen3 SoCs.
105
Patrice Chotardf2505b12017-09-05 11:04:24 +0200[diff] [blame]106config USB_XHCI_STI
107 bool "Support for STMicroelectronics STiH407 family on-chip xHCI USB controller"
108 depends on ARCH_STI
109 default y
110 help
111 Enables support for the on-chip xHCI controller on STMicroelectronics
112 STiH407 family SoCs. This is a driver for the dwc3 to provide the glue logic
113 to configure the controller.
114
Uri Mashiachf6ff74e2017-02-23 15:39:36 +0200[diff] [blame]115config USB_XHCI_DRA7XX_INDEX
116 int "DRA7XX xHCI USB index"
117 range 0 1
118 default 0
119 depends on DRA7XX
120 help
121 Select the DRA7XX xHCI USB index.
122 Current supported values: 0, 1.
123
Ran Wanga5a97352017-10-23 10:09:22 +0800[diff] [blame]124config USB_XHCI_FSL
125 bool "Support for NXP Layerscape on-chip xHCI USB controller"
126 default y if ARCH_LS1021A || FSL_LSCH3 || FSL_LSCH2
127 depends on !SPL_NO_USB
128 help
129 Enables support for the on-chip xHCI controller on NXP Layerscape SoCs.
Rayagonda Kokatanurf59d24e2020-04-09 09:23:15 +0530[diff] [blame]130
131config USB_XHCI_BRCM
132 bool "Broadcom USB3 Host XHCI controller"
133 depends on DM_USB
134 help
135 USB controller based on the Broadcom USB3 IP Core.
136 Supports USB2/3 functionality.
137
Masahiro Yamada78a9c792016-08-01 00:16:32 +0900[diff] [blame]138endif # USB_XHCI_HCD
Alexey Brodkin83fd3122015-12-14 17:18:50 +0300[diff] [blame]139
Tom Rini21ad2802022-06-08 08:24:26 -0400[diff] [blame]140config EHCI_DESC_BIG_ENDIAN
141 bool
142
143config EHCI_MMIO_BIG_ENDIAN
144 bool
145
Masahiro Yamada1b0a06b2014-11-07 18:48:31 +0900[diff] [blame]146config USB_EHCI_HCD
147 bool "EHCI HCD (USB 2.0) support"
Tom Rini7716cd62017-05-12 22:33:28 -0400[diff] [blame]148 default y if ARCH_MX5 || ARCH_MX6
Tom Rini5b9e6162021-07-09 10:11:56 -0400[diff] [blame]149 depends on DM && OF_CONTROL
Masahiro Yamada59cfdc02016-08-01 00:16:34 +0900[diff] [blame]150 select USB_HOST
Tom Rini21ad2802022-06-08 08:24:26 -0400[diff] [blame]151 select EHCI_DESC_BIG_ENDIAN if SYS_BIG_ENDIAN
152 select EHCI_MMIO_BIG_ENDIAN if SYS_BIG_ENDIAN
Masahiro Yamada1b0a06b2014-11-07 18:48:31 +0900[diff] [blame]153 ---help---
154 The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0
155 "high speed" (480 Mbit/sec, 60 Mbyte/sec) host controller hardware.
156 If your USB host controller supports USB 2.0, you will likely want to
157 configure this Host Controller Driver.
158
159 EHCI controllers are packaged with "companion" host controllers (OHCI
160 or UHCI) to handle USB 1.1 devices connected to root hub ports. Ports
161 will connect to EHCI if the device is high speed, otherwise they
162 connect to a companion controller. If you configure EHCI, you should
163 probably configure the OHCI (for NEC and some other vendors) USB Host
164 Controller Driver or UHCI (for Via motherboards) Host Controller
165 Driver too.
166
167 You may want to read <file:Documentation/usb/ehci.txt>.
168
Masahiro Yamada1b0a06b2014-11-07 18:48:31 +0900[diff] [blame]169if USB_EHCI_HCD
170
Marek Behúne1489262021-10-09 15:27:35 +0200[diff] [blame]171config USB_EHCI_IS_TDI
172 bool
173
Wenyou Yang11e26652016-08-05 08:57:35 +0800[diff] [blame]174config USB_EHCI_ATMEL
175 bool "Support for Atmel on-chip EHCI USB controller"
176 depends on ARCH_AT91
177 default y
178 ---help---
179 Enables support for the on-chip EHCI controller on Atmel chips.
180
Tom Rini6d772e52022-06-10 23:03:00 -0400[diff] [blame]181config USB_EHCI_EXYNOS
182 bool "Support for Samsung Exynos EHCI USB controller"
183 depends on ARCH_EXYNOS
184 default y
185 ---help---
186 Enables support for the on-chip EHCI controller on Samsung Exynos
187 SoCs.
188
Stefan Roese03901022015-09-01 11:39:44 +0200[diff] [blame]189config USB_EHCI_MARVELL
Tom Rini496a4172017-05-12 22:33:29 -0400[diff] [blame]190 bool "Support for Marvell on-chip EHCI USB controller"
Trevor Woernerbb7ab072020-05-06 08:02:40 -0400[diff] [blame]191 depends on ARCH_MVEBU || ARCH_KIRKWOOD || ARCH_ORION5X
Stefan Roese03901022015-09-01 11:39:44 +0200[diff] [blame]192 default y
Marek Behúne1489262021-10-09 15:27:35 +0200[diff] [blame]193 select USB_EHCI_IS_TDI if !ARM64
Chris Packham927671e2022-11-05 17:23:57 +1300[diff] [blame]194 select USB_EHCI_IS_TDI if ALLEYCAT_5
Stefan Roese03901022015-09-01 11:39:44 +0200[diff] [blame]195 ---help---
196 Enables support for the on-chip EHCI controller on MVEBU SoCs.
197
Lukasz Majewski6fccaf22019-04-04 12:26:55 +0200[diff] [blame]198config USB_EHCI_MX5
199 bool "Support for i.MX5 on-chip EHCI USB controller"
200 depends on ARCH_MX5
Lukasz Majewski6fccaf22019-04-04 12:26:55 +0200[diff] [blame]201 help
202 Enables support for the on-chip EHCI controller on i.MX5 SoCs.
203
Nikita Kiryanov99241032015-07-23 17:19:35 +0300[diff] [blame]204config USB_EHCI_MX6
Ye Li9da57ea2019-10-24 10:29:32 -0300[diff] [blame]205 bool "Support for i.MX6/i.MX7ULP on-chip EHCI USB controller"
Giulio Benetti13ded2c2021-05-20 16:10:15 +0200[diff] [blame]206 depends on ARCH_MX6 || ARCH_MX7ULP || ARCH_IMXRT
Tom Rini21ad2802022-06-08 08:24:26 -0400[diff] [blame]207 select EHCI_HCD_INIT_AFTER_RESET
Nikita Kiryanov99241032015-07-23 17:19:35 +0300[diff] [blame]208 default y
209 ---help---
210 Enables support for the on-chip EHCI controller on i.MX6 SoCs.
211
Stefan Agner100fe072016-07-13 00:25:36 -0700[diff] [blame]212config USB_EHCI_MX7
213 bool "Support for i.MX7 on-chip EHCI USB controller"
Marek Vasute15971f2021-04-02 14:07:22 +0200[diff] [blame]214 depends on ARCH_MX7 || IMX8M
Tom Rini21ad2802022-06-08 08:24:26 -0400[diff] [blame]215 select EHCI_HCD_INIT_AFTER_RESET if ARCH_MX7
Marek Vasute15971f2021-04-02 14:07:22 +0200[diff] [blame]216 select PHY if IMX8M
217 select NOP_PHY if IMX8M
Stefan Agner100fe072016-07-13 00:25:36 -0700[diff] [blame]218 default y
219 ---help---
220 Enables support for the on-chip EHCI controller on i.MX7 SoCs.
221
Marek Behún53d53512021-10-09 15:27:33 +0200[diff] [blame]222config USB_EHCI_MXS
Lukasz Majewski7a4aba62021-12-22 10:55:06 +0100[diff] [blame]223 bool "Support for i.MX23/i.MX28 EHCI USB controller"
224 depends on ARCH_MX23 || ARCH_MX28
Marek Behún53d53512021-10-09 15:27:33 +0200[diff] [blame]225 default y
Marek Behúne1489262021-10-09 15:27:35 +0200[diff] [blame]226 select USB_EHCI_IS_TDI
Marek Behún53d53512021-10-09 15:27:33 +0200[diff] [blame]227 help
Lukasz Majewski7a4aba62021-12-22 10:55:06 +0100[diff] [blame]228 Enables support for the on-chip EHCI controller on i.MX23 and
229 i.MX28 SoCs.
Marek Behún53d53512021-10-09 15:27:33 +0200[diff] [blame]230
Jim Liu1fd3b3d2022-06-21 17:09:02 +0800[diff] [blame]231config USB_EHCI_NPCM
232 bool "Support for Nuvoton NPCM on-chip EHCI USB controller"
233 depends on ARCH_NPCM
234 default n
235 ---help---
236 Enables support for the on-chip EHCI controller on
237 Nuvoton NPCM chips.
238
Tom Rini639a8402017-05-12 22:33:30 -0400[diff] [blame]239config USB_EHCI_OMAP
240 bool "Support for OMAP3+ on-chip EHCI USB controller"
241 depends on ARCH_OMAP2PLUS
Adam Fordcb9a3562022-02-19 17:08:44 -0600[diff] [blame]242 select PHY
243 imply NOP_PHY
Tom Rini639a8402017-05-12 22:33:30 -0400[diff] [blame]244 default y
245 ---help---
246 Enables support for the on-chip EHCI controller on OMAP3 and later
247 SoCs.
248
Marcel Ziswiler31f44952019-03-25 17:24:54 +0100[diff] [blame]249config USB_EHCI_VF
250 bool "Support for Vybrid on-chip EHCI USB controller"
251 depends on ARCH_VF610
252 default y
253 help
254 Enables support for the on-chip EHCI controller on Vybrid SoCs.
255
Ye Li9da57ea2019-10-24 10:29:32 -0300[diff] [blame]256if USB_EHCI_MX6 || USB_EHCI_MX7
Stefan Agner8652ce92016-07-13 00:25:38 -0700[diff] [blame]257
258config MXC_USB_OTG_HACTIVE
259 bool "USB Power pin high active"
260 ---help---
261 Set the USB Power pin polarity to be high active (PWR_POL)
262
263endif
264
Mateusz Kulikowskidc381172016-03-31 23:12:26 +0200[diff] [blame]265config USB_EHCI_MSM
266 bool "Support for Qualcomm on-chip EHCI USB controller"
267 depends on DM_USB
268 select USB_ULPI_VIEWPORT
Ramon Fried7e365962018-09-21 13:35:50 +0300[diff] [blame]269 select MSM8916_USB_PHY
Mateusz Kulikowskidc381172016-03-31 23:12:26 +0200[diff] [blame]270 ---help---
271 Enables support for the on-chip EHCI controller on Qualcomm
272 Snapdragon SoCs.
Mateusz Kulikowskidc381172016-03-31 23:12:26 +0200[diff] [blame]273
Bin Mengec4b5732017-08-09 00:21:54 -0700[diff] [blame]274config USB_EHCI_PCI
275 bool "Support for PCI-based EHCI USB controller"
276 default y if X86
277 help
278 Enables support for the PCI-based EHCI controller.
279
Peter Robinson43ecef42019-02-20 12:17:27 +0000[diff] [blame]280config USB_EHCI_TEGRA
281 bool "Support for NVIDIA Tegra on-chip EHCI USB controller"
Trevor Woerner513f6402020-05-06 08:02:41 -0400[diff] [blame]282 depends on ARCH_TEGRA
Marek Behúne1489262021-10-09 15:27:35 +0200[diff] [blame]283 select USB_EHCI_IS_TDI
Peter Robinson43ecef42019-02-20 12:17:27 +0000[diff] [blame]284 ---help---
285 Enable support for Tegra on-chip EHCI USB controller
286
Siva Durga Prasad Paladugu42fcc182016-07-22 14:51:51 +0530[diff] [blame]287config USB_EHCI_ZYNQ
288 bool "Support for Xilinx Zynq on-chip EHCI USB controller"
Michal Simek3239d712020-08-24 14:41:51 +0200[diff] [blame]289 default y if ARCH_ZYNQ
Marek Behúne1489262021-10-09 15:27:35 +0200[diff] [blame]290 select USB_EHCI_IS_TDI
Siva Durga Prasad Paladugu42fcc182016-07-22 14:51:51 +0530[diff] [blame]291 ---help---
292 Enable support for Zynq on-chip EHCI USB controller
293
Alexey Brodkina6aff432015-12-02 12:32:02 +0300[diff] [blame]294config USB_EHCI_GENERIC
295 bool "Support for generic EHCI USB controller"
Alexey Brodkina6aff432015-12-02 12:32:02 +0300[diff] [blame]296 depends on DM_USB
Jagan Teki1ba41e12018-12-22 18:18:10 +0530[diff] [blame]297 default ARCH_SUNXI
Alexey Brodkina6aff432015-12-02 12:32:02 +0300[diff] [blame]298 ---help---
299 Enables support for generic EHCI controller.
300
Tom Rini30fd3d92022-06-08 08:24:27 -0400[diff] [blame]301config EHCI_HCD_INIT_AFTER_RESET
302 bool
303
Ran Wang9798b662017-12-20 10:34:20 +0800[diff] [blame]304config USB_EHCI_FSL
305 bool "Support for FSL on-chip EHCI USB controller"
Tom Rini30fd3d92022-06-08 08:24:27 -0400[diff] [blame]306 select EHCI_HCD_INIT_AFTER_RESET
Tom Rini8d7aa572022-07-31 21:08:29 -0400[diff] [blame]307 select SYS_FSL_USB_INTERNAL_UTMI_PHY if MPC85xx && \
308 !(ARCH_B4860 || ARCH_B4420 || ARCH_P4080 || ARCH_P1020 || ARCH_P2020)
Ran Wang9798b662017-12-20 10:34:20 +0800[diff] [blame]309 ---help---
310 Enables support for the on-chip EHCI controller on FSL chips.
Tom Rinic85a7922022-06-08 08:24:31 -0400[diff] [blame]311
Tom Rini8d7aa572022-07-31 21:08:29 -0400[diff] [blame]312config SYS_FSL_USB_INTERNAL_UTMI_PHY
313 bool
314 depends on USB_EHCI_FSL
315
Tom Rinic85a7922022-06-08 08:24:31 -0400[diff] [blame]316config USB_EHCI_TXFIFO_THRESH
317 hex
318 depends on USB_EHCI_TEGRA
319 default 0x10
320 help
321 This parameter affects a TXFILLTUNING field that controls how much
322 data is sent to the latency fifo before it is sent to the wire.
323 Without this parameter, the default (2) causes occasional Data Buffer
324 Errors in OUT packets depending on the buffer address and size.
325
Masahiro Yamada78a9c792016-08-01 00:16:32 +0900[diff] [blame]326endif # USB_EHCI_HCD
327
Tom Rini112d2e02022-06-25 11:02:31 -0400[diff] [blame]328config USB_OHCI_NEW
329 bool
330
331config SYS_USB_OHCI_CPU_INIT
332 bool
333
Masahiro Yamada78a9c792016-08-01 00:16:32 +0900[diff] [blame]334config USB_OHCI_HCD
335 bool "OHCI HCD (USB 1.1) support"
Tom Rini5b9e6162021-07-09 10:11:56 -0400[diff] [blame]336 depends on DM && OF_CONTROL
337 select USB_HOST
Tom Rini112d2e02022-06-25 11:02:31 -0400[diff] [blame]338 select USB_OHCI_NEW
Masahiro Yamada78a9c792016-08-01 00:16:32 +0900[diff] [blame]339 ---help---
340 The Open Host Controller Interface (OHCI) is a standard for accessing
341 USB 1.1 host controller hardware. It does more in hardware than Intel's
342 UHCI specification. If your USB host controller follows the OHCI spec,
343 say Y. On most non-x86 systems, and on x86 hardware that's not using a
344 USB controller from Intel or VIA, this is appropriate. If your host
345 controller doesn't use PCI, this is probably appropriate. For a PCI
346 based system where you're not sure, the "lspci -v" entry will list the
347 right "prog-if" for your USB controller(s): EHCI, OHCI, or UHCI.
348
Tom Rini5b9e6162021-07-09 10:11:56 -0400[diff] [blame]349if USB_OHCI_HCD
350
Heiko Schocher124f9472019-07-16 10:49:07 +0200[diff] [blame]351config USB_OHCI_PCI
352 bool "Support for PCI-based OHCI USB controller"
Tom Rini5b9e6162021-07-09 10:11:56 -0400[diff] [blame]353 depends on PCI
Heiko Schocher124f9472019-07-16 10:49:07 +0200[diff] [blame]354 help
355 Enables support for the PCI-based OHCI controller.
356
Masahiro Yamada78a9c792016-08-01 00:16:32 +0900[diff] [blame]357config USB_OHCI_GENERIC
358 bool "Support for generic OHCI USB controller"
Jagan Teki1ba41e12018-12-22 18:18:10 +0530[diff] [blame]359 default ARCH_SUNXI
Masahiro Yamada78a9c792016-08-01 00:16:32 +0900[diff] [blame]360 ---help---
361 Enables support for generic OHCI controller.
362
Adam Ford5f364f52019-04-30 05:21:41 -0500[diff] [blame]363config USB_OHCI_DA8XX
364 bool "Support for da850 OHCI USB controller"
365 help
366 Enable support for the da850 USB controller.
367
Jim Liu1fd3b3d2022-06-21 17:09:02 +0800[diff] [blame]368config USB_OHCI_NPCM
369 bool "Support for Nuvoton NPCM on-chip OHCI USB controller"
370 depends on ARCH_NPCM
371 default n
372 ---help---
373 Enables support for the on-chip OHCI controller on
374 Nuvoton NPCM chips.
375
Masahiro Yamada78a9c792016-08-01 00:16:32 +0900[diff] [blame]376endif # USB_OHCI_HCD
Masahiro Yamada718ba3c2016-08-01 00:16:33 +0900[diff] [blame]377
Tom Rini112d2e02022-06-25 11:02:31 -0400[diff] [blame]378config SYS_USB_OHCI_SLOT_NAME
379 string "Display name for the OHCI controller"
380 depends on USB_OHCI_NEW && !DM_USB
381
Tom Rini112d2e02022-06-25 11:02:31 -0400[diff] [blame]382config SYS_OHCI_SWAP_REG_ACCESS
383 bool "Perform byte swapping on OHCI controller register accesses"
384 depends on USB_OHCI_NEW
385
Masahiro Yamada718ba3c2016-08-01 00:16:33 +0900[diff] [blame]386config USB_UHCI_HCD
387 bool "UHCI HCD (most Intel and VIA) support"
Masahiro Yamada59cfdc02016-08-01 00:16:34 +0900[diff] [blame]388 select USB_HOST
Masahiro Yamada718ba3c2016-08-01 00:16:33 +0900[diff] [blame]389 ---help---
390 The Universal Host Controller Interface is a standard by Intel for
391 accessing the USB hardware in the PC (which is also called the USB
392 host controller). If your USB host controller conforms to this
393 standard, you may want to say Y, but see below. All recent boards
394 with Intel PCI chipsets (like intel 430TX, 440FX, 440LX, 440BX,
395 i810, i820) conform to this standard. Also all VIA PCI chipsets
396 (like VIA VP2, VP3, MVP3, Apollo Pro, Apollo Pro II or Apollo Pro
397 133) and LEON/GRLIB SoCs with the GRUSBHC controller.
398 If unsure, say Y.
399
400if USB_UHCI_HCD
401
402endif # USB_UHCI_HCD
Philipp Tomsich54983812017-07-03 18:30:06 +0200[diff] [blame]403
404config USB_DWC2
405 bool "DesignWare USB2 Core support"
Tom Rini5b9e6162021-07-09 10:11:56 -0400[diff] [blame]406 depends on DM && OF_CONTROL
Philipp Tomsich54983812017-07-03 18:30:06 +0200[diff] [blame]407 select USB_HOST
408 ---help---
409 The DesignWare USB 2.0 controller is compliant with the
410 USB-Implementers Forum (USB-IF) USB 2.0 specifications.
411 Hi-Speed (480 Mbps), Full-Speed (12 Mbps), and Low-Speed (1.5 Mbps)
412 operation is compliant to the controller Supplement. If you want to
413 enable this controller in host mode, say Y.
Alexey Brodkinf19414b2018-02-28 16:16:58 +0300[diff] [blame]414
415if USB_DWC2
416config USB_DWC2_BUFFER_SIZE
417 int "Data buffer size in kB"
418 default 64
419 ---help---
420 By default 64 kB buffer is used but if amount of RAM avaialble on
421 the target is not enough to accommodate allocation of buffer of
422 that size it is possible to shrink it. Smaller sizes should be fine
423 because larger transactions could be split in smaller ones.
424
425endif # USB_DWC2
Marek Vasut88016032019-08-11 13:23:43 +0200[diff] [blame]426
427config USB_R8A66597_HCD
428 bool "Renesas R8A66597 USB Core support"
Tom Rini5b9e6162021-07-09 10:11:56 -0400[diff] [blame]429 depends on DM && OF_CONTROL
Marek Vasut88016032019-08-11 13:23:43 +0200[diff] [blame]430 select USB_HOST
431 ---help---
432 This enables support for the on-chip Renesas R8A66597 USB 2.0
433 controller, present in various RZ and SH SoCs.
Tom Rinibde21702022-06-12 20:02:04 -0400[diff] [blame]434
Tom Rini112d2e02022-06-25 11:02:31 -0400[diff] [blame]435config USB_ATMEL
436 bool "AT91 OHCI USB support"
437 depends on ARCH_AT91
438 select SYS_USB_OHCI_CPU_INIT
439 select USB_OHCI_NEW
440
441choice
442 prompt "Clock for OHCI"
443 depends on USB_ATMEL
444
445config USB_ATMEL_CLK_SEL_PLLB
446 bool "PLLB"
447
448config USB_ATMEL_CLK_SEL_UPLL
449 bool "UPLL"
450
451endchoice
452
453config USB_OHCI_LPC32XX
454 bool "LPC32xx USB OHCI support"
455 depends on ARCH_LPC32XX
456 select SYS_USB_OHCI_CPU_INIT
457 select USB_OHCI_NEW
458
Tom Rinibde21702022-06-12 20:02:04 -0400[diff] [blame]459config USB_MAX_CONTROLLER_COUNT
460 int "Maximum number of USB host controllers"
461 depends on USB_EHCI_FSL || USB_XHCI_FSL || \
462 (SPL_USB_HOST && !DM_SPL_USB) || (USB_HOST && !DM_USB)
463 default 1