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wdenke3a06802004-06-06 23:13:55 +00001/*
wdenk914be132004-06-08 00:22:43 +00002 * (C) Copyright 2003-2004
wdenke3a06802004-06-06 23:13:55 +00003 * MPC Data Limited (http://www.mpc-data.co.uk)
4 * Dave Peverley <dpeverley at mpc-data.co.uk>
5 *
6 * Configuation settings for the TI OMAP Perseus 2 board.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenk914be132004-06-08 00:22:43 +000018 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenke3a06802004-06-06 23:13:55 +000019 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
wdenke3a06802004-06-06 23:13:55 +000030/* allow to overwrite serial and ethaddr */
31#define CONFIG_ENV_OVERWRITE
32
wdenke3a06802004-06-06 23:13:55 +000033/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
wdenk914be132004-06-08 00:22:43 +000038#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
39#define CONFIG_OMAP 1 /* in a TI OMAP core */
40#define CONFIG_OMAP730 1 /* which is in a 730 */
41#define CONFIG_P2_OMAP730 1 /* a Perseus 2 Board */
wdenke3a06802004-06-06 23:13:55 +000042
wdenk914be132004-06-08 00:22:43 +000043/*
44 * Input clock of PLL
45 * The OMAP730 Perseus 2 has 13MHz input clock
wdenke3a06802004-06-06 23:13:55 +000046 */
47
wdenk914be132004-06-08 00:22:43 +000048#define CONFIG_SYS_CLK_FREQ 13000000
wdenke3a06802004-06-06 23:13:55 +000049
wdenk914be132004-06-08 00:22:43 +000050#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
wdenke3a06802004-06-06 23:13:55 +000051
wdenk914be132004-06-08 00:22:43 +000052#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
wdenke3a06802004-06-06 23:13:55 +000053#define CONFIG_SETUP_MEMORY_TAGS 1
54
wdenke3a06802004-06-06 23:13:55 +000055/*
56 * Size of malloc() pool
57 */
58
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020059#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
wdenke3a06802004-06-06 23:13:55 +000060
61/*
62 * Hardware drivers
63 */
64
Nishanth Menonee1c20f2009-10-16 00:06:37 -050065#define CONFIG_LAN91C96
wdenk914be132004-06-08 00:22:43 +000066#define CONFIG_LAN91C96_BASE 0x04000300
wdenke3a06802004-06-06 23:13:55 +000067#define CONFIG_LAN91C96_EXT_PHY
68
wdenke3a06802004-06-06 23:13:55 +000069/*
70 * NS16550 Configuration
71 */
72
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020073#define CONFIG_SYS_NS16550
74#define CONFIG_SYS_NS16550_SERIAL
75#define CONFIG_SYS_NS16550_REG_SIZE (1)
76#define CONFIG_SYS_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */
77#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart
wdenk914be132004-06-08 00:22:43 +000078 * on perseus */
wdenke3a06802004-06-06 23:13:55 +000079
80/*
81 * select serial console configuration
82 */
83
wdenk914be132004-06-08 00:22:43 +000084#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP730 Perseus 2 */
wdenke3a06802004-06-06 23:13:55 +000085
wdenk914be132004-06-08 00:22:43 +000086#define CONFIG_CONS_INDEX 1
87#define CONFIG_BAUDRATE 115200
wdenke3a06802004-06-06 23:13:55 +000088
wdenk914be132004-06-08 00:22:43 +000089/*
Jon Loeliger4bd7e1b2007-07-04 22:33:13 -050090 * Command line configuration.
wdenke3a06802004-06-06 23:13:55 +000091 */
Jon Loeliger4bd7e1b2007-07-04 22:33:13 -050092#include <config_cmd_default.h>
93
94#define CONFIG_CMD_DHCP
95
wdenke3a06802004-06-06 23:13:55 +000096
Jon Loeligerc6d535a2007-07-09 21:57:31 -050097/*
98 * BOOTP options
99 */
100#define CONFIG_BOOTP_SUBNETMASK
101#define CONFIG_BOOTP_GATEWAY
102#define CONFIG_BOOTP_HOSTNAME
103#define CONFIG_BOOTP_BOOTPATH
104
Jon Loeliger4bd7e1b2007-07-04 22:33:13 -0500105
wdenke3a06802004-06-06 23:13:55 +0000106#include <configs/omap730.h>
107#include <configs/h2_p2_dbg_board.h>
108
wdenk914be132004-06-08 00:22:43 +0000109#define CONFIG_BOOTDELAY 3
110#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw ip=bootp"
wdenke3a06802004-06-06 23:13:55 +0000111
wdenk914be132004-06-08 00:22:43 +0000112#define CONFIG_LOADADDR 0x10000000
wdenke3a06802004-06-06 23:13:55 +0000113
114#define CONFIG_ETHADDR
wdenk914be132004-06-08 00:22:43 +0000115#define CONFIG_NETMASK 255.255.255.0
116#define CONFIG_IPADDR 192.168.0.23
117#define CONFIG_SERVERIP 192.150.0.100
118#define CONFIG_BOOTFILE "uImage" /* File to load */
wdenke3a06802004-06-06 23:13:55 +0000119
Jon Loeliger4bd7e1b2007-07-04 22:33:13 -0500120#if defined(CONFIG_CMD_KGDB)
wdenk914be132004-06-08 00:22:43 +0000121#define CONFIG_KGDB_BAUDRATE 115200 /* Speed to run kgdb serial port */
122#define CONFIG_KGDB_SER_INDEX 1 /* Which serial port to use */
wdenke3a06802004-06-06 23:13:55 +0000123#endif
124
wdenke3a06802004-06-06 23:13:55 +0000125/*
126 * Miscellaneous configurable options
127 */
128
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200129#define CONFIG_SYS_LONGHELP /* undef to save memory */
130#define CONFIG_SYS_PROMPT "OMAP730 P2 # " /* Monitor Command Prompt */
131#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenke3a06802004-06-06 23:13:55 +0000132/* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200133#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
134#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
135#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenke3a06802004-06-06 23:13:55 +0000136
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200137#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */
138#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */
wdenke3a06802004-06-06 23:13:55 +0000139
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200140#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */
wdenke3a06802004-06-06 23:13:55 +0000141
wdenk914be132004-06-08 00:22:43 +0000142/* The OMAP730 has 3 general purpose MPU timers, they can be driven by
143 * the RefClk (12Mhz) or by DPLL1. This time is further subdivided by a
wdenke3a06802004-06-06 23:13:55 +0000144 * local divisor.
145 */
Ladislav Michl993e57d2009-03-30 18:58:41 +0200146#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */
147#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
148#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
wdenke3a06802004-06-06 23:13:55 +0000149
150/*-----------------------------------------------------------------------
151 * Stack sizes
152 *
153 * The stack sizes are set up in start.S using the settings below
154 */
155
wdenk914be132004-06-08 00:22:43 +0000156#define CONFIG_STACKSIZE (128*1024) /* regular stack */
wdenke3a06802004-06-06 23:13:55 +0000157#ifdef CONFIG_USE_IRQ
wdenk914be132004-06-08 00:22:43 +0000158#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
159#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
wdenke3a06802004-06-06 23:13:55 +0000160#endif
161
wdenke3a06802004-06-06 23:13:55 +0000162/*-----------------------------------------------------------------------
163 * Physical Memory Map
164 */
165
wdenk914be132004-06-08 00:22:43 +0000166#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
167#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
168#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
wdenke3a06802004-06-06 23:13:55 +0000169
170#if defined(CONFIG_CS0_BOOT)
wdenk914be132004-06-08 00:22:43 +0000171#define PHYS_FLASH_1 0x0C000000
wdenke3a06802004-06-06 23:13:55 +0000172#elif defined(CONFIG_CS3_BOOT)
wdenk914be132004-06-08 00:22:43 +0000173#define PHYS_FLASH_1 0x00000000
wdenke3a06802004-06-06 23:13:55 +0000174#else
175#error Unknown Boot Chip-Select number
176#endif
177
Aneesh V963bff72011-06-09 08:54:57 -0400178#define PHYS_SRAM 0x20000000
179
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200180#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
wdenke3a06802004-06-06 23:13:55 +0000181
182/*-----------------------------------------------------------------------
183 * FLASH and environment organization
184 */
185
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200186#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
wdenk914be132004-06-08 00:22:43 +0000187#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200188#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
wdenke3a06802004-06-06 23:13:55 +0000189/* addr of environment */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200190#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x020000)
wdenke3a06802004-06-06 23:13:55 +0000191
192/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200193#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
194#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenke3a06802004-06-06 23:13:55 +0000195
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200196#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200197#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
198#define CONFIG_ENV_OFFSET 0x20000 /* environment starts here */
wdenke3a06802004-06-06 23:13:55 +0000199
Aneesh V963bff72011-06-09 08:54:57 -0400200#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
201#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM
202
wdenk914be132004-06-08 00:22:43 +0000203#endif /* ! __CONFIG_H */