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wdenke3a06802004-06-06 23:13:55 +00001/*
wdenk914be132004-06-08 00:22:43 +00002 * (C) Copyright 2003-2004
wdenke3a06802004-06-06 23:13:55 +00003 * MPC Data Limited (http://www.mpc-data.co.uk)
4 * Dave Peverley <dpeverley at mpc-data.co.uk>
5 *
6 * Configuation settings for the TI OMAP Perseus 2 board.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenk914be132004-06-08 00:22:43 +000018 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenke3a06802004-06-06 23:13:55 +000019 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
wdenke3a06802004-06-06 23:13:55 +000030/* allow to overwrite serial and ethaddr */
31#define CONFIG_ENV_OVERWRITE
32
wdenke3a06802004-06-06 23:13:55 +000033/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
wdenk914be132004-06-08 00:22:43 +000038#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
39#define CONFIG_OMAP 1 /* in a TI OMAP core */
40#define CONFIG_OMAP730 1 /* which is in a 730 */
41#define CONFIG_P2_OMAP730 1 /* a Perseus 2 Board */
wdenke3a06802004-06-06 23:13:55 +000042
wdenk914be132004-06-08 00:22:43 +000043/*
44 * Input clock of PLL
45 * The OMAP730 Perseus 2 has 13MHz input clock
wdenke3a06802004-06-06 23:13:55 +000046 */
47
wdenk914be132004-06-08 00:22:43 +000048#define CONFIG_SYS_CLK_FREQ 13000000
wdenke3a06802004-06-06 23:13:55 +000049
wdenk914be132004-06-08 00:22:43 +000050#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
wdenke3a06802004-06-06 23:13:55 +000051
52#define CONFIG_MISC_INIT_R
53
wdenk914be132004-06-08 00:22:43 +000054#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
wdenke3a06802004-06-06 23:13:55 +000055#define CONFIG_SETUP_MEMORY_TAGS 1
56
wdenke3a06802004-06-06 23:13:55 +000057/*
58 * Size of malloc() pool
59 */
60
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020061#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
62#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
wdenke3a06802004-06-06 23:13:55 +000063
64/*
65 * Hardware drivers
66 */
67
Nishanth Menonee1c20f2009-10-16 00:06:37 -050068#define CONFIG_NET_MULTI
69#define CONFIG_LAN91C96
wdenk914be132004-06-08 00:22:43 +000070#define CONFIG_LAN91C96_BASE 0x04000300
wdenke3a06802004-06-06 23:13:55 +000071#define CONFIG_LAN91C96_EXT_PHY
72
wdenke3a06802004-06-06 23:13:55 +000073/*
74 * NS16550 Configuration
75 */
76
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020077#define CONFIG_SYS_NS16550
78#define CONFIG_SYS_NS16550_SERIAL
79#define CONFIG_SYS_NS16550_REG_SIZE (1)
80#define CONFIG_SYS_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */
81#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart
wdenk914be132004-06-08 00:22:43 +000082 * on perseus */
wdenke3a06802004-06-06 23:13:55 +000083
84/*
85 * select serial console configuration
86 */
87
wdenk914be132004-06-08 00:22:43 +000088#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP730 Perseus 2 */
wdenke3a06802004-06-06 23:13:55 +000089
wdenk914be132004-06-08 00:22:43 +000090#define CONFIG_CONS_INDEX 1
91#define CONFIG_BAUDRATE 115200
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020092#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenke3a06802004-06-06 23:13:55 +000093
wdenke3a06802004-06-06 23:13:55 +000094
wdenk914be132004-06-08 00:22:43 +000095/*
Jon Loeliger4bd7e1b2007-07-04 22:33:13 -050096 * Command line configuration.
wdenke3a06802004-06-06 23:13:55 +000097 */
Jon Loeliger4bd7e1b2007-07-04 22:33:13 -050098#include <config_cmd_default.h>
99
100#define CONFIG_CMD_DHCP
101
wdenke3a06802004-06-06 23:13:55 +0000102
Jon Loeligerc6d535a2007-07-09 21:57:31 -0500103/*
104 * BOOTP options
105 */
106#define CONFIG_BOOTP_SUBNETMASK
107#define CONFIG_BOOTP_GATEWAY
108#define CONFIG_BOOTP_HOSTNAME
109#define CONFIG_BOOTP_BOOTPATH
110
Jon Loeliger4bd7e1b2007-07-04 22:33:13 -0500111
wdenke3a06802004-06-06 23:13:55 +0000112#include <configs/omap730.h>
113#include <configs/h2_p2_dbg_board.h>
114
wdenk914be132004-06-08 00:22:43 +0000115#define CONFIG_BOOTDELAY 3
116#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw ip=bootp"
wdenke3a06802004-06-06 23:13:55 +0000117
wdenk914be132004-06-08 00:22:43 +0000118#define CONFIG_LOADADDR 0x10000000
wdenke3a06802004-06-06 23:13:55 +0000119
120#define CONFIG_ETHADDR
wdenk914be132004-06-08 00:22:43 +0000121#define CONFIG_NETMASK 255.255.255.0
122#define CONFIG_IPADDR 192.168.0.23
123#define CONFIG_SERVERIP 192.150.0.100
124#define CONFIG_BOOTFILE "uImage" /* File to load */
wdenke3a06802004-06-06 23:13:55 +0000125
Jon Loeliger4bd7e1b2007-07-04 22:33:13 -0500126#if defined(CONFIG_CMD_KGDB)
wdenk914be132004-06-08 00:22:43 +0000127#define CONFIG_KGDB_BAUDRATE 115200 /* Speed to run kgdb serial port */
128#define CONFIG_KGDB_SER_INDEX 1 /* Which serial port to use */
wdenke3a06802004-06-06 23:13:55 +0000129#endif
130
wdenke3a06802004-06-06 23:13:55 +0000131/*
132 * Miscellaneous configurable options
133 */
134
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200135#define CONFIG_SYS_LONGHELP /* undef to save memory */
136#define CONFIG_SYS_PROMPT "OMAP730 P2 # " /* Monitor Command Prompt */
137#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenke3a06802004-06-06 23:13:55 +0000138/* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200139#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
140#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
141#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenke3a06802004-06-06 23:13:55 +0000142
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200143#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */
144#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */
wdenke3a06802004-06-06 23:13:55 +0000145
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200146#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */
wdenke3a06802004-06-06 23:13:55 +0000147
wdenk914be132004-06-08 00:22:43 +0000148/* The OMAP730 has 3 general purpose MPU timers, they can be driven by
149 * the RefClk (12Mhz) or by DPLL1. This time is further subdivided by a
wdenke3a06802004-06-06 23:13:55 +0000150 * local divisor.
151 */
Ladislav Michl993e57d2009-03-30 18:58:41 +0200152#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */
153#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
154#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
wdenke3a06802004-06-06 23:13:55 +0000155
156/*-----------------------------------------------------------------------
157 * Stack sizes
158 *
159 * The stack sizes are set up in start.S using the settings below
160 */
161
wdenk914be132004-06-08 00:22:43 +0000162#define CONFIG_STACKSIZE (128*1024) /* regular stack */
wdenke3a06802004-06-06 23:13:55 +0000163#ifdef CONFIG_USE_IRQ
wdenk914be132004-06-08 00:22:43 +0000164#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
165#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
wdenke3a06802004-06-06 23:13:55 +0000166#endif
167
wdenke3a06802004-06-06 23:13:55 +0000168/*-----------------------------------------------------------------------
169 * Physical Memory Map
170 */
171
wdenk914be132004-06-08 00:22:43 +0000172#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
173#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
174#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
wdenke3a06802004-06-06 23:13:55 +0000175
176#if defined(CONFIG_CS0_BOOT)
wdenk914be132004-06-08 00:22:43 +0000177#define PHYS_FLASH_1 0x0C000000
wdenke3a06802004-06-06 23:13:55 +0000178#elif defined(CONFIG_CS3_BOOT)
wdenk914be132004-06-08 00:22:43 +0000179#define PHYS_FLASH_1 0x00000000
wdenke3a06802004-06-06 23:13:55 +0000180#else
181#error Unknown Boot Chip-Select number
182#endif
183
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200184#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
wdenke3a06802004-06-06 23:13:55 +0000185
186/*-----------------------------------------------------------------------
187 * FLASH and environment organization
188 */
189
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200190#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
wdenk914be132004-06-08 00:22:43 +0000191#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200192#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
wdenke3a06802004-06-06 23:13:55 +0000193/* addr of environment */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200194#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x020000)
wdenke3a06802004-06-06 23:13:55 +0000195
196/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200197#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
198#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenke3a06802004-06-06 23:13:55 +0000199
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200200#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200201#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
202#define CONFIG_ENV_OFFSET 0x20000 /* environment starts here */
wdenke3a06802004-06-06 23:13:55 +0000203
wdenk914be132004-06-08 00:22:43 +0000204#endif /* ! __CONFIG_H */