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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Dinh Nguyenad51f7c2012-10-04 06:46:02 +00002/*
Ley Foon Tanb149f2b2017-04-26 02:44:36 +08003 * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
Dinh Nguyenad51f7c2012-10-04 06:46:02 +00004 */
5
6#include <common.h>
Simon Glassed38aef2020-05-10 11:40:03 -06007#include <command.h>
Simon Glass1d91ba72019-11-14 12:57:37 -07008#include <cpu_func.h>
Simon Glassf11478f2019-12-28 10:45:07 -07009#include <hang.h>
Simon Glass274e0b02020-05-10 11:39:56 -060010#include <asm/cache.h>
Simon Glass97589732020-05-10 11:40:02 -060011#include <init.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060012#include <asm/global_data.h>
Dinh Nguyenad51f7c2012-10-04 06:46:02 +000013#include <asm/io.h>
Dinh Nguyen8ed66612015-08-01 03:42:10 +020014#include <errno.h>
Marek Vasutf3f8fe22015-07-25 19:33:56 +020015#include <fdtdec.h>
Masahiro Yamada75f82d02018-03-05 01:20:11 +090016#include <linux/libfdt.h>
Pavel Machekc7213802014-09-08 14:08:45 +020017#include <altera.h>
Pavel Machekce340e92014-07-14 14:14:17 +020018#include <miiphy.h>
19#include <netdev.h>
Stefan Roese3bfb5912014-12-19 13:49:10 +010020#include <watchdog.h>
Ley Foon Tanb149f2b2017-04-26 02:44:36 +080021#include <asm/arch/misc.h>
Pavel Machek56a00ab2014-09-09 14:03:28 +020022#include <asm/arch/reset_manager.h>
Dinh Nguyen8ed66612015-08-01 03:42:10 +020023#include <asm/arch/scan_manager.h>
Pavel Machek57d75eb2014-09-08 14:08:45 +020024#include <asm/arch/system_manager.h>
Marek Vasut56916e42014-09-15 03:58:22 +020025#include <asm/arch/nic301.h>
Pavel Macheke918e332014-09-08 14:08:45 +020026#include <asm/arch/scu.h>
Marek Vasut56916e42014-09-15 03:58:22 +020027#include <asm/pl310.h>
Dinh Nguyenad51f7c2012-10-04 06:46:02 +000028
29DECLARE_GLOBAL_DATA_PTR;
30
Ley Foon Tan26695912019-11-08 10:38:21 +080031phys_addr_t socfpga_clkmgr_base __section(".data");
Ley Foon Tanfed4c952019-11-08 10:38:19 +080032phys_addr_t socfpga_rstmgr_base __section(".data");
Ley Foon Tan3d3a8602019-11-08 10:38:20 +080033phys_addr_t socfpga_sysmgr_base __section(".data");
Ley Foon Tanfed4c952019-11-08 10:38:19 +080034
Ley Foon Tan6fa091d2018-05-18 22:05:25 +080035#ifdef CONFIG_SYS_L2_PL310
Ley Foon Tanb149f2b2017-04-26 02:44:36 +080036static const struct pl310_regs *const pl310 =
Marek Vasut56916e42014-09-15 03:58:22 +020037 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
Ley Foon Tan6fa091d2018-05-18 22:05:25 +080038#endif
Ley Foon Tanb149f2b2017-04-26 02:44:36 +080039
40struct bsel bsel_str[] = {
41 { "rsvd", "Reserved", },
42 { "fpga", "FPGA (HPS2FPGA Bridge)", },
43 { "nand", "NAND Flash (1.8V)", },
44 { "nand", "NAND Flash (3.0V)", },
45 { "sd", "SD/MMC External Transceiver (1.8V)", },
46 { "sd", "SD/MMC Internal Transceiver (3.0V)", },
47 { "qspi", "QSPI Flash (1.8V)", },
48 { "qspi", "QSPI Flash (3.0V)", },
49};
Pavel Machek57d75eb2014-09-08 14:08:45 +020050
Dinh Nguyenad51f7c2012-10-04 06:46:02 +000051int dram_init(void)
52{
Siva Durga Prasad Paladugub3d55ea2018-07-16 15:56:11 +053053 if (fdtdec_setup_mem_size_base() != 0)
Marek Vasut15303172018-05-28 17:09:45 +020054 return -EINVAL;
55
Dinh Nguyenad51f7c2012-10-04 06:46:02 +000056 return 0;
57}
Pavel Machek57d75eb2014-09-08 14:08:45 +020058
Marek Vasutd5157942014-09-21 13:57:40 +020059void enable_caches(void)
60{
Trevor Woerner43ec7e02019-05-03 09:41:00 -040061#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
Marek Vasutd5157942014-09-21 13:57:40 +020062 icache_enable();
63#endif
Trevor Woerner43ec7e02019-05-03 09:41:00 -040064#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
Marek Vasutd5157942014-09-21 13:57:40 +020065 dcache_enable();
66#endif
67}
68
Ley Foon Tan6fa091d2018-05-18 22:05:25 +080069#ifdef CONFIG_SYS_L2_PL310
Dinh Nguyene89ff702015-10-15 10:13:36 -050070void v7_outer_cache_enable(void)
71{
Dinh Nguyen86fbf9d2019-04-23 16:55:05 -050072 struct udevice *dev;
Marek Vasut9f7b30d2015-12-20 04:00:09 +010073
Dinh Nguyen86fbf9d2019-04-23 16:55:05 -050074 if (uclass_get_device(UCLASS_CACHE, 0, &dev))
75 pr_err("cache controller driver NOT found!\n");
Marek Vasut9f7b30d2015-12-20 04:00:09 +010076}
77
78void v7_outer_cache_disable(void)
79{
80 /* Disable the L2 cache */
81 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
Dinh Nguyene89ff702015-10-15 10:13:36 -050082}
Marek Vasutb6ba4902019-03-21 23:05:38 +010083
84void socfpga_pl310_clear(void)
85{
86 u32 mask = 0xff, ena = 0;
87
88 icache_enable();
89
90 /* Disable the L2 cache */
91 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
92
93 writel(0x0, &pl310->pl310_tag_latency_ctrl);
94 writel(0x10, &pl310->pl310_data_latency_ctrl);
95
96 /* enable BRESP, instruction and data prefetch, full line of zeroes */
97 setbits_le32(&pl310->pl310_aux_ctrl,
98 L310_AUX_CTRL_DATA_PREFETCH_MASK |
99 L310_AUX_CTRL_INST_PREFETCH_MASK |
100 L310_SHARED_ATT_OVERRIDE_ENABLE);
101
102 /* Enable the L2 cache */
103 ena = readl(&pl310->pl310_ctrl);
104 ena |= L2X0_CTRL_EN;
105
106 /*
107 * Invalidate the PL310 L2 cache. Keep the invalidation code
108 * entirely in L1 I-cache to avoid any bus traffic through
109 * the L2.
110 */
111 asm volatile(
112 ".align 5 \n"
113 " b 3f \n"
114 "1: str %1, [%4] \n"
115 " dsb \n"
116 " isb \n"
117 " str %0, [%2] \n"
118 " dsb \n"
119 " isb \n"
120 "2: ldr %0, [%2] \n"
121 " cmp %0, #0 \n"
122 " bne 2b \n"
123 " str %0, [%3] \n"
124 " dsb \n"
125 " isb \n"
126 " b 4f \n"
127 "3: b 1b \n"
128 "4: nop \n"
129 : "+r"(mask), "+r"(ena)
130 : "r"(&pl310->pl310_inv_way),
131 "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
132 : "memory", "cc");
133
134 /* Disable the L2 cache */
135 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
136}
Ley Foon Tan6fa091d2018-05-18 22:05:25 +0800137#endif
Dinh Nguyene89ff702015-10-15 10:13:36 -0500138
Chin Liang Seebff262c2014-06-10 02:23:45 -0500139#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
140defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
141int overwrite_console(void)
142{
143 return 0;
144}
145#endif
146
Pavel Machekc7213802014-09-08 14:08:45 +0200147#ifdef CONFIG_FPGA
Pavel Machekc7213802014-09-08 14:08:45 +0200148/* add device descriptor to FPGA device table */
Ang, Chee Hongff14f162018-12-19 18:35:15 -0800149void socfpga_fpga_add(void *fpga_desc)
Pavel Machekc7213802014-09-08 14:08:45 +0200150{
Pavel Machekc7213802014-09-08 14:08:45 +0200151 fpga_init();
Ang, Chee Hongff14f162018-12-19 18:35:15 -0800152 fpga_add(fpga_altera, fpga_desc);
Pavel Machekc7213802014-09-08 14:08:45 +0200153}
Pavel Machekc7213802014-09-08 14:08:45 +0200154#endif
155
Pavel Machek56a00ab2014-09-09 14:03:28 +0200156int arch_cpu_init(void)
157{
Ley Foon Tanfed4c952019-11-08 10:38:19 +0800158 socfpga_get_managers_addr();
159
Stefan Roese3bfb5912014-12-19 13:49:10 +0100160#ifdef CONFIG_HW_WATCHDOG
161 /*
162 * In case the watchdog is enabled, make sure to (re-)configure it
163 * so that the defined timeout is valid. Otherwise the SPL (Perloader)
164 * timeout value is still active which might too short for Linux
165 * booting.
166 */
167 hw_watchdog_init();
168#else
Pavel Machek56a00ab2014-09-09 14:03:28 +0200169 /*
170 * If the HW watchdog is NOT enabled, make sure it is not running,
171 * for example because it was enabled in the preloader. This might
172 * trigger a watchdog-triggered reboot of Linux kernel later.
Marek Vasut75f6b5c2015-07-09 02:51:56 +0200173 * Toggle watchdog reset, so watchdog in not running state.
Pavel Machek56a00ab2014-09-09 14:03:28 +0200174 */
Marek Vasut75f6b5c2015-07-09 02:51:56 +0200175 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
176 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
Pavel Machek56a00ab2014-09-09 14:03:28 +0200177#endif
Stefan Roese3bfb5912014-12-19 13:49:10 +0100178
Pavel Machek56a00ab2014-09-09 14:03:28 +0200179 return 0;
180}
Marek Vasut3386c852018-04-23 22:49:31 +0200181
Ley Foon Tan4cc6b582018-05-24 00:17:23 +0800182#ifndef CONFIG_SPL_BUILD
Simon Glassed38aef2020-05-10 11:40:03 -0600183static int do_bridge(struct cmd_tbl *cmdtp, int flag, int argc,
184 char *const argv[])
Ley Foon Tan4cc6b582018-05-24 00:17:23 +0800185{
Marek Vasut713a8a22019-04-16 22:28:08 +0200186 unsigned int mask = ~0;
187
188 if (argc < 2 || argc > 3)
Ley Foon Tan4cc6b582018-05-24 00:17:23 +0800189 return CMD_RET_USAGE;
190
191 argv++;
192
Marek Vasut713a8a22019-04-16 22:28:08 +0200193 if (argc == 3)
Simon Glass3ff49ec2021-07-24 09:03:29 -0600194 mask = hextoul(argv[1], NULL);
Marek Vasut713a8a22019-04-16 22:28:08 +0200195
Ley Foon Tan4cc6b582018-05-24 00:17:23 +0800196 switch (*argv[0]) {
197 case 'e': /* Enable */
Marek Vasut713a8a22019-04-16 22:28:08 +0200198 do_bridge_reset(1, mask);
Ley Foon Tan4cc6b582018-05-24 00:17:23 +0800199 break;
200 case 'd': /* Disable */
Marek Vasut713a8a22019-04-16 22:28:08 +0200201 do_bridge_reset(0, mask);
Ley Foon Tan4cc6b582018-05-24 00:17:23 +0800202 break;
203 default:
204 return CMD_RET_USAGE;
205 }
206
207 return 0;
208}
209
Marek Vasut713a8a22019-04-16 22:28:08 +0200210U_BOOT_CMD(bridge, 3, 1, do_bridge,
Ley Foon Tanf9c7f792018-05-24 00:17:30 +0800211 "SoCFPGA HPS FPGA bridge control",
Marek Vasut713a8a22019-04-16 22:28:08 +0200212 "enable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
213 "bridge disable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
Ley Foon Tanf9c7f792018-05-24 00:17:30 +0800214 ""
Ley Foon Tan4cc6b582018-05-24 00:17:23 +0800215);
216
217#endif
Ley Foon Tanfed4c952019-11-08 10:38:19 +0800218
219static int socfpga_get_base_addr(const char *compat, phys_addr_t *base)
220{
221 const void *blob = gd->fdt_blob;
222 struct fdt_resource r;
223 int node;
224 int ret;
225
226 node = fdt_node_offset_by_compatible(blob, -1, compat);
227 if (node < 0)
228 return node;
229
230 if (!fdtdec_get_is_enabled(blob, node))
231 return -ENODEV;
232
233 ret = fdt_get_resource(blob, node, "reg", 0, &r);
234 if (ret)
235 return ret;
236
237 *base = (phys_addr_t)r.start;
238
239 return 0;
240}
241
242void socfpga_get_managers_addr(void)
243{
244 int ret;
245
246 ret = socfpga_get_base_addr("altr,rst-mgr", &socfpga_rstmgr_base);
247 if (ret)
248 hang();
Ley Foon Tan3d3a8602019-11-08 10:38:20 +0800249
250 ret = socfpga_get_base_addr("altr,sys-mgr", &socfpga_sysmgr_base);
251 if (ret)
252 hang();
Ley Foon Tan26695912019-11-08 10:38:21 +0800253
Ley Foon Tanef5458f2019-11-27 15:55:22 +0800254#ifdef CONFIG_TARGET_SOCFPGA_AGILEX
255 ret = socfpga_get_base_addr("intel,agilex-clkmgr",
256 &socfpga_clkmgr_base);
Siew Chin Limc16c7ec2021-08-10 11:26:31 +0800257#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
258 ret = socfpga_get_base_addr("intel,n5x-clkmgr",
259 &socfpga_clkmgr_base);
Ley Foon Tanef5458f2019-11-27 15:55:22 +0800260#else
Ley Foon Tan26695912019-11-08 10:38:21 +0800261 ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
Ley Foon Tanef5458f2019-11-27 15:55:22 +0800262#endif
Ley Foon Tan26695912019-11-08 10:38:21 +0800263 if (ret)
264 hang();
Ley Foon Tanfed4c952019-11-08 10:38:19 +0800265}
266
267phys_addr_t socfpga_get_rstmgr_addr(void)
268{
269 return socfpga_rstmgr_base;
270}
Ley Foon Tan3d3a8602019-11-08 10:38:20 +0800271
272phys_addr_t socfpga_get_sysmgr_addr(void)
273{
274 return socfpga_sysmgr_base;
275}
Ley Foon Tan26695912019-11-08 10:38:21 +0800276
277phys_addr_t socfpga_get_clkmgr_addr(void)
278{
279 return socfpga_clkmgr_base;
280}