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Jernej Skrabece52dc3e2021-01-11 21:11:52 +01001// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2021 Jernej Skrabec <jernej.skrabec@siol.net>
4 */
5
Jernej Skrabece52dc3e2021-01-11 21:11:52 +01006#include <clk-uclass.h>
7#include <dm.h>
8#include <errno.h>
Samuel Holland12e3faa2021-09-12 11:48:43 -05009#include <clk/sunxi.h>
Jernej Skrabece52dc3e2021-01-11 21:11:52 +010010#include <dt-bindings/clock/sun50i-h616-ccu.h>
11#include <dt-bindings/reset/sun50i-h616-ccu.h>
12#include <linux/bitops.h>
13
14static struct ccu_clk_gate h616_gates[] = {
Andre Przywara3e9aa0b2022-05-04 22:10:28 +010015 [CLK_PLL_PERIPH0] = GATE(0x020, BIT(31) | BIT(27)),
16
Andre Przywara2d1864f2022-05-05 01:25:43 +010017 [CLK_APB1] = GATE_DUMMY,
18
Samuel Holland1467d442022-11-28 01:02:24 -060019 [CLK_DE] = GATE(0x600, BIT(31)),
20 [CLK_BUS_DE] = GATE(0x60c, BIT(0)),
21
Samuel Hollanda0f27ba2023-01-22 16:06:31 -060022 [CLK_NAND0] = GATE(0x810, BIT(31)),
23 [CLK_NAND1] = GATE(0x814, BIT(31)),
24 [CLK_BUS_NAND] = GATE(0x82c, BIT(0)),
25
Jernej Skrabece52dc3e2021-01-11 21:11:52 +010026 [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
27 [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
28 [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
29
30 [CLK_BUS_UART0] = GATE(0x90c, BIT(0)),
31 [CLK_BUS_UART1] = GATE(0x90c, BIT(1)),
32 [CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
33 [CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
34 [CLK_BUS_UART4] = GATE(0x90c, BIT(4)),
35 [CLK_BUS_UART5] = GATE(0x90c, BIT(5)),
36
Samuel Hollandfa7a7fa2021-09-12 09:47:24 -050037 [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)),
38 [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)),
39 [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)),
40 [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)),
41 [CLK_BUS_I2C4] = GATE(0x91c, BIT(4)),
42
Jernej Skrabece52dc3e2021-01-11 21:11:52 +010043 [CLK_SPI0] = GATE(0x940, BIT(31)),
44 [CLK_SPI1] = GATE(0x944, BIT(31)),
45
46 [CLK_BUS_SPI0] = GATE(0x96c, BIT(0)),
47 [CLK_BUS_SPI1] = GATE(0x96c, BIT(1)),
48
49 [CLK_BUS_EMAC0] = GATE(0x97c, BIT(0)),
50 [CLK_BUS_EMAC1] = GATE(0x97c, BIT(1)),
51
52 [CLK_USB_PHY0] = GATE(0xa70, BIT(29)),
53 [CLK_USB_OHCI0] = GATE(0xa70, BIT(31)),
54
55 [CLK_USB_PHY1] = GATE(0xa74, BIT(29)),
56 [CLK_USB_OHCI1] = GATE(0xa74, BIT(31)),
57
58 [CLK_USB_PHY2] = GATE(0xa78, BIT(29)),
59 [CLK_USB_OHCI2] = GATE(0xa78, BIT(31)),
60
61 [CLK_USB_PHY3] = GATE(0xa7c, BIT(29)),
62 [CLK_USB_OHCI3] = GATE(0xa7c, BIT(31)),
63
64 [CLK_BUS_OHCI0] = GATE(0xa8c, BIT(0)),
65 [CLK_BUS_OHCI1] = GATE(0xa8c, BIT(1)),
66 [CLK_BUS_OHCI2] = GATE(0xa8c, BIT(2)),
67 [CLK_BUS_OHCI3] = GATE(0xa8c, BIT(3)),
68 [CLK_BUS_EHCI0] = GATE(0xa8c, BIT(4)),
69 [CLK_BUS_EHCI1] = GATE(0xa8c, BIT(5)),
70 [CLK_BUS_EHCI2] = GATE(0xa8c, BIT(6)),
71 [CLK_BUS_EHCI3] = GATE(0xa8c, BIT(7)),
72 [CLK_BUS_OTG] = GATE(0xa8c, BIT(8)),
Samuel Holland1467d442022-11-28 01:02:24 -060073
74 [CLK_HDMI] = GATE(0xb00, BIT(31)),
75 [CLK_HDMI_SLOW] = GATE(0xb04, BIT(31)),
76 [CLK_HDMI_CEC] = GATE(0xb10, BIT(31)),
77 [CLK_BUS_HDMI] = GATE(0xb1c, BIT(0)),
78 [CLK_BUS_TCON_TOP] = GATE(0xb5c, BIT(0)),
79 [CLK_TCON_TV0] = GATE(0xb80, BIT(31)),
80 [CLK_TCON_TV1] = GATE(0xb84, BIT(31)),
81 [CLK_BUS_TCON_TV0] = GATE(0xb9c, BIT(0)),
82 [CLK_BUS_TCON_TV1] = GATE(0xb9c, BIT(1)),
Jernej Skrabece52dc3e2021-01-11 21:11:52 +010083};
84
85static struct ccu_reset h616_resets[] = {
Samuel Holland1467d442022-11-28 01:02:24 -060086 [RST_BUS_DE] = RESET(0x60c, BIT(16)),
Samuel Hollanda0f27ba2023-01-22 16:06:31 -060087 [RST_BUS_NAND] = RESET(0x82c, BIT(16)),
Samuel Holland1467d442022-11-28 01:02:24 -060088
Jernej Skrabece52dc3e2021-01-11 21:11:52 +010089 [RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
90 [RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
91 [RST_BUS_MMC2] = RESET(0x84c, BIT(18)),
92
93 [RST_BUS_UART0] = RESET(0x90c, BIT(16)),
94 [RST_BUS_UART1] = RESET(0x90c, BIT(17)),
95 [RST_BUS_UART2] = RESET(0x90c, BIT(18)),
96 [RST_BUS_UART3] = RESET(0x90c, BIT(19)),
97 [RST_BUS_UART4] = RESET(0x90c, BIT(20)),
98 [RST_BUS_UART5] = RESET(0x90c, BIT(21)),
99
Samuel Hollandfa7a7fa2021-09-12 09:47:24 -0500100 [RST_BUS_I2C0] = RESET(0x91c, BIT(16)),
101 [RST_BUS_I2C1] = RESET(0x91c, BIT(17)),
102 [RST_BUS_I2C2] = RESET(0x91c, BIT(18)),
103 [RST_BUS_I2C3] = RESET(0x91c, BIT(19)),
104 [RST_BUS_I2C4] = RESET(0x91c, BIT(20)),
105
Jernej Skrabece52dc3e2021-01-11 21:11:52 +0100106 [RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
107 [RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
108
109 [RST_BUS_EMAC0] = RESET(0x97c, BIT(16)),
110 [RST_BUS_EMAC1] = RESET(0x97c, BIT(17)),
111
112 [RST_USB_PHY0] = RESET(0xa70, BIT(30)),
113
114 [RST_USB_PHY1] = RESET(0xa74, BIT(30)),
115
116 [RST_USB_PHY2] = RESET(0xa78, BIT(30)),
117
118 [RST_USB_PHY3] = RESET(0xa7c, BIT(30)),
119
120 [RST_BUS_OHCI0] = RESET(0xa8c, BIT(16)),
121 [RST_BUS_OHCI1] = RESET(0xa8c, BIT(17)),
122 [RST_BUS_OHCI2] = RESET(0xa8c, BIT(18)),
123 [RST_BUS_OHCI3] = RESET(0xa8c, BIT(19)),
124 [RST_BUS_EHCI0] = RESET(0xa8c, BIT(20)),
125 [RST_BUS_EHCI1] = RESET(0xa8c, BIT(21)),
126 [RST_BUS_EHCI2] = RESET(0xa8c, BIT(22)),
127 [RST_BUS_EHCI3] = RESET(0xa8c, BIT(23)),
128 [RST_BUS_OTG] = RESET(0xa8c, BIT(24)),
Samuel Holland1467d442022-11-28 01:02:24 -0600129
130 [RST_BUS_HDMI] = RESET(0xb1c, BIT(16)),
131 [RST_BUS_HDMI_SUB] = RESET(0xb1c, BIT(17)),
132 [RST_BUS_TCON_TOP] = RESET(0xb5c, BIT(16)),
133 [RST_BUS_TCON_TV0] = RESET(0xb9c, BIT(16)),
134 [RST_BUS_TCON_TV1] = RESET(0xb9c, BIT(17)),
Jernej Skrabece52dc3e2021-01-11 21:11:52 +0100135};
136
Samuel Holland751c6c62022-05-09 00:29:34 -0500137const struct ccu_desc h616_ccu_desc = {
Jernej Skrabece52dc3e2021-01-11 21:11:52 +0100138 .gates = h616_gates,
139 .resets = h616_resets,
Samuel Holland84436502022-05-09 00:29:31 -0500140 .num_gates = ARRAY_SIZE(h616_gates),
141 .num_resets = ARRAY_SIZE(h616_resets),
Jernej Skrabece52dc3e2021-01-11 21:11:52 +0100142};