clk: sunxi: Add DE2 display-related clocks/resets
Add clock/reset definitions for display-related peripherals, including
the display engine, TCONs, and DSI and HDMI encoders, so those drivers
can be converted to DM clock consumers instead of directly manipulating
the CCU registers.
Signed-off-by: Samuel Holland <samuel@sholland.org>
diff --git a/drivers/clk/sunxi/clk_h616.c b/drivers/clk/sunxi/clk_h616.c
index 964636d..88d6bf3 100644
--- a/drivers/clk/sunxi/clk_h616.c
+++ b/drivers/clk/sunxi/clk_h616.c
@@ -17,6 +17,9 @@
[CLK_APB1] = GATE_DUMMY,
+ [CLK_DE] = GATE(0x600, BIT(31)),
+ [CLK_BUS_DE] = GATE(0x60c, BIT(0)),
+
[CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
[CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
[CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
@@ -64,9 +67,21 @@
[CLK_BUS_EHCI2] = GATE(0xa8c, BIT(6)),
[CLK_BUS_EHCI3] = GATE(0xa8c, BIT(7)),
[CLK_BUS_OTG] = GATE(0xa8c, BIT(8)),
+
+ [CLK_HDMI] = GATE(0xb00, BIT(31)),
+ [CLK_HDMI_SLOW] = GATE(0xb04, BIT(31)),
+ [CLK_HDMI_CEC] = GATE(0xb10, BIT(31)),
+ [CLK_BUS_HDMI] = GATE(0xb1c, BIT(0)),
+ [CLK_BUS_TCON_TOP] = GATE(0xb5c, BIT(0)),
+ [CLK_TCON_TV0] = GATE(0xb80, BIT(31)),
+ [CLK_TCON_TV1] = GATE(0xb84, BIT(31)),
+ [CLK_BUS_TCON_TV0] = GATE(0xb9c, BIT(0)),
+ [CLK_BUS_TCON_TV1] = GATE(0xb9c, BIT(1)),
};
static struct ccu_reset h616_resets[] = {
+ [RST_BUS_DE] = RESET(0x60c, BIT(16)),
+
[RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
[RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
[RST_BUS_MMC2] = RESET(0x84c, BIT(18)),
@@ -107,6 +122,12 @@
[RST_BUS_EHCI2] = RESET(0xa8c, BIT(22)),
[RST_BUS_EHCI3] = RESET(0xa8c, BIT(23)),
[RST_BUS_OTG] = RESET(0xa8c, BIT(24)),
+
+ [RST_BUS_HDMI] = RESET(0xb1c, BIT(16)),
+ [RST_BUS_HDMI_SUB] = RESET(0xb1c, BIT(17)),
+ [RST_BUS_TCON_TOP] = RESET(0xb5c, BIT(16)),
+ [RST_BUS_TCON_TV0] = RESET(0xb9c, BIT(16)),
+ [RST_BUS_TCON_TV1] = RESET(0xb9c, BIT(17)),
};
const struct ccu_desc h616_ccu_desc = {