Blame - arch/arm/mach-stm32mp/Kconfig - filogic/uboot

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Patrick Delaunay	85b5397	2018-03-12 10:46:10 +0100	[diff] [blame]	1	if ARCH_STM32MP
				2
				3	config SPL
Patrick Delaunay	4c5821d	2020-07-24 11:13:31 +0200	[diff] [blame]	4	select SPL_BOARD_INIT
Patrick Delaunay	85b5397	2018-03-12 10:46:10 +0100	[diff] [blame]	5	select SPL_CLK
				6	select SPL_DM
				7	select SPL_DM_SEQ_ALIAS
Simon Glass	284cb9c	2021-07-10 21:14:31 -0600	[diff] [blame]	8	select SPL_DRIVERS_MISC
Patrick Delaunay	85b5397	2018-03-12 10:46:10 +0100	[diff] [blame]	9	select SPL_FRAMEWORK
Simon Glass	035939e	2021-07-10 21:14:30 -0600	[diff] [blame]	10	select SPL_GPIO
Patrick Delaunay	85b5397	2018-03-12 10:46:10 +0100	[diff] [blame]	11	select SPL_LIBCOMMON_SUPPORT
				12	select SPL_LIBGENERIC_SUPPORT
				13	select SPL_OF_CONTROL
				14	select SPL_OF_TRANSLATE
				15	select SPL_PINCTRL
				16	select SPL_REGMAP
Ley Foon Tan	9caf712	2018-06-14 18:45:19 +0800	[diff] [blame]	17	select SPL_DM_RESET
Simon Glass	f4d6039	2021-08-08 12:20:12 -0600	[diff] [blame]	18	select SPL_SERIAL
Patrick Delaunay	85b5397	2018-03-12 10:46:10 +0100	[diff] [blame]	19	select SPL_SYSCON
Simon Glass	1ba1d4e	2021-07-10 21:14:28 -0600	[diff] [blame]	20	select SPL_WATCHDOG if WATCHDOG
Patrick Delaunay	f860020	2019-04-18 17:32:47 +0200	[diff] [blame]	21	imply BOOTSTAGE_STASH if SPL_BOOTSTAGE
				22	imply SPL_BOOTSTAGE if BOOTSTAGE
Patrick Delaunay	aa4e685	2019-02-27 17:01:14 +0100	[diff] [blame]	23	imply SPL_DISPLAY_PRINT
Patrick Delaunay	85b5397	2018-03-12 10:46:10 +0100	[diff] [blame]	24	imply SPL_LIBDISK_SUPPORT
Simon Glass	a582047	2021-08-08 12:20:14 -0600	[diff] [blame]	25	imply SPL_SPI_LOAD if SPL_SPI
Patrick Delaunay	85b5397	2018-03-12 10:46:10 +0100	[diff] [blame]	26
				27	config SYS_SOC
				28	default "stm32mp"
				29
Patrick Delaunay	7e517c6	2019-04-18 17:32:36 +0200	[diff] [blame]	30	config SYS_MALLOC_LEN
				31	default 0x2000000
				32
Patrick Delaunay	088b676	2019-04-18 17:32:37 +0200	[diff] [blame]	33	config ENV_SIZE
Patrice Chotard	d83bba4	2019-05-07 18:40:47 +0200	[diff] [blame]	34	default 0x2000
Patrick Delaunay	088b676	2019-04-18 17:32:37 +0200	[diff] [blame]	35
Patrick Delaunay	55cf477	2022-05-20 18:24:43 +0200	[diff] [blame]	36	choice
				37	prompt "Select STMicroelectronics STM32MPxxx Soc"
Patrick Delaunay	4c6fcbc	2024-01-15 15:05:57 +0100	[diff] [blame]	38	default STM32MP15X
Patrick Delaunay	55cf477	2022-05-20 18:24:43 +0200	[diff] [blame]	39
Patrick Delaunay	990e057	2024-01-15 15:05:56 +0100	[diff] [blame]	40	config STM32MP13X
Patrick Delaunay	123687c	2022-05-20 18:24:46 +0200	[diff] [blame]	41	bool "Support STMicroelectronics STM32MP13x Soc"
				42	select ARM_SMCCC
				43	select CPU_V7A
				44	select CPU_V7_HAS_NONSEC
				45	select CPU_V7_HAS_VIRT
				46	select OF_BOARD
				47	select OF_BOARD_SETUP
				48	select PINCTRL_STM32
				49	select STM32_RCC
				50	select STM32_RESET
				51	select STM32_SERIAL
				52	select SYS_ARCH_TIMER
				53	imply CMD_NVEDIT_INFO
				54	help
				55	support of STMicroelectronics SOC STM32MP13x family
				56	STMicroelectronics MPU with core ARMv7
				57
Patrick Delaunay	4c6fcbc	2024-01-15 15:05:57 +0100	[diff] [blame]	58	config STM32MP15X
Patrick Delaunay	310aa8a	2020-01-13 15:17:42 +0100	[diff] [blame]	59	bool "Support STMicroelectronics STM32MP15x Soc"
Patrick Delaunay	196b7db	2021-10-11 09:52:49 +0200	[diff] [blame]	60	select ARCH_SUPPORT_PSCI
Patrick Delaunay	1e2a9b7	2021-10-13 15:11:18 +0200	[diff] [blame]	61	select BINMAN
Lokesh Vutla	81b1a67	2018-04-26 18:21:26 +0530	[diff] [blame]	62	select CPU_V7A
Patrick Delaunay	196b7db	2021-10-11 09:52:49 +0200	[diff] [blame]	63	select CPU_V7_HAS_NONSEC
Patrick Delaunay	e020737	2018-04-16 10:13:24 +0200	[diff] [blame]	64	select CPU_V7_HAS_VIRT
Patrice Chotard	df29081	2022-01-20 08:19:15 +0100	[diff] [blame]	65	select OF_BOARD if TFABOOT
Patrick Delaunay	de98cbf	2019-07-02 13:26:07 +0200	[diff] [blame]	66	select OF_BOARD_SETUP
Patrick Delaunay	85b5397	2018-03-12 10:46:10 +0100	[diff] [blame]	67	select PINCTRL_STM32
Patrick Delaunay	b139a5b	2018-07-09 15:17:20 +0200	[diff] [blame]	68	select STM32_RCC
Patrick Delaunay	85b5397	2018-03-12 10:46:10 +0100	[diff] [blame]	69	select STM32_RESET
Patrick Delaunay	4368e56	2019-07-30 19:16:25 +0200	[diff] [blame]	70	select STM32_SERIAL
Patrick Delaunay	efd00f3	2022-05-20 18:24:40 +0200	[diff] [blame]	71	select SUPPORT_SPL
Andre Przywara	7b16925	2018-04-12 04:24:46 +0300	[diff] [blame]	72	select SYS_ARCH_TIMER
Patrick Delaunay	59d0da1	2020-07-02 17:43:45 +0200	[diff] [blame]	73	imply CMD_NVEDIT_INFO
Patrick Delaunay	310aa8a	2020-01-13 15:17:42 +0100	[diff] [blame]	74	help
				75	support of STMicroelectronics SOC STM32MP15x family
				76	STM32MP157, STM32MP153 or STM32MP151
				77	STMicroelectronics MPU with core ARMv7
				78	dual core A7 for STM32MP157/3, monocore for STM32MP151
Patrice Chotard	d29531c	2023-10-27 16:43:04 +0200	[diff] [blame]	79
				80	config STM32MP25X
				81	bool "Support STMicroelectronics STM32MP25x Soc"
				82	select ARM64
				83	select CLK_STM32MP25
				84	select OF_BOARD
				85	select PINCTRL_STM32
				86	select STM32_RCC
				87	select STM32_RESET
				88	select STM32_SERIAL
				89	select SYS_ARCH_TIMER
				90	select TFABOOT
				91	imply CLK_SCMI
				92	imply CMD_NVEDIT_INFO
				93	imply DM_REGULATOR
				94	imply DM_REGULATOR_SCMI
				95	imply OPTEE
				96	imply RESET_SCMI
				97	imply SYSRESET_PSCI
				98	imply TEE
				99	imply VERSION_VARIABLE
				100	help
				101	Support of STMicroelectronics SOC STM32MP25x family
				102	STMicroelectronics MPU with 2 * A53 core and 1 M33 core
Patrick Delaunay	55cf477	2022-05-20 18:24:43 +0200	[diff] [blame]	103	endchoice
				104
Patrick Delaunay	6d3cbf3	2019-02-27 17:01:15 +0100	[diff] [blame]	105	config NR_DRAM_BANKS
				106	default 1
				107
Patrick Delaunay	ab7d644	2020-09-04 12:55:19 +0200	[diff] [blame]	108	config DDR_CACHEABLE_SIZE
				109	hex "Size of the DDR marked cacheable in pre-reloc stage"
Patrick Delaunay	ab7d644	2020-09-04 12:55:19 +0200	[diff] [blame]	110	default 0x40000000
				111	help
				112	Define the size of the DDR marked as cacheable in U-Boot
				113	pre-reloc stage.
				114	This option can be useful to avoid speculatif access
				115	to secured area of DDR used by TF-A or OP-TEE before U-Boot
				116	initialization.
				117	The areas marked "no-map" in device tree should be located
				118	before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE.
				119
Patrick Delaunay	fc69c68	2018-03-20 10:54:54 +0100	[diff] [blame]	120	config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2
				121	hex "Partition on MMC2 to use to load U-Boot from"
				122	depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
				123	default 1
				124	help
				125	Partition on the second MMC to load U-Boot from when the MMC is being
				126	used in raw mode
				127
Patrick Delaunay	43f214c	2019-07-05 17:20:15 +0200	[diff] [blame]	128	config STM32_ETZPC
				129	bool "STM32 Extended TrustZone Protection"
Patrick Delaunay	4c6fcbc	2024-01-15 15:05:57 +0100	[diff] [blame]	130	depends on STM32MP15X \|\| STM32MP13X
Patrick Delaunay	43f214c	2019-07-05 17:20:15 +0200	[diff] [blame]	131	default y
Simon Glass	1c38374	2021-12-18 11:27:51 -0700	[diff] [blame]	132	imply BOOTP_SERVERIP
Patrick Delaunay	43f214c	2019-07-05 17:20:15 +0200	[diff] [blame]	133	help
				134	Say y to enable STM32 Extended TrustZone Protection
				135
Alexandru Gagniuc	31aa697	2021-07-29 11:47:17 -0500	[diff] [blame]	136	config STM32_ECDSA_VERIFY
				137	bool "STM32 ECDSA verification via the ROM API"
				138	depends on SPL_ECDSA_VERIFY
				139	default y
				140	help
				141	Say y to enable the uclass driver for ECDSA verification using the
				142	ROM API provided on STM32MP.
				143	The ROM API is only available during SPL for now.
				144
Patrick Delaunay	109d13f	2019-07-05 17:20:17 +0200	[diff] [blame]	145	config CMD_STM32KEY
				146	bool "command stm32key to fuse public key hash"
Patrick Delaunay	c4e1879	2024-01-15 14:30:54 +0100	[diff] [blame]	147	depends on CMDLINE
Patrick Delaunay	109d13f	2019-07-05 17:20:17 +0200	[diff] [blame]	148	help
				149	fuse public key hash in corresponding fuse used to authenticate
				150	binary.
Patrick Delaunay	d6c098a	2021-06-28 14:55:57 +0200	[diff] [blame]	151	This command is used to evaluate the secure boot on stm32mp SOC,
				152	it is deactivated by default in real products.
Patrick Delaunay	109d13f	2019-07-05 17:20:17 +0200	[diff] [blame]	153
Patrick Delaunay	123687c	2022-05-20 18:24:46 +0200	[diff] [blame]	154	source "arch/arm/mach-stm32mp/Kconfig.13x"
Patrick Delaunay	ff45fca	2022-05-20 18:24:44 +0200	[diff] [blame]	155	source "arch/arm/mach-stm32mp/Kconfig.15x"
Patrice Chotard	d29531c	2023-10-27 16:43:04 +0200	[diff] [blame]	156	source "arch/arm/mach-stm32mp/Kconfig.25x"
Patrick Delaunay	0440d86	2021-02-25 13:37:00 +0100	[diff] [blame]	157	source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig"
Marek Vasut	86a02ee	2024-03-19 03:45:08 +0100	[diff] [blame]	158
				159	config STM32MP15_PWR
				160	bool "Enable driver for STM32MP15x PWR"
				161	depends on DM_REGULATOR && DM_PMIC && (STM32MP13X \|\| STM32MP15X)
				162	default y if STM32MP15X
				163	help
				164	This config enables implementation of driver-model pmic and
				165	regulator uclass features for access to STM32MP15x PWR.
				166
				167	config SPL_STM32MP15_PWR
				168	bool "Enable driver for STM32MP15x PWR in SPL"
				169	depends on SPL && SPL_DM_REGULATOR && SPL_DM_PMIC && (STM32MP13X \|\| STM32MP15X)
				170	default y if STM32MP15X
				171	help
				172	This config enables implementation of driver-model pmic and
				173	regulator uclass features for access to STM32MP15x PWR in SPL.
				174
Patrick Delaunay	85b5397	2018-03-12 10:46:10 +0100	[diff] [blame]	175	endif