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git01.mediatek.com / filogic / uboot / 41377856ecdbd27d50252b65b9acd194d89d7240 / . / board / gateworks / gw_ventana / common.h
blob: 480c6675d7b0ed78f6fa6e19eeb5cd4025ed7e13 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Tim Harvey0cee2242015-05-08 18:28:35 -0700[diff] [blame]2/*
3 * Copyright (C) 2013 Gateworks Corporation
4 *
5 * Author: Tim Harvey <tharvey@gateworks.com>
Tim Harvey0cee2242015-05-08 18:28:35 -0700[diff] [blame]6 */
7
8#ifndef _GWVENTANA_COMMON_H_
9#define _GWVENTANA_COMMON_H_
10
Tim Harvey41377852022-04-13 09:29:16 -0700[diff] [blame^]11#include "eeprom.h"
Tim Harvey0cee2242015-05-08 18:28:35 -0700[diff] [blame]12
13/* GPIO's common to all baseboards */
Tim Harvey0cee2242015-05-08 18:28:35 -0700[diff] [blame]14#define GP_RS232_EN IMX_GPIO_NR(2, 11)
15#define GP_MSATA_SEL IMX_GPIO_NR(2, 8)
16
17#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
18 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
19 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
20
21#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
22 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
23 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
24
25#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
26 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
27 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
28
29#define SPI_PAD_CTRL (PAD_CTL_HYS | \
30 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
31 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
32
Tim Harvey0cee2242015-05-08 18:28:35 -0700[diff] [blame]33#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
34 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
35 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
36
37#define IRQ_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
38 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
39 PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
40
Tim Harveydb7edfa2015-05-26 11:04:54 -0700[diff] [blame]41#define DIO_PAD_CFG (MUX_PAD_CTRL(IRQ_PAD_CTRL) | MUX_MODE_SION)
Tim Harvey0cee2242015-05-08 18:28:35 -0700[diff] [blame]42
43#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
44
45/*
Tim Harvey41595b52016-07-15 07:14:23 -0700[diff] [blame]46 * each baseboard has an optional set user configurable Digital IO lines which
47 * can be pinmuxed as a GPIO or in some cases a PWM
Tim Harvey0cee2242015-05-08 18:28:35 -0700[diff] [blame]48 */
49struct dio_cfg {
50 iomux_v3_cfg_t gpio_padmux[2];
51 unsigned gpio_param;
52 iomux_v3_cfg_t pwm_padmux[2];
53 unsigned pwm_param;
54};
55
56struct ventana {
57 /* pinmux */
58 iomux_v3_cfg_t const *gpio_pads;
59 int num_pads;
60 /* DIO pinmux/val */
Tim Harvey41595b52016-07-15 07:14:23 -0700[diff] [blame]61 struct dio_cfg *dio_cfg;
62 int dio_num;
Tim Harvey0cee2242015-05-08 18:28:35 -0700[diff] [blame]63 /* various gpios (0 if non-existent) */
Tim Harvey0cee2242015-05-08 18:28:35 -0700[diff] [blame]64 int mezz_pwren;
65 int mezz_irq;
66 int rs485en;
67 int gps_shdn;
Tim Harvey0cee2242015-05-08 18:28:35 -0700[diff] [blame]68 int dioi2c_en;
69 int pcie_sson;
70 int usb_sel;
71 int wdis;
Tim Harvey86b75322016-05-24 11:03:56 -0700[diff] [blame]72 int msata_en;
Tim Harvey2cb61c12016-07-15 07:14:22 -0700[diff] [blame]73 int rs232_en;
Tim Harveyd7babd42017-03-13 08:51:08 -0700[diff] [blame]74 int vsel_pin;
Tim Harvey63537792017-03-17 07:30:38 -0700[diff] [blame]75 int mmc_cd;
Tim Harvey2cb61c12016-07-15 07:14:22 -0700[diff] [blame]76 /* various features */
Tim Harvey147b5762016-05-24 11:03:59 -0700[diff] [blame]77 bool usd_vsel;
Tim Harvey0cee2242015-05-08 18:28:35 -0700[diff] [blame]78};
79
80extern struct ventana gpio_cfg[GW_UNKNOWN];
81
Tim Harvey0cee2242015-05-08 18:28:35 -0700[diff] [blame]82/* configure gpio iomux/defaults */
Tim Harvey41377852022-04-13 09:29:16 -0700[diff] [blame^]83void setup_iomux_gpio(int board);
Tim Harvey0cee2242015-05-08 18:28:35 -0700[diff] [blame]84
85#endif /* #ifndef _GWVENTANA_COMMON_H_ */