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git01.mediatek.com / filogic / uboot / 6353779326b0cd2862225e5ad5a6f6eb3adda748 / . / board / gateworks / gw_ventana / common.h
blob: 3eb4c59400255fea89dcb2060ef96794e0ebc827 [file] [log] [blame]
Tim Harvey0cee2242015-05-08 18:28:35 -0700[diff] [blame]1/*
2 * Copyright (C) 2013 Gateworks Corporation
3 *
4 * Author: Tim Harvey <tharvey@gateworks.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef _GWVENTANA_COMMON_H_
10#define _GWVENTANA_COMMON_H_
11
12#include "ventana_eeprom.h"
13
14/* GPIO's common to all baseboards */
15#define GP_PHY_RST IMX_GPIO_NR(1, 30)
Tim Harvey0cee2242015-05-08 18:28:35 -0700[diff] [blame]16#define GP_RS232_EN IMX_GPIO_NR(2, 11)
17#define GP_MSATA_SEL IMX_GPIO_NR(2, 8)
18
19#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
20 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
21 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
22
23#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
24 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
25 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
26
27#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
28 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
29 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
30
31#define SPI_PAD_CTRL (PAD_CTL_HYS | \
32 PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
33 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
34
Tim Harvey0cee2242015-05-08 18:28:35 -0700[diff] [blame]35#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
36 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
37 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
38
39#define IRQ_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
40 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
41 PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
42
Tim Harveydb7edfa2015-05-26 11:04:54 -0700[diff] [blame]43#define DIO_PAD_CFG (MUX_PAD_CTRL(IRQ_PAD_CTRL) | MUX_MODE_SION)
Tim Harvey0cee2242015-05-08 18:28:35 -0700[diff] [blame]44
45#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
46
47/*
Tim Harvey41595b52016-07-15 07:14:23 -0700[diff] [blame]48 * each baseboard has an optional set user configurable Digital IO lines which
49 * can be pinmuxed as a GPIO or in some cases a PWM
Tim Harvey0cee2242015-05-08 18:28:35 -0700[diff] [blame]50 */
51struct dio_cfg {
52 iomux_v3_cfg_t gpio_padmux[2];
53 unsigned gpio_param;
54 iomux_v3_cfg_t pwm_padmux[2];
55 unsigned pwm_param;
56};
57
58struct ventana {
59 /* pinmux */
60 iomux_v3_cfg_t const *gpio_pads;
61 int num_pads;
62 /* DIO pinmux/val */
Tim Harvey41595b52016-07-15 07:14:23 -0700[diff] [blame]63 struct dio_cfg *dio_cfg;
64 int dio_num;
Tim Harvey0cee2242015-05-08 18:28:35 -0700[diff] [blame]65 /* various gpios (0 if non-existent) */
66 int leds[3];
67 int pcie_rst;
68 int mezz_pwren;
69 int mezz_irq;
70 int rs485en;
71 int gps_shdn;
72 int vidin_en;
73 int dioi2c_en;
74 int pcie_sson;
75 int usb_sel;
76 int wdis;
Tim Harvey86b75322016-05-24 11:03:56 -0700[diff] [blame]77 int msata_en;
Tim Harvey2cb61c12016-07-15 07:14:22 -0700[diff] [blame]78 int rs232_en;
Tim Harvey9b9e75f2017-03-13 08:51:07 -0700[diff] [blame]79 int otgpwr_en;
Tim Harveyd7babd42017-03-13 08:51:08 -0700[diff] [blame]80 int vsel_pin;
Tim Harvey63537792017-03-17 07:30:38 -0700[diff] [blame^]81 int mmc_cd;
Tim Harvey2cb61c12016-07-15 07:14:22 -0700[diff] [blame]82 /* various features */
Tim Harvey147b5762016-05-24 11:03:59 -0700[diff] [blame]83 bool usd_vsel;
Tim Harvey0cee2242015-05-08 18:28:35 -0700[diff] [blame]84};
85
86extern struct ventana gpio_cfg[GW_UNKNOWN];
87
88/* configure i2c iomux */
89void setup_ventana_i2c(void);
90/* configure uart iomux */
91void setup_iomux_uart(void);
92/* conifgure PMIC */
Tim Harvey195bc972015-05-08 18:28:37 -0700[diff] [blame]93void setup_pmic(void);
Tim Harvey0cee2242015-05-08 18:28:35 -0700[diff] [blame]94/* configure gpio iomux/defaults */
95void setup_iomux_gpio(int board, struct ventana_board_info *);
96/* late setup of GPIO (configuration per baseboard and env) */
97void setup_board_gpio(int board, struct ventana_board_info *);
98
99#endif /* #ifndef _GWVENTANA_COMMON_H_ */