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git01.mediatek.com / filogic / uboot / 39bf18d8fe1f83346555e1b241130e1fc35a01ec / . / arch / arm / include / asm / arch-fsl-layerscape / fsl_serdes.h
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Minghuan Lian0e3a2b92015-03-20 19:28:16 -0700[diff] [blame]1/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
Mingkai Hu0e58b512015-10-26 19:47:50 +0800[diff] [blame]7#ifndef __FSL_SERDES_H__
8#define __FSL_SERDES_H__
Minghuan Lian0e3a2b92015-03-20 19:28:16 -0700[diff] [blame]9
10#include <config.h>
11
Ashish Kumarb25faa22017-08-31 16:12:53 +0530[diff] [blame]12#ifdef CONFIG_FSL_LSCH3
Minghuan Lian0e3a2b92015-03-20 19:28:16 -0700[diff] [blame]13enum srds_prtcl {
Hou Zhiqiangb435ae92016-08-02 19:03:22 +0800[diff] [blame]14 /*
15 * Nobody will check whether the device 'NONE' has been configured,
16 * So use it to indicate if the serdes_prtcl_map has been initialized.
17 */
Minghuan Lian0e3a2b92015-03-20 19:28:16 -0700[diff] [blame]18 NONE = 0,
19 PCIE1,
20 PCIE2,
21 PCIE3,
22 PCIE4,
23 SATA1,
24 SATA2,
25 XAUI1,
26 XAUI2,
27 XFI1,
28 XFI2,
29 XFI3,
30 XFI4,
31 XFI5,
32 XFI6,
33 XFI7,
34 XFI8,
35 SGMII1,
36 SGMII2,
37 SGMII3,
38 SGMII4,
39 SGMII5,
40 SGMII6,
41 SGMII7,
42 SGMII8,
43 SGMII9,
44 SGMII10,
45 SGMII11,
46 SGMII12,
47 SGMII13,
48 SGMII14,
49 SGMII15,
50 SGMII16,
Prabhakar Kushwaha3c39c082017-02-15 20:40:00 +0530[diff] [blame]51 QSGMII_A,
52 QSGMII_B,
53 QSGMII_C,
54 QSGMII_D,
Minghuan Lian0e3a2b92015-03-20 19:28:16 -0700[diff] [blame]55 SERDES_PRCTL_COUNT
56};
57
58enum srds {
59 FSL_SRDS_1 = 0,
60 FSL_SRDS_2 = 1,
61};
Prabhakar Kushwaha1966d012016-06-03 18:41:27 +0530[diff] [blame]62#elif defined(CONFIG_FSL_LSCH2)
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800[diff] [blame]63enum srds_prtcl {
Hou Zhiqiangb435ae92016-08-02 19:03:22 +0800[diff] [blame]64 /*
65 * Nobody will check whether the device 'NONE' has been configured,
66 * So use it to indicate if the serdes_prtcl_map has been initialized.
67 */
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800[diff] [blame]68 NONE = 0,
69 PCIE1,
70 PCIE2,
71 PCIE3,
72 PCIE4,
73 SATA1,
74 SATA2,
75 SRIO1,
76 SRIO2,
77 SGMII_FM1_DTSEC1,
78 SGMII_FM1_DTSEC2,
79 SGMII_FM1_DTSEC3,
80 SGMII_FM1_DTSEC4,
81 SGMII_FM1_DTSEC5,
82 SGMII_FM1_DTSEC6,
83 SGMII_FM1_DTSEC9,
84 SGMII_FM1_DTSEC10,
85 SGMII_FM2_DTSEC1,
86 SGMII_FM2_DTSEC2,
87 SGMII_FM2_DTSEC3,
88 SGMII_FM2_DTSEC4,
89 SGMII_FM2_DTSEC5,
90 SGMII_FM2_DTSEC6,
91 SGMII_FM2_DTSEC9,
92 SGMII_FM2_DTSEC10,
93 SGMII_TSEC1,
94 SGMII_TSEC2,
95 SGMII_TSEC3,
96 SGMII_TSEC4,
97 XAUI_FM1,
98 XAUI_FM2,
99 AURORA,
100 CPRI1,
101 CPRI2,
102 CPRI3,
103 CPRI4,
104 CPRI5,
105 CPRI6,
106 CPRI7,
107 CPRI8,
108 XAUI_FM1_MAC9,
109 XAUI_FM1_MAC10,
110 XAUI_FM2_MAC9,
111 XAUI_FM2_MAC10,
112 HIGIG_FM1_MAC9,
113 HIGIG_FM1_MAC10,
114 HIGIG_FM2_MAC9,
115 HIGIG_FM2_MAC10,
116 QSGMII_FM1_A, /* A indicates MACs 1,2,5,6 */
117 QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */
118 QSGMII_FM2_A,
119 QSGMII_FM2_B,
120 XFI_FM1_MAC1,
121 XFI_FM1_MAC2,
122 XFI_FM1_MAC9,
123 XFI_FM1_MAC10,
124 XFI_FM2_MAC9,
125 XFI_FM2_MAC10,
126 INTERLAKEN,
127 QSGMII_SW1_A, /* Indicates ports on L2 Switch */
128 QSGMII_SW1_B,
129 SGMII_2500_FM1_DTSEC1,
130 SGMII_2500_FM1_DTSEC2,
131 SGMII_2500_FM1_DTSEC3,
132 SGMII_2500_FM1_DTSEC4,
133 SGMII_2500_FM1_DTSEC5,
134 SGMII_2500_FM1_DTSEC6,
135 SGMII_2500_FM1_DTSEC9,
136 SGMII_2500_FM1_DTSEC10,
137 SGMII_2500_FM2_DTSEC1,
138 SGMII_2500_FM2_DTSEC2,
139 SGMII_2500_FM2_DTSEC3,
140 SGMII_2500_FM2_DTSEC4,
141 SGMII_2500_FM2_DTSEC5,
142 SGMII_2500_FM2_DTSEC6,
143 SGMII_2500_FM2_DTSEC9,
144 SGMII_2500_FM2_DTSEC10,
Prabhakar Kushwahad169ebe2016-06-03 18:41:31 +0530[diff] [blame]145 TX_CLK,
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800[diff] [blame]146 SERDES_PRCTL_COUNT
147};
148
149enum srds {
150 FSL_SRDS_1 = 0,
Qianyu Gong2b5b7a92016-07-05 16:01:54 +0800[diff] [blame]151 FSL_SRDS_2 = 1,
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800[diff] [blame]152};
153
Mingkai Hu0e58b512015-10-26 19:47:50 +0800[diff] [blame]154#endif
Minghuan Lian0e3a2b92015-03-20 19:28:16 -0700[diff] [blame]155
156int is_serdes_configured(enum srds_prtcl device);
157void fsl_serdes_init(void);
Minghuan Lian0e3a2b92015-03-20 19:28:16 -0700[diff] [blame]158int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
159enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
160int is_serdes_prtcl_valid(int serdes, u32 prtcl);
Ashish Kumarb25faa22017-08-31 16:12:53 +0530[diff] [blame]161int serdes_get_number(int serdes, int cfg);
Ashish Kumarec455e22017-08-31 16:37:31 +0530[diff] [blame]162void fsl_rgmii_init(void);
Minghuan Lian0e3a2b92015-03-20 19:28:16 -0700[diff] [blame]163
Mingkai Hucd54c0f2016-07-05 16:01:55 +0800[diff] [blame]164#ifdef CONFIG_FSL_LSCH2
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800[diff] [blame]165const char *serdes_clock_to_string(u32 clock);
166int get_serdes_protocol(void);
Hou Zhiqiang4ad59992016-12-09 16:09:00 +0800[diff] [blame]167#ifdef CONFIG_SYS_HAS_SERDES
168/* Get the volt of SVDD in unit mV */
169int get_serdes_volt(void);
170/* Set the volt of SVDD in unit mV */
171int set_serdes_volt(int svdd);
172/* The target volt of SVDD in unit mV */
173int setup_serdes_volt(u32 svdd);
174#endif
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800[diff] [blame]175#endif
176
Mingkai Hu0e58b512015-10-26 19:47:50 +0800[diff] [blame]177#endif /* __FSL_SERDES_H__ */