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Minghuan Lian0e3a2b92015-03-20 19:28:16 -07001/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __FSL_SERDES_H
8#define __FSL_SERDES_H
9
10#include <config.h>
11
12#define SRDS_MAX_LANES 8
13
14enum srds_prtcl {
15 NONE = 0,
16 PCIE1,
17 PCIE2,
18 PCIE3,
19 PCIE4,
20 SATA1,
21 SATA2,
22 XAUI1,
23 XAUI2,
24 XFI1,
25 XFI2,
26 XFI3,
27 XFI4,
28 XFI5,
29 XFI6,
30 XFI7,
31 XFI8,
32 SGMII1,
33 SGMII2,
34 SGMII3,
35 SGMII4,
36 SGMII5,
37 SGMII6,
38 SGMII7,
39 SGMII8,
40 SGMII9,
41 SGMII10,
42 SGMII11,
43 SGMII12,
44 SGMII13,
45 SGMII14,
46 SGMII15,
47 SGMII16,
48 QSGMII_A, /* A indicates MACs 1-4 */
49 QSGMII_B, /* B indicates MACs 5-8 */
50 QSGMII_C, /* C indicates MACs 9-12 */
51 QSGMII_D, /* D indicates MACs 12-16 */
52 SERDES_PRCTL_COUNT
53};
54
55enum srds {
56 FSL_SRDS_1 = 0,
57 FSL_SRDS_2 = 1,
58};
59
60int is_serdes_configured(enum srds_prtcl device);
61void fsl_serdes_init(void);
62
63int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
64enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
65int is_serdes_prtcl_valid(int serdes, u32 prtcl);
66
67#endif /* __FSL_SERDES_H */