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git01.mediatek.com / filogic / uboot / d169ebe45a559d0068ec2d6a051a0c831e2cd166 / . / arch / arm / include / asm / arch-fsl-layerscape / fsl_serdes.h
blob: 487cba80803f64c9f520e7c15e08d65542c06abe [file] [log] [blame]
Minghuan Lian0e3a2b92015-03-20 19:28:16 -0700[diff] [blame]1/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
Mingkai Hu0e58b512015-10-26 19:47:50 +0800[diff] [blame]7#ifndef __FSL_SERDES_H__
8#define __FSL_SERDES_H__
Minghuan Lian0e3a2b92015-03-20 19:28:16 -0700[diff] [blame]9
10#include <config.h>
11
York Suncbe8e1c2016-04-04 11:41:26 -0700[diff] [blame]12#ifdef CONFIG_LS2080A
Minghuan Lian0e3a2b92015-03-20 19:28:16 -0700[diff] [blame]13enum srds_prtcl {
14 NONE = 0,
15 PCIE1,
16 PCIE2,
17 PCIE3,
18 PCIE4,
19 SATA1,
20 SATA2,
21 XAUI1,
22 XAUI2,
23 XFI1,
24 XFI2,
25 XFI3,
26 XFI4,
27 XFI5,
28 XFI6,
29 XFI7,
30 XFI8,
31 SGMII1,
32 SGMII2,
33 SGMII3,
34 SGMII4,
35 SGMII5,
36 SGMII6,
37 SGMII7,
38 SGMII8,
39 SGMII9,
40 SGMII10,
41 SGMII11,
42 SGMII12,
43 SGMII13,
44 SGMII14,
45 SGMII15,
46 SGMII16,
47 QSGMII_A, /* A indicates MACs 1-4 */
48 QSGMII_B, /* B indicates MACs 5-8 */
49 QSGMII_C, /* C indicates MACs 9-12 */
50 QSGMII_D, /* D indicates MACs 12-16 */
51 SERDES_PRCTL_COUNT
52};
53
54enum srds {
55 FSL_SRDS_1 = 0,
56 FSL_SRDS_2 = 1,
57};
Prabhakar Kushwaha1966d012016-06-03 18:41:27 +0530[diff] [blame]58#elif defined(CONFIG_FSL_LSCH2)
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800[diff] [blame]59enum srds_prtcl {
60 NONE = 0,
61 PCIE1,
62 PCIE2,
63 PCIE3,
64 PCIE4,
65 SATA1,
66 SATA2,
67 SRIO1,
68 SRIO2,
69 SGMII_FM1_DTSEC1,
70 SGMII_FM1_DTSEC2,
71 SGMII_FM1_DTSEC3,
72 SGMII_FM1_DTSEC4,
73 SGMII_FM1_DTSEC5,
74 SGMII_FM1_DTSEC6,
75 SGMII_FM1_DTSEC9,
76 SGMII_FM1_DTSEC10,
77 SGMII_FM2_DTSEC1,
78 SGMII_FM2_DTSEC2,
79 SGMII_FM2_DTSEC3,
80 SGMII_FM2_DTSEC4,
81 SGMII_FM2_DTSEC5,
82 SGMII_FM2_DTSEC6,
83 SGMII_FM2_DTSEC9,
84 SGMII_FM2_DTSEC10,
85 SGMII_TSEC1,
86 SGMII_TSEC2,
87 SGMII_TSEC3,
88 SGMII_TSEC4,
89 XAUI_FM1,
90 XAUI_FM2,
91 AURORA,
92 CPRI1,
93 CPRI2,
94 CPRI3,
95 CPRI4,
96 CPRI5,
97 CPRI6,
98 CPRI7,
99 CPRI8,
100 XAUI_FM1_MAC9,
101 XAUI_FM1_MAC10,
102 XAUI_FM2_MAC9,
103 XAUI_FM2_MAC10,
104 HIGIG_FM1_MAC9,
105 HIGIG_FM1_MAC10,
106 HIGIG_FM2_MAC9,
107 HIGIG_FM2_MAC10,
108 QSGMII_FM1_A, /* A indicates MACs 1,2,5,6 */
109 QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */
110 QSGMII_FM2_A,
111 QSGMII_FM2_B,
112 XFI_FM1_MAC1,
113 XFI_FM1_MAC2,
114 XFI_FM1_MAC9,
115 XFI_FM1_MAC10,
116 XFI_FM2_MAC9,
117 XFI_FM2_MAC10,
118 INTERLAKEN,
119 QSGMII_SW1_A, /* Indicates ports on L2 Switch */
120 QSGMII_SW1_B,
121 SGMII_2500_FM1_DTSEC1,
122 SGMII_2500_FM1_DTSEC2,
123 SGMII_2500_FM1_DTSEC3,
124 SGMII_2500_FM1_DTSEC4,
125 SGMII_2500_FM1_DTSEC5,
126 SGMII_2500_FM1_DTSEC6,
127 SGMII_2500_FM1_DTSEC9,
128 SGMII_2500_FM1_DTSEC10,
129 SGMII_2500_FM2_DTSEC1,
130 SGMII_2500_FM2_DTSEC2,
131 SGMII_2500_FM2_DTSEC3,
132 SGMII_2500_FM2_DTSEC4,
133 SGMII_2500_FM2_DTSEC5,
134 SGMII_2500_FM2_DTSEC6,
135 SGMII_2500_FM2_DTSEC9,
136 SGMII_2500_FM2_DTSEC10,
Prabhakar Kushwahad169ebe2016-06-03 18:41:31 +0530[diff] [blame^]137 TX_CLK,
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800[diff] [blame]138 SERDES_PRCTL_COUNT
139};
140
141enum srds {
142 FSL_SRDS_1 = 0,
143};
144
Mingkai Hu0e58b512015-10-26 19:47:50 +0800[diff] [blame]145#endif
Minghuan Lian0e3a2b92015-03-20 19:28:16 -0700[diff] [blame]146
147int is_serdes_configured(enum srds_prtcl device);
148void fsl_serdes_init(void);
Minghuan Lian0e3a2b92015-03-20 19:28:16 -0700[diff] [blame]149int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
150enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
151int is_serdes_prtcl_valid(int serdes, u32 prtcl);
152
Mingkai Hue4e93ea2015-10-26 19:47:51 +0800[diff] [blame]153#ifdef CONFIG_LS1043A
154const char *serdes_clock_to_string(u32 clock);
155int get_serdes_protocol(void);
156#endif
157
Mingkai Hu0e58b512015-10-26 19:47:50 +0800[diff] [blame]158#endif /* __FSL_SERDES_H__ */