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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
David Feng3b5458c2013-12-14 11:47:37 +08002/*
3 * Configuration for Versatile Express. Parts were derived from other ARM
4 * configurations.
David Feng3b5458c2013-12-14 11:47:37 +08005 */
6
Peter Hoyes32860372021-11-11 09:26:00 +00007#ifndef __VEXPRESS_AEMV8_H
8#define __VEXPRESS_AEMV8_H
David Feng3b5458c2013-12-14 11:47:37 +08009
Peter Hoyes16fff302021-11-11 09:26:01 +000010#include <linux/stringify.h>
11
David Feng3b5458c2013-12-14 11:47:37 +080012/* Link Definitions */
Peter Hoyes32860372021-11-11 09:26:00 +000013#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
Peter Hoyes32860372021-11-11 09:26:00 +000014#else
Darwin Rambod32d4112014-06-09 11:12:59 -070015/* ATF loads u-boot here for BASE_FVP model */
Darwin Rambod32d4112014-06-09 11:12:59 -070016#endif
David Feng3b5458c2013-12-14 11:47:37 +080017
David Feng3b5458c2013-12-14 11:47:37 +080018/* CS register bases for the original memory map. */
Peter Hoyes3ca0ea02022-03-04 16:30:18 +000019#ifdef CONFIG_TARGET_VEXPRESS64_BASER_FVP
20#define V2M_DRAM_BASE 0x00000000
21#define V2M_PA_BASE 0x80000000
22#else
Andre Przywara87de4b72022-03-04 16:30:16 +000023#define V2M_DRAM_BASE 0x80000000
Peter Hoyes32860372021-11-11 09:26:00 +000024#define V2M_PA_BASE 0x00000000
Peter Hoyes3ca0ea02022-03-04 16:30:18 +000025#endif
Peter Hoyes32860372021-11-11 09:26:00 +000026
27#define V2M_PA_CS0 (V2M_PA_BASE + 0x00000000)
28#define V2M_PA_CS1 (V2M_PA_BASE + 0x14000000)
29#define V2M_PA_CS2 (V2M_PA_BASE + 0x18000000)
30#define V2M_PA_CS3 (V2M_PA_BASE + 0x1c000000)
31#define V2M_PA_CS4 (V2M_PA_BASE + 0x0c000000)
32#define V2M_PA_CS5 (V2M_PA_BASE + 0x10000000)
David Feng3b5458c2013-12-14 11:47:37 +080033
34#define V2M_PERIPH_OFFSET(x) (x << 16)
35#define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
36#define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
37#define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
38
David Feng3b5458c2013-12-14 11:47:37 +080039/* Common peripherals relative to CS7. */
40#define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
41#define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
42#define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
43#define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
44
Linus Walleijc5822502015-01-23 14:41:10 +010045#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
46#define V2M_UART0 0x7ff80000
47#define V2M_UART1 0x7ff70000
48#else /* Not Juno */
David Feng3b5458c2013-12-14 11:47:37 +080049#define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
50#define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
51#define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
52#define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
Linus Walleijc5822502015-01-23 14:41:10 +010053#endif
David Feng3b5458c2013-12-14 11:47:37 +080054
55#define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
56
57#define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
58#define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))
59
60#define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
61#define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))
62
63#define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))
64
65#define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))
66
67/* System register offsets. */
68#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
69#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
70#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
71
David Feng3b5458c2013-12-14 11:47:37 +080072/* Generic Interrupt Controller Definitions */
David Feng79bbde02014-03-14 14:26:27 +080073#ifdef CONFIG_GICV3
Peter Hoyes32860372021-11-11 09:26:00 +000074#define GICD_BASE (V2M_PA_BASE + 0x2f000000)
75#define GICR_BASE (V2M_PA_BASE + 0x2f100000)
David Feng79bbde02014-03-14 14:26:27 +080076#else
Darwin Rambod32d4112014-06-09 11:12:59 -070077
Peter Hoyes32860372021-11-11 09:26:00 +000078#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
Linus Walleijc5822502015-01-23 14:41:10 +010079#define GICD_BASE (0x2C010000)
80#define GICC_BASE (0x2C02f000)
Peter Hoyes32860372021-11-11 09:26:00 +000081#else
82#define GICD_BASE (V2M_PA_BASE + 0x2f000000)
83#define GICC_BASE (V2M_PA_BASE + 0x2c000000)
David Feng79bbde02014-03-14 14:26:27 +080084#endif
Linus Walleija90caa32015-03-23 11:06:14 +010085#endif /* !CONFIG_GICV3 */
David Feng3b5458c2013-12-14 11:47:37 +080086
David Feng3b5458c2013-12-14 11:47:37 +080087/* PL011 Serial Configuration */
Linus Walleijc5822502015-01-23 14:41:10 +010088#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
Andre Przywarad3457182020-04-27 19:18:00 +010089#define CONFIG_PL011_CLOCK 7372800
Linus Walleijc5822502015-01-23 14:41:10 +010090#else
David Feng3b5458c2013-12-14 11:47:37 +080091#define CONFIG_PL011_CLOCK 24000000
Linus Walleijc5822502015-01-23 14:41:10 +010092#endif
David Feng3b5458c2013-12-14 11:47:37 +080093
David Feng3b5458c2013-12-14 11:47:37 +080094/* Physical Memory Map */
Andre Przywara87de4b72022-03-04 16:30:16 +000095#define PHYS_SDRAM_1 (V2M_DRAM_BASE) /* SDRAM Bank #1 */
Linus Walleij0a38bfe2015-05-11 10:03:57 +020096/* Top 16MB reserved for secure world use */
97#define DRAM_SEC_SIZE 0x01000000
98#define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE
Tom Rinibb4dd962022-11-16 13:10:37 -050099#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
Linus Walleij0a38bfe2015-05-11 10:03:57 +0200100
Ryan Harkin98d2fff2015-11-18 10:39:07 +0000101#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
Ryan Harkin98d2fff2015-11-18 10:39:07 +0000102#define PHYS_SDRAM_2 (0x880000000)
103#define PHYS_SDRAM_2_SIZE 0x180000000
Peter Hoyes32860372021-11-11 09:26:00 +0000104#elif CONFIG_NR_DRAM_BANKS == 2
Diego Sueiro7a02a1b2021-02-15 07:27:57 +0000105#define PHYS_SDRAM_2 (0x880000000)
106#define PHYS_SDRAM_2_SIZE 0x80000000
Ryan Harkin98d2fff2015-11-18 10:39:07 +0000107#endif
108
Andre Przywaraec41c7f2022-03-04 16:30:12 +0000109/* Copy the kernel, initrd and FDT from NOR flash to DRAM memory and boot. */
Andre Przywarabe035312021-07-12 00:25:15 +0100110#define BOOTENV_DEV_AFS(devtypeu, devtypel, instance) \
111 "bootcmd_afs=" \
112 "afs load ${kernel_name} ${kernel_addr_r} ;"\
113 "if test $? -eq 1; then "\
114 " echo Loading ${kernel_alt_name} instead of ${kernel_name}; "\
115 " afs load ${kernel_alt_name} ${kernel_addr_r};"\
116 "fi ; "\
117 "afs load ${fdtfile} ${fdt_addr_r} ;"\
118 "if test $? -eq 1; then "\
119 " echo Loading ${fdt_alt_name} instead of ${fdtfile}; "\
120 " afs load ${fdt_alt_name} ${fdt_addr_r}; "\
121 "fi ; "\
122 "fdt addr ${fdt_addr_r}; fdt resize; " \
123 "if afs load ${ramdisk_name} ${ramdisk_addr_r} ; "\
124 "then "\
125 " setenv ramdisk_param ${ramdisk_addr_r}; "\
126 "else "\
127 " setenv ramdisk_param -; "\
128 "fi ; " \
129 "booti ${kernel_addr_r} ${ramdisk_param} ${fdt_addr_r}\0"
130#define BOOTENV_DEV_NAME_AFS(devtypeu, devtypel, instance) "afs "
131
Andre Przywara019753a2022-03-04 16:30:14 +0000132/* Boot by executing a U-Boot script pre-loaded into DRAM. */
133#define BOOTENV_DEV_MEM(devtypeu, devtypel, instance) \
134 "bootcmd_mem= " \
135 "source ${scriptaddr}; " \
136 "if test $? -eq 1; then " \
137 " env import -t ${scriptaddr}; " \
138 " if test -n $uenvcmd; then " \
139 " echo Running uenvcmd ...; " \
140 " run uenvcmd; " \
141 " fi; " \
142 "fi\0"
143#define BOOTENV_DEV_NAME_MEM(devtypeu, devtypel, instance) "mem "
144
145#ifdef CONFIG_CMD_VIRTIO
146#define FUNC_VIRTIO(func) func(VIRTIO, virtio, 0)
147#else
148#define FUNC_VIRTIO(func)
149#endif
150
151/*
152 * Boot by loading an Android image, or kernel, initrd and FDT through
153 * semihosting into DRAM.
154 */
155#define BOOTENV_DEV_SMH(devtypeu, devtypel, instance) \
156 "bootcmd_smh= " \
Sean Anderson3e056ba2022-03-22 16:59:22 -0400157 "if load hostfs - ${boot_addr_r} ${boot_name}; then" \
Andre Przywara019753a2022-03-04 16:30:14 +0000158 " setenv bootargs;" \
159 " abootimg addr ${boot_addr_r};" \
160 " abootimg get dtb --index=0 fdt_addr_r;" \
161 " bootm ${boot_addr_r} ${boot_addr_r} ${fdt_addr_r};" \
162 "else" \
Sean Anderson3e056ba2022-03-22 16:59:22 -0400163 " if load hostfs - ${kernel_addr_r} ${kernel_name}; then" \
Andre Przywara019753a2022-03-04 16:30:14 +0000164 " setenv fdt_high 0xffffffffffffffff;" \
165 " setenv initrd_high 0xffffffffffffffff;" \
Sean Anderson3e056ba2022-03-22 16:59:22 -0400166 " load hostfs - ${fdt_addr_r} ${fdtfile};" \
167 " load hostfs - ${ramdisk_addr_r} ${ramdisk_name};" \
Andre Przywara019753a2022-03-04 16:30:14 +0000168 " fdt addr ${fdt_addr_r};" \
169 " fdt resize;" \
Sean Anderson3e056ba2022-03-22 16:59:22 -0400170 " fdt chosen ${ramdisk_addr_r} ${filesize};" \
Andre Przywara019753a2022-03-04 16:30:14 +0000171 " booti $kernel_addr_r - $fdt_addr_r;" \
172 " fi;" \
173 "fi\0"
174#define BOOTENV_DEV_NAME_SMH(devtypeu, devtypel, instance) "smh "
175
Andre Przywaraec41c7f2022-03-04 16:30:12 +0000176/* Boot sources for distro boot and load addresses, per board */
177
178#ifdef CONFIG_TARGET_VEXPRESS64_JUNO /* Arm Juno board */
179
Andre Przywarabe035312021-07-12 00:25:15 +0100180#define BOOT_TARGET_DEVICES(func) \
181 func(USB, usb, 0) \
182 func(SATA, sata, 0) \
183 func(SATA, sata, 1) \
184 func(PXE, pxe, na) \
185 func(DHCP, dhcp, na) \
186 func(AFS, afs, na)
187
Andre Przywaraec41c7f2022-03-04 16:30:12 +0000188#define VEXPRESS_KERNEL_ADDR 0x80080000
189#define VEXPRESS_PXEFILE_ADDR 0x8fb00000
190#define VEXPRESS_FDT_ADDR 0x8fc00000
191#define VEXPRESS_SCRIPT_ADDR 0x8fd00000
192#define VEXPRESS_RAMDISK_ADDR 0x8fe00000
Linus Walleijc39566a2015-04-05 01:48:32 +0200193
Andre Przywaraec41c7f2022-03-04 16:30:12 +0000194#define EXTRA_ENV_NAMES \
195 "kernel_name=norkern\0" \
196 "kernel_alt_name=Image\0" \
197 "ramdisk_name=ramdisk.img\0" \
198 "fdtfile=board.dtb\0" \
199 "fdt_alt_name=juno\0"
Peter Hoyes16fff302021-11-11 09:26:01 +0000200
Andre Przywaraec41c7f2022-03-04 16:30:12 +0000201#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP /* ARMv8-A base model */
Peter Hoyes16fff302021-11-11 09:26:01 +0000202
Andre Przywara019753a2022-03-04 16:30:14 +0000203#define BOOT_TARGET_DEVICES(func) \
204 func(SMH, smh, na) \
205 func(MEM, mem, na) \
206 FUNC_VIRTIO(func) \
207 func(PXE, pxe, na) \
208 func(DHCP, dhcp, na)
209
Andre Przywaraec41c7f2022-03-04 16:30:12 +0000210#define VEXPRESS_KERNEL_ADDR 0x80080000
211#define VEXPRESS_PXEFILE_ADDR 0x8fa00000
212#define VEXPRESS_SCRIPT_ADDR 0x8fb00000
213#define VEXPRESS_FDT_ADDR 0x8fc00000
214#define VEXPRESS_BOOT_ADDR 0x8fd00000
215#define VEXPRESS_RAMDISK_ADDR 0x8fe00000
216
217#define EXTRA_ENV_NAMES \
218 "kernel_name=Image\0" \
219 "ramdisk_name=ramdisk.img\0" \
220 "fdtfile=devtree.dtb\0" \
221 "boot_name=boot.img\0" \
222 "boot_addr_r=" __stringify(VEXPRESS_BOOT_ADDR) "\0"
223
Peter Hoyes3ca0ea02022-03-04 16:30:18 +0000224#elif CONFIG_TARGET_VEXPRESS64_BASER_FVP /* ARMv8-R base model */
225
226#define BOOT_TARGET_DEVICES(func) \
227 func(MEM, mem, na) \
228 FUNC_VIRTIO(func) \
229 func(PXE, pxe, na) \
230 func(DHCP, dhcp, na)
231
232#define VEXPRESS_KERNEL_ADDR 0x00200000
233#define VEXPRESS_PXEFILE_ADDR 0x0fb00000
234#define VEXPRESS_FDT_ADDR 0x0fc00000
235#define VEXPRESS_SCRIPT_ADDR 0x0fd00000
236#define VEXPRESS_RAMDISK_ADDR 0x0fe00000
237
238#define EXTRA_ENV_NAMES \
239 "kernel_name=Image\0" \
240 "ramdisk_name=ramdisk.img\0" \
241 "fdtfile=board.dtb\0"
Darwin Rambod32d4112014-06-09 11:12:59 -0700242#endif
David Feng3b5458c2013-12-14 11:47:37 +0800243
Andre Przywara019753a2022-03-04 16:30:14 +0000244#include <config_distro_bootcmd.h>
245
Andre Przywaraec41c7f2022-03-04 16:30:12 +0000246/* Default load addresses and names for the different payloads. */
247#define CONFIG_EXTRA_ENV_SETTINGS \
248 "kernel_addr_r=" __stringify(VEXPRESS_KERNEL_ADDR) "\0" \
249 "ramdisk_addr_r=" __stringify(VEXPRESS_RAMDISK_ADDR) "\0" \
250 "pxefile_addr_r=" __stringify(VEXPRESS_PXEFILE_ADDR) "\0" \
251 "fdt_addr_r=" __stringify(VEXPRESS_FDT_ADDR) "\0" \
252 "scriptaddr=" __stringify(VEXPRESS_SCRIPT_ADDR) "\0" \
253 EXTRA_ENV_NAMES \
254 BOOTENV
255
Ryan Harkinad5b2a22015-11-18 10:39:09 +0000256#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
Tom Rini6a5dccc2022-11-16 13:10:41 -0500257#define CFG_SYS_FLASH_BASE 0x08000000
Linus Walleij6ba4b6a2015-02-19 17:19:37 +0100258#else
Tom Rini6a5dccc2022-11-16 13:10:41 -0500259#define CFG_SYS_FLASH_BASE (V2M_PA_BASE + 0x0C000000)
Ryan Harkinad5b2a22015-11-18 10:39:09 +0000260#endif
261
Peter Hoyes32860372021-11-11 09:26:00 +0000262#endif /* __VEXPRESS_AEMV8_H */