Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 2 | /* |
Bin Meng | 8c5acf4 | 2014-12-12 21:05:22 +0800 | [diff] [blame] | 3 | * U-Boot - x86 Startup Code |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 4 | * |
Simon Glass | 202a096 | 2019-09-25 08:11:44 -0600 | [diff] [blame] | 5 | * This is always the first code to run from the U-Boot source. To spell it out: |
| 6 | * |
| 7 | * 1. When TPL (Tertiary Program Loader) is enabled, the boot flow is |
| 8 | * TPL->SPL->U-Boot and this file is used for TPL. Then start_from_tpl.S is used |
| 9 | * for SPL and start_from_spl.S is used for U-Boot proper. |
| 10 | * |
| 11 | * 2. When SPL (Secondary Program Loader) is enabled, but not TPL, the boot |
| 12 | * flow is SPL->U-Boot and this file is used for SPL. Then start_from_spl.S is |
| 13 | * used for U-Boot proper. |
| 14 | * |
| 15 | * 3. When neither TPL nor SPL is used, this file is used for U-Boot proper. |
| 16 | * |
Graeme Russ | 45fc1d8 | 2011-04-13 19:43:26 +1000 | [diff] [blame] | 17 | * (C) Copyright 2008-2011 |
| 18 | * Graeme Russ, <graeme.russ@gmail.com> |
| 19 | * |
| 20 | * (C) Copyright 2002 |
Albert ARIBAUD | 60fbc8d | 2011-08-04 18:45:45 +0200 | [diff] [blame] | 21 | * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 22 | */ |
| 23 | |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 24 | #include <config.h> |
Graeme Russ | 5fb91cc | 2010-10-07 20:03:29 +1100 | [diff] [blame] | 25 | #include <asm/global_data.h> |
Simon Glass | 245561d | 2014-11-12 22:42:09 -0700 | [diff] [blame] | 26 | #include <asm/post.h> |
Graeme Russ | 391bb95 | 2011-12-31 10:24:36 +1100 | [diff] [blame] | 27 | #include <asm/processor.h> |
Graeme Russ | 93efcb2 | 2011-02-12 15:11:32 +1100 | [diff] [blame] | 28 | #include <asm/processor-flags.h> |
Graeme Russ | 3536896 | 2011-12-31 22:58:15 +1100 | [diff] [blame] | 29 | #include <generated/generic-asm-offsets.h> |
Bin Meng | 8c5acf4 | 2014-12-12 21:05:22 +0800 | [diff] [blame] | 30 | #include <generated/asm-offsets.h> |
Bin Meng | 253a24a | 2018-10-25 03:05:37 -0700 | [diff] [blame] | 31 | #include <linux/linkage.h> |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 32 | |
Alexander Graf | 94a10f2 | 2018-06-12 07:48:37 +0200 | [diff] [blame] | 33 | .section .text.start |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 34 | .code32 |
| 35 | .globl _start |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 36 | .type _start, @function |
Graeme Russ | cbfce1d | 2011-04-13 19:43:28 +1000 | [diff] [blame] | 37 | .globl _x86boot_start |
| 38 | _x86boot_start: |
Graeme Russ | 8accbb9 | 2010-04-24 00:05:42 +1000 | [diff] [blame] | 39 | /* |
Simon Glass | 611f749 | 2015-07-31 09:31:25 -0600 | [diff] [blame] | 40 | * This is the fail-safe 32-bit bootstrap entry point. |
| 41 | * |
| 42 | * This code is used when booting from another boot loader like |
| 43 | * coreboot or EFI. So we repeat some of the same init found in |
| 44 | * start16. |
Graeme Russ | 8accbb9 | 2010-04-24 00:05:42 +1000 | [diff] [blame] | 45 | */ |
| 46 | cli |
| 47 | cld |
| 48 | |
Graeme Russ | c379b5d | 2011-11-08 02:33:23 +0000 | [diff] [blame] | 49 | /* Turn off cache (this might require a 486-class CPU) */ |
Graeme Russ | 8accbb9 | 2010-04-24 00:05:42 +1000 | [diff] [blame] | 50 | movl %cr0, %eax |
Graeme Russ | 93efcb2 | 2011-02-12 15:11:32 +1100 | [diff] [blame] | 51 | orl $(X86_CR0_NW | X86_CR0_CD), %eax |
Graeme Russ | 8accbb9 | 2010-04-24 00:05:42 +1000 | [diff] [blame] | 52 | movl %eax, %cr0 |
Andy Shevchenko | f3514a6 | 2020-02-17 17:30:12 +0200 | [diff] [blame] | 53 | wbinvd |
Graeme Russ | 8accbb9 | 2010-04-24 00:05:42 +1000 | [diff] [blame] | 54 | |
Simon Glass | f95ad8c | 2015-08-04 12:33:57 -0600 | [diff] [blame] | 55 | /* |
| 56 | * Zero the BIST (Built-In Self Test) value since we don't have it. |
| 57 | * It must be 0 or the previous loader would have reported an error. |
| 58 | */ |
| 59 | movl $0, %ebp |
| 60 | |
Gabe Black | ef89932 | 2012-11-03 11:41:28 +0000 | [diff] [blame] | 61 | jmp 1f |
Simon Glass | 5d18dc9 | 2015-07-31 09:31:28 -0600 | [diff] [blame] | 62 | |
| 63 | /* Add a way for tools to discover the _start entry point */ |
| 64 | .align 4 |
| 65 | .long 0x12345678 |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 66 | _start: |
Stefan Roese | faa8821 | 2019-08-16 14:45:28 +0200 | [diff] [blame] | 67 | /* This is the 32-bit cold-reset entry point, coming from start16 */ |
Simon Glass | f95ad8c | 2015-08-04 12:33:57 -0600 | [diff] [blame] | 68 | |
Simon Glass | 1f4476c | 2014-11-06 13:20:10 -0700 | [diff] [blame] | 69 | /* Save BIST */ |
| 70 | movl %eax, %ebp |
Simon Glass | f95ad8c | 2015-08-04 12:33:57 -0600 | [diff] [blame] | 71 | 1: |
| 72 | |
| 73 | /* Save table pointer */ |
| 74 | movl %ecx, %esi |
Graeme Russ | 8accbb9 | 2010-04-24 00:05:42 +1000 | [diff] [blame] | 75 | |
Andy Shevchenko | 2ae7da0 | 2017-02-05 16:52:00 +0300 | [diff] [blame] | 76 | #ifdef CONFIG_X86_LOAD_FROM_32_BIT |
Simon Glass | b4ded74 | 2016-03-16 07:44:40 -0600 | [diff] [blame] | 77 | lgdt gdt_ptr2 |
| 78 | #endif |
| 79 | |
Simon Glass | 611f749 | 2015-07-31 09:31:25 -0600 | [diff] [blame] | 80 | /* Load the segement registers to match the GDT loaded in start16.S */ |
Graeme Russ | 391bb95 | 2011-12-31 10:24:36 +1100 | [diff] [blame] | 81 | movl $(X86_GDT_ENTRY_32BIT_DS * X86_GDT_ENTRY_SIZE), %eax |
Graeme Russ | 3e6ec38 | 2010-10-07 20:03:21 +1100 | [diff] [blame] | 82 | movw %ax, %fs |
| 83 | movw %ax, %ds |
| 84 | movw %ax, %gs |
| 85 | movw %ax, %es |
| 86 | movw %ax, %ss |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 87 | |
Mike Williams | bf895ad | 2011-07-22 04:01:30 +0000 | [diff] [blame] | 88 | /* Clear the interrupt vectors */ |
Graeme Russ | 8accbb9 | 2010-04-24 00:05:42 +1000 | [diff] [blame] | 89 | lidt blank_idt_ptr |
| 90 | |
Andy Shevchenko | 3e90244 | 2020-08-20 13:02:20 +0300 | [diff] [blame] | 91 | #ifdef CONFIG_USE_EARLY_BOARD_INIT |
Simon Glass | 611f749 | 2015-07-31 09:31:25 -0600 | [diff] [blame] | 92 | /* |
| 93 | * Critical early platform init - generally not used, we prefer init |
| 94 | * to happen later when we have a console, in case something goes |
| 95 | * wrong. |
| 96 | */ |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 97 | jmp early_board_init |
Graeme Russ | 157b0e9 | 2010-10-07 20:03:27 +1100 | [diff] [blame] | 98 | .globl early_board_init_ret |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 99 | early_board_init_ret: |
Andy Shevchenko | 3e90244 | 2020-08-20 13:02:20 +0300 | [diff] [blame] | 100 | #endif |
| 101 | |
Simon Glass | 245561d | 2014-11-12 22:42:09 -0700 | [diff] [blame] | 102 | post_code(POST_START) |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 103 | |
Graeme Russ | bc76193 | 2011-02-12 15:11:52 +1100 | [diff] [blame] | 104 | /* Initialise Cache-As-RAM */ |
| 105 | jmp car_init |
| 106 | .globl car_init_ret |
| 107 | car_init_ret: |
Simon Glass | 9e60b43 | 2019-09-25 08:11:43 -0600 | [diff] [blame] | 108 | #ifdef CONFIG_USE_CAR |
Graeme Russ | bc76193 | 2011-02-12 15:11:52 +1100 | [diff] [blame] | 109 | /* |
| 110 | * We now have CONFIG_SYS_CAR_SIZE bytes of Cache-As-RAM (or SRAM, |
| 111 | * or fully initialised SDRAM - we really don't care which) |
| 112 | * starting at CONFIG_SYS_CAR_ADDR to be used as a temporary stack |
Simon Glass | 611f749 | 2015-07-31 09:31:25 -0600 | [diff] [blame] | 113 | * and early malloc() area. The MRC requires some space at the top. |
Simon Glass | a4fd0db | 2014-11-06 13:20:04 -0700 | [diff] [blame] | 114 | * |
| 115 | * Stack grows down from top of CAR. We have: |
| 116 | * |
| 117 | * top-> CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE |
Simon Glass | 268eefd | 2014-11-12 22:42:28 -0700 | [diff] [blame] | 118 | * MRC area |
Simon Glass | 0e27b87 | 2015-08-10 20:44:32 -0600 | [diff] [blame] | 119 | * global_data with x86 global descriptor table |
Simon Glass | a4fd0db | 2014-11-06 13:20:04 -0700 | [diff] [blame] | 120 | * early malloc area |
| 121 | * stack |
| 122 | * bottom-> CONFIG_SYS_CAR_ADDR |
Graeme Russ | bc76193 | 2011-02-12 15:11:52 +1100 | [diff] [blame] | 123 | */ |
Simon Glass | 268eefd | 2014-11-12 22:42:28 -0700 | [diff] [blame] | 124 | movl $(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE - 4), %esp |
| 125 | #ifdef CONFIG_DCACHE_RAM_MRC_VAR_SIZE |
| 126 | subl $CONFIG_DCACHE_RAM_MRC_VAR_SIZE, %esp |
| 127 | #endif |
Bin Meng | 005f0af | 2014-12-12 21:05:31 +0800 | [diff] [blame] | 128 | #else |
| 129 | /* |
Simon Glass | 1062e34 | 2020-07-16 21:22:35 -0600 | [diff] [blame] | 130 | * Instructions for FSP1, but not FSP2: |
Bin Meng | 73574dc | 2015-08-20 06:40:20 -0700 | [diff] [blame] | 131 | * U-Boot enters here twice. For the first time it comes from |
| 132 | * car_init_done() with esp points to a temporary stack and esi |
| 133 | * set to zero. For the second time it comes from fsp_init_done() |
| 134 | * with esi holding the HOB list address returned by the FSP. |
Bin Meng | 005f0af | 2014-12-12 21:05:31 +0800 | [diff] [blame] | 135 | */ |
| 136 | #endif |
Simon Glass | 0e27b87 | 2015-08-10 20:44:32 -0600 | [diff] [blame] | 137 | /* Set up global data */ |
| 138 | mov %esp, %eax |
Albert ARIBAUD | 6cb4c46 | 2015-11-25 17:56:32 +0100 | [diff] [blame] | 139 | call board_init_f_alloc_reserve |
Simon Glass | 0e27b87 | 2015-08-10 20:44:32 -0600 | [diff] [blame] | 140 | mov %eax, %esp |
Albert ARIBAUD | 6cb4c46 | 2015-11-25 17:56:32 +0100 | [diff] [blame] | 141 | call board_init_f_init_reserve |
Graeme Russ | 007818a | 2012-11-27 15:38:36 +0000 | [diff] [blame] | 142 | |
Simon Glass | 4773012 | 2015-10-18 19:51:26 -0600 | [diff] [blame] | 143 | #ifdef CONFIG_DEBUG_UART |
| 144 | call debug_uart_init |
| 145 | #endif |
Simon Glass | 9bbb37f | 2015-08-02 18:07:21 -0600 | [diff] [blame] | 146 | |
Simon Glass | 0e27b87 | 2015-08-10 20:44:32 -0600 | [diff] [blame] | 147 | /* Get address of global_data */ |
| 148 | mov %fs:0, %edx |
Simon Glass | 9e60b43 | 2019-09-25 08:11:43 -0600 | [diff] [blame] | 149 | #if defined(CONFIG_USE_HOB) && !defined(CONFIG_USE_CAR) |
Simon Glass | 0e27b87 | 2015-08-10 20:44:32 -0600 | [diff] [blame] | 150 | /* Store the HOB list if we have one */ |
Bin Meng | d560c5c | 2015-06-07 11:33:14 +0800 | [diff] [blame] | 151 | test %esi, %esi |
| 152 | jz skip_hob |
Simon Glass | 0e27b87 | 2015-08-10 20:44:32 -0600 | [diff] [blame] | 153 | movl %esi, GD_HOB_LIST(%edx) |
Bin Meng | 005f0af | 2014-12-12 21:05:31 +0800 | [diff] [blame] | 154 | |
Park, Aiden | 6e3cc36 | 2019-08-03 08:30:12 +0000 | [diff] [blame] | 155 | #ifdef CONFIG_HAVE_FSP |
Bin Meng | 12440cd | 2015-08-20 06:40:19 -0700 | [diff] [blame] | 156 | /* |
| 157 | * After fsp_init() returns, the stack has already been switched to a |
| 158 | * place within system memory as defined by CONFIG_FSP_TEMP_RAM_ADDR. |
| 159 | * Enlarge the size of malloc() pool before relocation since we have |
| 160 | * plenty of memory now. |
| 161 | */ |
| 162 | subl $CONFIG_FSP_SYS_MALLOC_F_LEN, %esp |
| 163 | movl %esp, GD_MALLOC_BASE(%edx) |
Park, Aiden | 6e3cc36 | 2019-08-03 08:30:12 +0000 | [diff] [blame] | 164 | #endif |
Bin Meng | d560c5c | 2015-06-07 11:33:14 +0800 | [diff] [blame] | 165 | skip_hob: |
Simon Glass | f95ad8c | 2015-08-04 12:33:57 -0600 | [diff] [blame] | 166 | #else |
| 167 | /* Store table pointer */ |
Simon Glass | 0e27b87 | 2015-08-10 20:44:32 -0600 | [diff] [blame] | 168 | movl %esi, GD_TABLE(%edx) |
Bin Meng | d560c5c | 2015-06-07 11:33:14 +0800 | [diff] [blame] | 169 | #endif |
Simon Glass | 0e27b87 | 2015-08-10 20:44:32 -0600 | [diff] [blame] | 170 | /* Store BIST */ |
| 171 | movl %ebp, GD_BIST(%edx) |
Graeme Russ | 3536896 | 2011-12-31 22:58:15 +1100 | [diff] [blame] | 172 | |
Graeme Russ | 3818393 | 2011-02-12 15:11:54 +1100 | [diff] [blame] | 173 | /* Set parameter to board_init_f() to boot flags */ |
Simon Glass | 245561d | 2014-11-12 22:42:09 -0700 | [diff] [blame] | 174 | post_code(POST_START_DONE) |
Graeme Russ | 45fc1d8 | 2011-04-13 19:43:26 +1000 | [diff] [blame] | 175 | xorl %eax, %eax |
Graeme Russ | 5fb91cc | 2010-10-07 20:03:29 +1100 | [diff] [blame] | 176 | |
Simon Glass | 611f749 | 2015-07-31 09:31:25 -0600 | [diff] [blame] | 177 | /* Enter, U-Boot! */ |
Graeme Russ | 45fc1d8 | 2011-04-13 19:43:26 +1000 | [diff] [blame] | 178 | call board_init_f |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 179 | |
| 180 | /* indicate (lack of) progress */ |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 181 | movw $0x85, %ax |
Graeme Russ | 9c44afc | 2011-02-12 15:11:58 +1100 | [diff] [blame] | 182 | jmp die |
| 183 | |
Graeme Russ | d7755b4 | 2012-01-01 15:06:39 +1100 | [diff] [blame] | 184 | .globl board_init_f_r_trampoline |
| 185 | .type board_init_f_r_trampoline, @function |
| 186 | board_init_f_r_trampoline: |
Graeme Russ | 9c44afc | 2011-02-12 15:11:58 +1100 | [diff] [blame] | 187 | /* |
| 188 | * SDRAM has been initialised, U-Boot code has been copied into |
| 189 | * RAM, BSS has been cleared and relocation adjustments have been |
| 190 | * made. It is now time to jump into the in-RAM copy of U-Boot |
| 191 | * |
Graeme Russ | d7755b4 | 2012-01-01 15:06:39 +1100 | [diff] [blame] | 192 | * %eax = Address of top of new stack |
Graeme Russ | 9c44afc | 2011-02-12 15:11:58 +1100 | [diff] [blame] | 193 | */ |
| 194 | |
Graeme Russ | 007818a | 2012-11-27 15:38:36 +0000 | [diff] [blame] | 195 | /* Stack grows down from top of SDRAM */ |
Graeme Russ | 9c44afc | 2011-02-12 15:11:58 +1100 | [diff] [blame] | 196 | movl %eax, %esp |
| 197 | |
Simon Glass | 0e27b87 | 2015-08-10 20:44:32 -0600 | [diff] [blame] | 198 | /* See if we need to disable CAR */ |
Simon Glass | 78da72c | 2015-01-01 16:18:13 -0700 | [diff] [blame] | 199 | call car_uninit |
Bin Meng | 253a24a | 2018-10-25 03:05:37 -0700 | [diff] [blame] | 200 | |
Simon Glass | 611f749 | 2015-07-31 09:31:25 -0600 | [diff] [blame] | 201 | /* Re-enter U-Boot by calling board_init_f_r() */ |
Graeme Russ | d7755b4 | 2012-01-01 15:06:39 +1100 | [diff] [blame] | 202 | call board_init_f_r |
Graeme Russ | 9c44afc | 2011-02-12 15:11:58 +1100 | [diff] [blame] | 203 | |
Simon Glass | d4f266f | 2019-05-02 10:52:27 -0600 | [diff] [blame] | 204 | #ifdef CONFIG_TPL |
| 205 | .globl jump_to_spl |
| 206 | .type jump_to_spl, @function |
| 207 | jump_to_spl: |
| 208 | /* Reset stack to the top of CAR space */ |
| 209 | movl $(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE - 4), %esp |
| 210 | #ifdef CONFIG_DCACHE_RAM_MRC_VAR_SIZE |
| 211 | subl $CONFIG_DCACHE_RAM_MRC_VAR_SIZE, %esp |
| 212 | #endif |
| 213 | |
| 214 | jmp *%eax |
| 215 | #endif |
| 216 | |
Graeme Russ | c379b5d | 2011-11-08 02:33:23 +0000 | [diff] [blame] | 217 | die: |
| 218 | hlt |
wdenk | 591dda5 | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 219 | jmp die |
wdenk | 57b2d80 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 220 | hlt |
Graeme Russ | 8accbb9 | 2010-04-24 00:05:42 +1000 | [diff] [blame] | 221 | |
Bin Meng | 253a24a | 2018-10-25 03:05:37 -0700 | [diff] [blame] | 222 | WEAK(car_uninit) |
| 223 | ret |
| 224 | ENDPROC(car_uninit) |
| 225 | |
Graeme Russ | 8accbb9 | 2010-04-24 00:05:42 +1000 | [diff] [blame] | 226 | blank_idt_ptr: |
| 227 | .word 0 /* limit */ |
| 228 | .long 0 /* base */ |
Graeme Russ | 786c395 | 2011-11-08 02:33:19 +0000 | [diff] [blame] | 229 | |
| 230 | .p2align 2 /* force 4-byte alignment */ |
| 231 | |
Simon Glass | 611f749 | 2015-07-31 09:31:25 -0600 | [diff] [blame] | 232 | /* Add a multiboot header so U-Boot can be loaded by GRUB2 */ |
Graeme Russ | 786c395 | 2011-11-08 02:33:19 +0000 | [diff] [blame] | 233 | multiboot_header: |
| 234 | /* magic */ |
Simon Glass | 611f749 | 2015-07-31 09:31:25 -0600 | [diff] [blame] | 235 | .long 0x1badb002 |
Graeme Russ | 786c395 | 2011-11-08 02:33:19 +0000 | [diff] [blame] | 236 | /* flags */ |
| 237 | .long (1 << 16) |
| 238 | /* checksum */ |
| 239 | .long -0x1BADB002 - (1 << 16) |
| 240 | /* header addr */ |
| 241 | .long multiboot_header - _x86boot_start + CONFIG_SYS_TEXT_BASE |
| 242 | /* load addr */ |
| 243 | .long CONFIG_SYS_TEXT_BASE |
| 244 | /* load end addr */ |
| 245 | .long 0 |
| 246 | /* bss end addr */ |
| 247 | .long 0 |
| 248 | /* entry addr */ |
| 249 | .long CONFIG_SYS_TEXT_BASE |
Simon Glass | b4ded74 | 2016-03-16 07:44:40 -0600 | [diff] [blame] | 250 | |
Andy Shevchenko | 2ae7da0 | 2017-02-05 16:52:00 +0300 | [diff] [blame] | 251 | #ifdef CONFIG_X86_LOAD_FROM_32_BIT |
Simon Glass | b4ded74 | 2016-03-16 07:44:40 -0600 | [diff] [blame] | 252 | /* |
| 253 | * The following Global Descriptor Table is just enough to get us into |
| 254 | * 'Flat Protected Mode' - It will be discarded as soon as the final |
| 255 | * GDT is setup in a safe location in RAM |
| 256 | */ |
| 257 | gdt_ptr2: |
| 258 | .word 0x1f /* limit (31 bytes = 4 GDT entries - 1) */ |
| 259 | .long gdt_rom2 /* base */ |
| 260 | |
| 261 | /* Some CPUs are picky about GDT alignment... */ |
| 262 | .align 16 |
| 263 | .globl gdt_rom2 |
| 264 | gdt_rom2: |
| 265 | /* |
| 266 | * The GDT table ... |
| 267 | * |
| 268 | * Selector Type |
| 269 | * 0x00 NULL |
| 270 | * 0x08 Unused |
| 271 | * 0x10 32bit code |
| 272 | * 0x18 32bit data/stack |
| 273 | */ |
| 274 | /* The NULL Desciptor - Mandatory */ |
| 275 | .word 0x0000 /* limit_low */ |
| 276 | .word 0x0000 /* base_low */ |
| 277 | .byte 0x00 /* base_middle */ |
| 278 | .byte 0x00 /* access */ |
| 279 | .byte 0x00 /* flags + limit_high */ |
| 280 | .byte 0x00 /* base_high */ |
| 281 | |
| 282 | /* Unused Desciptor - (matches Linux) */ |
| 283 | .word 0x0000 /* limit_low */ |
| 284 | .word 0x0000 /* base_low */ |
| 285 | .byte 0x00 /* base_middle */ |
| 286 | .byte 0x00 /* access */ |
| 287 | .byte 0x00 /* flags + limit_high */ |
| 288 | .byte 0x00 /* base_high */ |
| 289 | |
| 290 | /* |
| 291 | * The Code Segment Descriptor: |
| 292 | * - Base = 0x00000000 |
| 293 | * - Size = 4GB |
| 294 | * - Access = Present, Ring 0, Exec (Code), Readable |
| 295 | * - Flags = 4kB Granularity, 32-bit |
| 296 | */ |
| 297 | .word 0xffff /* limit_low */ |
| 298 | .word 0x0000 /* base_low */ |
| 299 | .byte 0x00 /* base_middle */ |
| 300 | .byte 0x9b /* access */ |
| 301 | .byte 0xcf /* flags + limit_high */ |
| 302 | .byte 0x00 /* base_high */ |
| 303 | |
| 304 | /* |
| 305 | * The Data Segment Descriptor: |
| 306 | * - Base = 0x00000000 |
| 307 | * - Size = 4GB |
| 308 | * - Access = Present, Ring 0, Non-Exec (Data), Writable |
| 309 | * - Flags = 4kB Granularity, 32-bit |
| 310 | */ |
| 311 | .word 0xffff /* limit_low */ |
| 312 | .word 0x0000 /* base_low */ |
| 313 | .byte 0x00 /* base_middle */ |
| 314 | .byte 0x93 /* access */ |
| 315 | .byte 0xcf /* flags + limit_high */ |
| 316 | .byte 0x00 /* base_high */ |
| 317 | #endif |