blob: f0b3c5f83f47868869ffcd97e9b4ae161f23a6f3 [file] [log] [blame]
Heiko Stuebnerfc367852019-07-16 22:18:21 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd
4 */
5
Heiko Stuebnerfc367852019-07-16 22:18:21 +02006#include <debug_uart.h>
7#include <dm.h>
Simon Glass97589732020-05-10 11:40:02 -06008#include <init.h>
Heiko Stuebnerfc367852019-07-16 22:18:21 +02009#include <ram.h>
10#include <spl.h>
Heiko Stuebnerfc367852019-07-16 22:18:21 +020011#include <asm/io.h>
12#include <asm/arch-rockchip/bootrom.h>
13#include <asm/arch-rockchip/sdram_px30.h>
14
15#define TIMER_LOAD_COUNT0 0x00
16#define TIMER_LOAD_COUNT1 0x04
17#define TIMER_CUR_VALUE0 0x08
18#define TIMER_CUR_VALUE1 0x0c
19#define TIMER_CONTROL_REG 0x10
20
21#define TIMER_EN 0x1
22#define TIMER_FMODE (0 << 1)
23#define TIMER_RMODE (1 << 1)
24
25void secure_timer_init(void)
26{
27 writel(0, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
28 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_LOAD_COUNT0);
29 writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + TIMER_LOAD_COUNT1);
30 writel(TIMER_EN | TIMER_FMODE,
31 CONFIG_ROCKCHIP_STIMER_BASE + TIMER_CONTROL_REG);
32}
33
34void board_init_f(ulong dummy)
35{
36 int ret;
37
Lukasz Czechowski6460a702024-04-17 13:21:28 +020038#if defined(CONFIG_DEBUG_UART) && defined(CONFIG_TPL_SERIAL)
Heiko Stuebnerfc367852019-07-16 22:18:21 +020039 debug_uart_init();
40 /*
41 * Debug UART can be used from here if required:
42 *
43 * debug_uart_init();
44 * printch('a');
45 * printhex8(0x1234);
46 * printascii("string");
47 */
Lukasz Czechowski6460a702024-04-17 13:21:28 +020048#if CONFIG_TPL_BANNER_PRINT
Heiko Stuebnerfc367852019-07-16 22:18:21 +020049 printascii("U-Boot TPL board init\n");
50#endif
Lukasz Czechowski6460a702024-04-17 13:21:28 +020051#endif
Heiko Stuebnerfc367852019-07-16 22:18:21 +020052
53 secure_timer_init();
54 ret = sdram_init();
55 if (ret)
56 printascii("sdram_init failed\n");
57
58 /* return to maskrom */
59 back_to_bootrom(BROM_BOOT_NEXTSTAGE);
60}