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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Ilya Yanoke93a4a52009-07-21 19:32:21 +04002/*
3 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
4 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
5 * (C) Copyright 2008 Armadeus Systems nc
6 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
7 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
Ilya Yanoke93a4a52009-07-21 19:32:21 +04008 */
9
10#include <common.h>
Simon Glass63334482019-11-14 12:57:39 -070011#include <cpu_func.h>
Jagan Teki484f0212016-12-06 00:00:49 +010012#include <dm.h>
Simon Glass5e6201b2019-08-01 09:46:51 -060013#include <env.h>
Ilya Yanoke93a4a52009-07-21 19:32:21 +040014#include <malloc.h>
Simon Glass2dd337a2015-09-02 17:24:58 -060015#include <memalign.h>
Jagan Tekic6cd8d52016-12-06 00:00:50 +010016#include <miiphy.h>
Ilya Yanoke93a4a52009-07-21 19:32:21 +040017#include <net.h>
Jeroen Hofstee120f43f2014-10-08 22:57:40 +020018#include <netdev.h>
Martin Fuzzey9a6a2c92018-10-04 19:59:20 +020019#include <power/regulator.h>
Ilya Yanoke93a4a52009-07-21 19:32:21 +040020
Ilya Yanoke93a4a52009-07-21 19:32:21 +040021#include <asm/io.h>
Masahiro Yamada56a931c2016-09-21 11:28:55 +090022#include <linux/errno.h>
Marek Vasut4d85b032012-08-26 10:19:20 +000023#include <linux/compiler.h>
Ilya Yanoke93a4a52009-07-21 19:32:21 +040024
Jagan Tekic6cd8d52016-12-06 00:00:50 +010025#include <asm/arch/clock.h>
26#include <asm/arch/imx-regs.h>
Stefano Babic33731bc2017-06-29 10:16:06 +020027#include <asm/mach-imx/sys_proto.h>
Michael Trimarchi0e5cccf2018-06-17 15:22:39 +020028#include <asm-generic/gpio.h>
29
30#include "fec_mxc.h"
Jagan Tekic6cd8d52016-12-06 00:00:50 +010031
Ilya Yanoke93a4a52009-07-21 19:32:21 +040032DECLARE_GLOBAL_DATA_PTR;
33
Marek Vasut5f1631d2012-08-29 03:49:49 +000034/*
35 * Timeout the transfer after 5 mS. This is usually a bit more, since
36 * the code in the tightloops this timeout is used in adds some overhead.
37 */
38#define FEC_XFER_TIMEOUT 5000
39
Fabio Estevam8b798b22014-08-25 13:34:16 -030040/*
41 * The standard 32-byte DMA alignment does not work on mx6solox, which requires
42 * 64-byte alignment in the DMA RX FEC buffer.
43 * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
44 * satisfies the alignment on other SoCs (32-bytes)
45 */
46#define FEC_DMA_RX_MINALIGN 64
47
Ilya Yanoke93a4a52009-07-21 19:32:21 +040048#ifndef CONFIG_MII
49#error "CONFIG_MII has to be defined!"
50#endif
51
Eric Nelson3d2f7272012-03-15 18:33:25 +000052#ifndef CONFIG_FEC_XCV_TYPE
53#define CONFIG_FEC_XCV_TYPE MII100
Marek Vasutdbb4fce2011-09-11 18:05:33 +000054#endif
55
Marek Vasut6a5fd4c2011-11-08 23:18:10 +000056/*
57 * The i.MX28 operates with packets in big endian. We need to swap them before
58 * sending and after receiving.
59 */
Eric Nelson3d2f7272012-03-15 18:33:25 +000060#ifdef CONFIG_MX28
61#define CONFIG_FEC_MXC_SWAP_PACKET
Marek Vasut6a5fd4c2011-11-08 23:18:10 +000062#endif
63
Eric Nelson3d2f7272012-03-15 18:33:25 +000064#define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
65
66/* Check various alignment issues at compile time */
67#if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
68#error "ARCH_DMA_MINALIGN must be multiple of 16!"
69#endif
70
71#if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
72 (PKTALIGN % ARCH_DMA_MINALIGN != 0))
73#error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
74#endif
75
Ilya Yanoke93a4a52009-07-21 19:32:21 +040076#undef DEBUG
77
Eric Nelson3d2f7272012-03-15 18:33:25 +000078#ifdef CONFIG_FEC_MXC_SWAP_PACKET
Marek Vasut6a5fd4c2011-11-08 23:18:10 +000079static void swap_packet(uint32_t *packet, int length)
80{
81 int i;
82
83 for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
84 packet[i] = __swab32(packet[i]);
85}
86#endif
87
Jagan Tekic6cd8d52016-12-06 00:00:50 +010088/* MII-interface related functions */
89static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr,
90 uint8_t regaddr)
Ilya Yanoke93a4a52009-07-21 19:32:21 +040091{
Ilya Yanoke93a4a52009-07-21 19:32:21 +040092 uint32_t reg; /* convenient holder for the PHY register */
93 uint32_t phy; /* convenient holder for the PHY */
94 uint32_t start;
Troy Kisky2000c662012-02-07 14:08:47 +000095 int val;
Ilya Yanoke93a4a52009-07-21 19:32:21 +040096
97 /*
98 * reading from any PHY's register is done by properly
99 * programming the FEC's MII data register.
100 */
Marek Vasutbf2386b2011-09-11 18:05:34 +0000101 writel(FEC_IEVENT_MII, &eth->ievent);
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100102 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
103 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400104
105 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
Marek Vasutbf2386b2011-09-11 18:05:34 +0000106 phy | reg, &eth->mii_data);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400107
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100108 /* wait for the related interrupt */
Graeme Russf8b82ee2011-07-15 23:31:37 +0000109 start = get_timer(0);
Marek Vasutbf2386b2011-09-11 18:05:34 +0000110 while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400111 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
112 printf("Read MDIO failed...\n");
113 return -1;
114 }
115 }
116
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100117 /* clear mii interrupt bit */
Marek Vasutbf2386b2011-09-11 18:05:34 +0000118 writel(FEC_IEVENT_MII, &eth->ievent);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400119
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100120 /* it's now safe to read the PHY's register */
Troy Kisky2000c662012-02-07 14:08:47 +0000121 val = (unsigned short)readl(&eth->mii_data);
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100122 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
123 regaddr, val);
Troy Kisky2000c662012-02-07 14:08:47 +0000124 return val;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400125}
126
Peng Fandcf5e1b2019-10-25 09:48:02 +0000127#ifndef imx_get_fecclk
128u32 __weak imx_get_fecclk(void)
129{
130 return 0;
131}
132#endif
133
Anatolij Gustschinb71fc5e2018-10-18 16:15:11 +0200134static int fec_get_clk_rate(void *udev, int idx)
135{
Anatolij Gustschinb71fc5e2018-10-18 16:15:11 +0200136 struct fec_priv *fec;
137 struct udevice *dev;
138 int ret;
139
Peng Fandcf5e1b2019-10-25 09:48:02 +0000140 if (IS_ENABLED(CONFIG_IMX8) ||
141 CONFIG_IS_ENABLED(CLK_CCF)) {
142 dev = udev;
143 if (!dev) {
144 ret = uclass_get_device(UCLASS_ETH, idx, &dev);
145 if (ret < 0) {
146 debug("Can't get FEC udev: %d\n", ret);
147 return ret;
148 }
Anatolij Gustschinb71fc5e2018-10-18 16:15:11 +0200149 }
Anatolij Gustschinb71fc5e2018-10-18 16:15:11 +0200150
Peng Fandcf5e1b2019-10-25 09:48:02 +0000151 fec = dev_get_priv(dev);
152 if (fec)
153 return fec->clk_rate;
Anatolij Gustschinb71fc5e2018-10-18 16:15:11 +0200154
Peng Fandcf5e1b2019-10-25 09:48:02 +0000155 return -EINVAL;
156 } else {
157 return imx_get_fecclk();
158 }
Anatolij Gustschinb71fc5e2018-10-18 16:15:11 +0200159}
160
Troy Kisky5e762652012-10-22 16:40:41 +0000161static void fec_mii_setspeed(struct ethernet_regs *eth)
Stefano Babic889f2e22010-02-01 14:51:30 +0100162{
163 /*
164 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
165 * and do not drop the Preamble.
Måns Rullgård4aeddb72015-12-08 15:38:45 +0000166 *
167 * The i.MX28 and i.MX6 types have another field in the MSCR (aka
168 * MII_SPEED) register that defines the MDIO output hold time. Earlier
169 * versions are RAZ there, so just ignore the difference and write the
170 * register always.
171 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
172 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
173 * output.
174 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
175 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
176 * holdtime cannot result in a value greater than 3.
Stefano Babic889f2e22010-02-01 14:51:30 +0100177 */
Anatolij Gustschinb71fc5e2018-10-18 16:15:11 +0200178 u32 pclk;
179 u32 speed;
180 u32 hold;
181 int ret;
182
183 ret = fec_get_clk_rate(NULL, 0);
184 if (ret < 0) {
185 printf("Can't find FEC0 clk rate: %d\n", ret);
186 return;
187 }
188 pclk = ret;
189 speed = DIV_ROUND_UP(pclk, 5000000);
190 hold = DIV_ROUND_UP(pclk, 100000000) - 1;
191
Markus Niebel1af82742014-02-05 10:54:11 +0100192#ifdef FEC_QUIRK_ENET_MAC
193 speed--;
194#endif
Måns Rullgård4aeddb72015-12-08 15:38:45 +0000195 writel(speed << 1 | hold << 8, &eth->mii_speed);
Troy Kisky5e762652012-10-22 16:40:41 +0000196 debug("%s: mii_speed %08x\n", __func__, readl(&eth->mii_speed));
Stefano Babic889f2e22010-02-01 14:51:30 +0100197}
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400198
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100199static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr,
200 uint8_t regaddr, uint16_t data)
Troy Kisky2000c662012-02-07 14:08:47 +0000201{
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400202 uint32_t reg; /* convenient holder for the PHY register */
203 uint32_t phy; /* convenient holder for the PHY */
204 uint32_t start;
205
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100206 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
207 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400208
209 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
Marek Vasutbf2386b2011-09-11 18:05:34 +0000210 FEC_MII_DATA_TA | phy | reg | data, &eth->mii_data);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400211
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100212 /* wait for the MII interrupt */
Graeme Russf8b82ee2011-07-15 23:31:37 +0000213 start = get_timer(0);
Marek Vasutbf2386b2011-09-11 18:05:34 +0000214 while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400215 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
216 printf("Write MDIO failed...\n");
217 return -1;
218 }
219 }
220
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100221 /* clear MII interrupt bit */
Marek Vasutbf2386b2011-09-11 18:05:34 +0000222 writel(FEC_IEVENT_MII, &eth->ievent);
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100223 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
224 regaddr, data);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400225
226 return 0;
227}
228
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100229static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr,
230 int regaddr)
Troy Kisky2000c662012-02-07 14:08:47 +0000231{
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100232 return fec_mdio_read(bus->priv, phyaddr, regaddr);
Troy Kisky2000c662012-02-07 14:08:47 +0000233}
234
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100235static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr,
236 int regaddr, u16 data)
Troy Kisky2000c662012-02-07 14:08:47 +0000237{
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100238 return fec_mdio_write(bus->priv, phyaddr, regaddr, data);
Troy Kisky2000c662012-02-07 14:08:47 +0000239}
240
241#ifndef CONFIG_PHYLIB
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400242static int miiphy_restart_aneg(struct eth_device *dev)
243{
Stefano Babicd6228172012-02-22 00:24:35 +0000244 int ret = 0;
245#if !defined(CONFIG_FEC_MXC_NO_ANEG)
Marek Vasutedcd6c02011-09-16 01:13:47 +0200246 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Troy Kisky2000c662012-02-07 14:08:47 +0000247 struct ethernet_regs *eth = fec->bus->priv;
Marek Vasutedcd6c02011-09-16 01:13:47 +0200248
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400249 /*
250 * Wake up from sleep if necessary
251 * Reset PHY, then delay 300ns
252 */
John Rigbye650e492010-01-25 23:12:55 -0700253#ifdef CONFIG_MX27
Troy Kisky2000c662012-02-07 14:08:47 +0000254 fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
John Rigbye650e492010-01-25 23:12:55 -0700255#endif
Troy Kisky2000c662012-02-07 14:08:47 +0000256 fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400257 udelay(1000);
258
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100259 /* Set the auto-negotiation advertisement register bits */
Troy Kisky2000c662012-02-07 14:08:47 +0000260 fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100261 LPA_100FULL | LPA_100HALF | LPA_10FULL |
262 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
Troy Kisky2000c662012-02-07 14:08:47 +0000263 fec_mdio_write(eth, fec->phy_id, MII_BMCR,
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100264 BMCR_ANENABLE | BMCR_ANRESTART);
Marek Vasut539ecee2011-09-11 18:05:36 +0000265
266 if (fec->mii_postcall)
267 ret = fec->mii_postcall(fec->phy_id);
268
Stefano Babicd6228172012-02-22 00:24:35 +0000269#endif
Marek Vasut539ecee2011-09-11 18:05:36 +0000270 return ret;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400271}
272
Hannes Schmelzer5a15c1a2016-06-22 12:07:14 +0200273#ifndef CONFIG_FEC_FIXED_SPEED
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400274static int miiphy_wait_aneg(struct eth_device *dev)
275{
276 uint32_t start;
Troy Kisky2000c662012-02-07 14:08:47 +0000277 int status;
Marek Vasutedcd6c02011-09-16 01:13:47 +0200278 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Troy Kisky2000c662012-02-07 14:08:47 +0000279 struct ethernet_regs *eth = fec->bus->priv;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400280
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100281 /* Wait for AN completion */
Graeme Russf8b82ee2011-07-15 23:31:37 +0000282 start = get_timer(0);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400283 do {
284 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
285 printf("%s: Autonegotiation timeout\n", dev->name);
286 return -1;
287 }
288
Troy Kisky2000c662012-02-07 14:08:47 +0000289 status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
290 if (status < 0) {
291 printf("%s: Autonegotiation failed. status: %d\n",
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100292 dev->name, status);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400293 return -1;
294 }
Mike Frysingerd63ee712010-12-23 15:40:12 -0500295 } while (!(status & BMSR_LSTATUS));
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400296
297 return 0;
298}
Hannes Schmelzer5a15c1a2016-06-22 12:07:14 +0200299#endif /* CONFIG_FEC_FIXED_SPEED */
Troy Kisky2000c662012-02-07 14:08:47 +0000300#endif
301
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400302static int fec_rx_task_enable(struct fec_priv *fec)
303{
Marek Vasutc1582c02012-08-29 03:49:51 +0000304 writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400305 return 0;
306}
307
308static int fec_rx_task_disable(struct fec_priv *fec)
309{
310 return 0;
311}
312
313static int fec_tx_task_enable(struct fec_priv *fec)
314{
Marek Vasutc1582c02012-08-29 03:49:51 +0000315 writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400316 return 0;
317}
318
319static int fec_tx_task_disable(struct fec_priv *fec)
320{
321 return 0;
322}
323
324/**
325 * Initialize receive task's buffer descriptors
326 * @param[in] fec all we know about the device yet
327 * @param[in] count receive buffer count to be allocated
Eric Nelson3d2f7272012-03-15 18:33:25 +0000328 * @param[in] dsize desired size of each receive buffer
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400329 * @return 0 on success
330 *
Marek Vasut03880452013-10-12 20:36:25 +0200331 * Init all RX descriptors to default values.
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400332 */
Marek Vasut03880452013-10-12 20:36:25 +0200333static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400334{
Eric Nelson3d2f7272012-03-15 18:33:25 +0000335 uint32_t size;
Ye Lie2670912018-01-10 13:20:44 +0800336 ulong data;
Eric Nelson3d2f7272012-03-15 18:33:25 +0000337 int i;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400338
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400339 /*
Marek Vasut03880452013-10-12 20:36:25 +0200340 * Reload the RX descriptors with default values and wipe
341 * the RX buffers.
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400342 */
Eric Nelson3d2f7272012-03-15 18:33:25 +0000343 size = roundup(dsize, ARCH_DMA_MINALIGN);
344 for (i = 0; i < count; i++) {
Ye Lie2670912018-01-10 13:20:44 +0800345 data = fec->rbd_base[i].data_pointer;
346 memset((void *)data, 0, dsize);
347 flush_dcache_range(data, data + size);
Marek Vasut03880452013-10-12 20:36:25 +0200348
349 fec->rbd_base[i].status = FEC_RBD_EMPTY;
350 fec->rbd_base[i].data_length = 0;
Eric Nelson3d2f7272012-03-15 18:33:25 +0000351 }
352
353 /* Mark the last RBD to close the ring. */
Marek Vasut03880452013-10-12 20:36:25 +0200354 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400355 fec->rbd_index = 0;
356
Ye Lie2670912018-01-10 13:20:44 +0800357 flush_dcache_range((ulong)fec->rbd_base,
358 (ulong)fec->rbd_base + size);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400359}
360
361/**
362 * Initialize transmit task's buffer descriptors
363 * @param[in] fec all we know about the device yet
364 *
365 * Transmit buffers are created externally. We only have to init the BDs here.\n
366 * Note: There is a race condition in the hardware. When only one BD is in
367 * use it must be marked with the WRAP bit to use it for every transmitt.
368 * This bit in combination with the READY bit results into double transmit
369 * of each data buffer. It seems the state machine checks READY earlier then
370 * resetting it after the first transfer.
371 * Using two BDs solves this issue.
372 */
373static void fec_tbd_init(struct fec_priv *fec)
374{
Ye Lie2670912018-01-10 13:20:44 +0800375 ulong addr = (ulong)fec->tbd_base;
Eric Nelson3d2f7272012-03-15 18:33:25 +0000376 unsigned size = roundup(2 * sizeof(struct fec_bd),
377 ARCH_DMA_MINALIGN);
Marek Vasut03880452013-10-12 20:36:25 +0200378
379 memset(fec->tbd_base, 0, size);
380 fec->tbd_base[0].status = 0;
381 fec->tbd_base[1].status = FEC_TBD_WRAP;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400382 fec->tbd_index = 0;
Marek Vasut03880452013-10-12 20:36:25 +0200383 flush_dcache_range(addr, addr + size);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400384}
385
386/**
387 * Mark the given read buffer descriptor as free
388 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100389 * @param[in] prbd buffer descriptor to mark free again
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400390 */
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100391static void fec_rbd_clean(int last, struct fec_bd *prbd)
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400392{
Eric Nelson3d2f7272012-03-15 18:33:25 +0000393 unsigned short flags = FEC_RBD_EMPTY;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400394 if (last)
Eric Nelson3d2f7272012-03-15 18:33:25 +0000395 flags |= FEC_RBD_WRAP;
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100396 writew(flags, &prbd->status);
397 writew(0, &prbd->data_length);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400398}
399
Jagan Tekibc5fb462016-12-06 00:00:48 +0100400static int fec_get_hwaddr(int dev_id, unsigned char *mac)
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400401{
Fabio Estevam04fc1282011-12-20 05:46:31 +0000402 imx_get_mac_from_fuse(dev_id, mac);
Joe Hershberger8ecdbed2015-04-08 01:41:04 -0500403 return !is_valid_ethaddr(mac);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400404}
405
Jagan Teki484f0212016-12-06 00:00:49 +0100406#ifdef CONFIG_DM_ETH
407static int fecmxc_set_hwaddr(struct udevice *dev)
408#else
Stefano Babic889f2e22010-02-01 14:51:30 +0100409static int fec_set_hwaddr(struct eth_device *dev)
Jagan Teki484f0212016-12-06 00:00:49 +0100410#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400411{
Jagan Teki484f0212016-12-06 00:00:49 +0100412#ifdef CONFIG_DM_ETH
413 struct fec_priv *fec = dev_get_priv(dev);
414 struct eth_pdata *pdata = dev_get_platdata(dev);
415 uchar *mac = pdata->enetaddr;
416#else
Stefano Babic889f2e22010-02-01 14:51:30 +0100417 uchar *mac = dev->enetaddr;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400418 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Jagan Teki484f0212016-12-06 00:00:49 +0100419#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400420
421 writel(0, &fec->eth->iaddr1);
422 writel(0, &fec->eth->iaddr2);
423 writel(0, &fec->eth->gaddr1);
424 writel(0, &fec->eth->gaddr2);
425
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100426 /* Set physical address */
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400427 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100428 &fec->eth->paddr1);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400429 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
430
431 return 0;
432}
433
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100434/* Do initial configuration of the FEC registers */
Marek Vasut335cbd22012-05-01 11:09:41 +0000435static void fec_reg_setup(struct fec_priv *fec)
436{
437 uint32_t rcntrl;
438
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100439 /* Set interrupt mask register */
Marek Vasut335cbd22012-05-01 11:09:41 +0000440 writel(0x00000000, &fec->eth->imask);
441
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100442 /* Clear FEC-Lite interrupt event register(IEVENT) */
Marek Vasut335cbd22012-05-01 11:09:41 +0000443 writel(0xffffffff, &fec->eth->ievent);
444
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100445 /* Set FEC-Lite receive control register(R_CNTRL): */
Marek Vasut335cbd22012-05-01 11:09:41 +0000446
447 /* Start with frame length = 1518, common for all modes. */
448 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
benoit.thebaudeau@advansacc7a282012-07-19 02:12:46 +0000449 if (fec->xcv_type != SEVENWIRE) /* xMII modes */
450 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
451 if (fec->xcv_type == RGMII)
Marek Vasut335cbd22012-05-01 11:09:41 +0000452 rcntrl |= FEC_RCNTRL_RGMII;
453 else if (fec->xcv_type == RMII)
454 rcntrl |= FEC_RCNTRL_RMII;
Marek Vasut335cbd22012-05-01 11:09:41 +0000455
456 writel(rcntrl, &fec->eth->r_cntrl);
457}
458
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400459/**
460 * Start the FEC engine
461 * @param[in] dev Our device to handle
462 */
Jagan Teki484f0212016-12-06 00:00:49 +0100463#ifdef CONFIG_DM_ETH
464static int fec_open(struct udevice *dev)
465#else
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400466static int fec_open(struct eth_device *edev)
Jagan Teki484f0212016-12-06 00:00:49 +0100467#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400468{
Jagan Teki484f0212016-12-06 00:00:49 +0100469#ifdef CONFIG_DM_ETH
470 struct fec_priv *fec = dev_get_priv(dev);
471#else
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400472 struct fec_priv *fec = (struct fec_priv *)edev->priv;
Jagan Teki484f0212016-12-06 00:00:49 +0100473#endif
Troy Kisky01112132012-02-07 14:08:46 +0000474 int speed;
Ye Lie2670912018-01-10 13:20:44 +0800475 ulong addr, size;
Eric Nelson3d2f7272012-03-15 18:33:25 +0000476 int i;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400477
478 debug("fec_open: fec_open(dev)\n");
479 /* full-duplex, heartbeat disabled */
480 writel(1 << 2, &fec->eth->x_cntrl);
481 fec->rbd_index = 0;
482
Eric Nelson3d2f7272012-03-15 18:33:25 +0000483 /* Invalidate all descriptors */
484 for (i = 0; i < FEC_RBD_NUM - 1; i++)
485 fec_rbd_clean(0, &fec->rbd_base[i]);
486 fec_rbd_clean(1, &fec->rbd_base[i]);
487
488 /* Flush the descriptors into RAM */
489 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
490 ARCH_DMA_MINALIGN);
Ye Lie2670912018-01-10 13:20:44 +0800491 addr = (ulong)fec->rbd_base;
Eric Nelson3d2f7272012-03-15 18:33:25 +0000492 flush_dcache_range(addr, addr + size);
493
Troy Kisky01112132012-02-07 14:08:46 +0000494#ifdef FEC_QUIRK_ENET_MAC
Jason Liubbcef6c2011-12-16 05:17:07 +0000495 /* Enable ENET HW endian SWAP */
496 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100497 &fec->eth->ecntrl);
Jason Liubbcef6c2011-12-16 05:17:07 +0000498 /* Enable ENET store and forward mode */
499 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100500 &fec->eth->x_wmrk);
Jason Liubbcef6c2011-12-16 05:17:07 +0000501#endif
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100502 /* Enable FEC-Lite controller */
John Rigbye650e492010-01-25 23:12:55 -0700503 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100504 &fec->eth->ecntrl);
505
Fabio Estevam84c1f522013-09-13 00:36:27 -0300506#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
John Rigby99d5fed2010-01-25 23:12:57 -0700507 udelay(100);
John Rigby99d5fed2010-01-25 23:12:57 -0700508
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100509 /* setup the MII gasket for RMII mode */
John Rigby99d5fed2010-01-25 23:12:57 -0700510 /* disable the gasket */
511 writew(0, &fec->eth->miigsk_enr);
512
513 /* wait for the gasket to be disabled */
514 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
515 udelay(2);
516
517 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
518 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
519
520 /* re-enable the gasket */
521 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
522
523 /* wait until MII gasket is ready */
524 int max_loops = 10;
525 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
526 if (--max_loops <= 0) {
527 printf("WAIT for MII Gasket ready timed out\n");
528 break;
529 }
530 }
531#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400532
Troy Kisky2000c662012-02-07 14:08:47 +0000533#ifdef CONFIG_PHYLIB
Troy Kisky2c42b3c2012-10-22 16:40:45 +0000534 {
Troy Kisky2000c662012-02-07 14:08:47 +0000535 /* Start up the PHY */
Timur Tabi42387462012-07-09 08:52:43 +0000536 int ret = phy_startup(fec->phydev);
537
538 if (ret) {
539 printf("Could not initialize PHY %s\n",
540 fec->phydev->dev->name);
541 return ret;
542 }
Troy Kisky2000c662012-02-07 14:08:47 +0000543 speed = fec->phydev->speed;
Troy Kisky2000c662012-02-07 14:08:47 +0000544 }
Hannes Schmelzer5a15c1a2016-06-22 12:07:14 +0200545#elif CONFIG_FEC_FIXED_SPEED
546 speed = CONFIG_FEC_FIXED_SPEED;
Troy Kisky2000c662012-02-07 14:08:47 +0000547#else
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400548 miiphy_wait_aneg(edev);
Troy Kisky01112132012-02-07 14:08:46 +0000549 speed = miiphy_speed(edev->name, fec->phy_id);
Marek Vasutedcd6c02011-09-16 01:13:47 +0200550 miiphy_duplex(edev->name, fec->phy_id);
Troy Kisky2000c662012-02-07 14:08:47 +0000551#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400552
Troy Kisky01112132012-02-07 14:08:46 +0000553#ifdef FEC_QUIRK_ENET_MAC
554 {
555 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
Alison Wang89d932a2013-05-27 22:55:43 +0000556 u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
Troy Kisky01112132012-02-07 14:08:46 +0000557 if (speed == _1000BASET)
558 ecr |= FEC_ECNTRL_SPEED;
559 else if (speed != _100BASET)
560 rcr |= FEC_RCNTRL_RMII_10T;
561 writel(ecr, &fec->eth->ecntrl);
562 writel(rcr, &fec->eth->r_cntrl);
563 }
564#endif
565 debug("%s:Speed=%i\n", __func__, speed);
566
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100567 /* Enable SmartDMA receive task */
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400568 fec_rx_task_enable(fec);
569
570 udelay(100000);
571 return 0;
572}
573
Jagan Teki484f0212016-12-06 00:00:49 +0100574#ifdef CONFIG_DM_ETH
575static int fecmxc_init(struct udevice *dev)
576#else
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100577static int fec_init(struct eth_device *dev, bd_t *bd)
Jagan Teki484f0212016-12-06 00:00:49 +0100578#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400579{
Jagan Teki484f0212016-12-06 00:00:49 +0100580#ifdef CONFIG_DM_ETH
581 struct fec_priv *fec = dev_get_priv(dev);
582#else
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400583 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Jagan Teki484f0212016-12-06 00:00:49 +0100584#endif
Ye Lie2670912018-01-10 13:20:44 +0800585 u8 *mib_ptr = (uint8_t *)&fec->eth->rmon_t_drop;
586 u8 *i;
587 ulong addr;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400588
John Rigbya4a30552010-10-13 14:31:08 -0600589 /* Initialize MAC address */
Jagan Teki484f0212016-12-06 00:00:49 +0100590#ifdef CONFIG_DM_ETH
591 fecmxc_set_hwaddr(dev);
592#else
John Rigbya4a30552010-10-13 14:31:08 -0600593 fec_set_hwaddr(dev);
Jagan Teki484f0212016-12-06 00:00:49 +0100594#endif
John Rigbya4a30552010-10-13 14:31:08 -0600595
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100596 /* Setup transmit descriptors, there are two in total. */
Marek Vasut03880452013-10-12 20:36:25 +0200597 fec_tbd_init(fec);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400598
Marek Vasut03880452013-10-12 20:36:25 +0200599 /* Setup receive descriptors. */
600 fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400601
Marek Vasut335cbd22012-05-01 11:09:41 +0000602 fec_reg_setup(fec);
Marek Vasutb8f88562011-09-11 18:05:31 +0000603
benoit.thebaudeau@advans551bb362012-07-19 02:12:58 +0000604 if (fec->xcv_type != SEVENWIRE)
Troy Kisky5e762652012-10-22 16:40:41 +0000605 fec_mii_setspeed(fec->bus->priv);
Marek Vasutb8f88562011-09-11 18:05:31 +0000606
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100607 /* Set Opcode/Pause Duration Register */
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400608 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
609 writel(0x2, &fec->eth->x_wmrk);
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100610
611 /* Set multicast address filter */
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400612 writel(0x00000000, &fec->eth->gaddr1);
613 writel(0x00000000, &fec->eth->gaddr2);
614
Peng Fanbf8e58b2018-01-10 13:20:43 +0800615 /* Do not access reserved register */
Peng Fan6146a082019-04-15 05:18:33 +0000616 if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m()) {
Peng Fan13433fd2015-08-12 17:46:51 +0800617 /* clear MIB RAM */
618 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
619 writel(0, i);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400620
Peng Fan13433fd2015-08-12 17:46:51 +0800621 /* FIFO receive start register */
622 writel(0x520, &fec->eth->r_fstart);
623 }
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400624
625 /* size and address of each buffer */
626 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
Ye Lie2670912018-01-10 13:20:44 +0800627
628 addr = (ulong)fec->tbd_base;
629 writel((uint32_t)addr, &fec->eth->etdsr);
630
631 addr = (ulong)fec->rbd_base;
632 writel((uint32_t)addr, &fec->eth->erdsr);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400633
Troy Kisky2000c662012-02-07 14:08:47 +0000634#ifndef CONFIG_PHYLIB
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400635 if (fec->xcv_type != SEVENWIRE)
636 miiphy_restart_aneg(dev);
Troy Kisky2000c662012-02-07 14:08:47 +0000637#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400638 fec_open(dev);
639 return 0;
640}
641
642/**
643 * Halt the FEC engine
644 * @param[in] dev Our device to handle
645 */
Jagan Teki484f0212016-12-06 00:00:49 +0100646#ifdef CONFIG_DM_ETH
647static void fecmxc_halt(struct udevice *dev)
648#else
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400649static void fec_halt(struct eth_device *dev)
Jagan Teki484f0212016-12-06 00:00:49 +0100650#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400651{
Jagan Teki484f0212016-12-06 00:00:49 +0100652#ifdef CONFIG_DM_ETH
653 struct fec_priv *fec = dev_get_priv(dev);
654#else
Marek Vasutedcd6c02011-09-16 01:13:47 +0200655 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Jagan Teki484f0212016-12-06 00:00:49 +0100656#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400657 int counter = 0xffff;
658
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100659 /* issue graceful stop command to the FEC transmitter if necessary */
John Rigbye650e492010-01-25 23:12:55 -0700660 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100661 &fec->eth->x_cntrl);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400662
663 debug("eth_halt: wait for stop regs\n");
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100664 /* wait for graceful stop to register */
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400665 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
John Rigbye650e492010-01-25 23:12:55 -0700666 udelay(1);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400667
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100668 /* Disable SmartDMA tasks */
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400669 fec_tx_task_disable(fec);
670 fec_rx_task_disable(fec);
671
672 /*
673 * Disable the Ethernet Controller
674 * Note: this will also reset the BD index counter!
675 */
John Rigby99d5fed2010-01-25 23:12:57 -0700676 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100677 &fec->eth->ecntrl);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400678 fec->rbd_index = 0;
679 fec->tbd_index = 0;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400680 debug("eth_halt: done\n");
681}
682
683/**
684 * Transmit one frame
685 * @param[in] dev Our ethernet device to handle
686 * @param[in] packet Pointer to the data to be transmitted
687 * @param[in] length Data count in bytes
688 * @return 0 on success
689 */
Jagan Teki484f0212016-12-06 00:00:49 +0100690#ifdef CONFIG_DM_ETH
691static int fecmxc_send(struct udevice *dev, void *packet, int length)
692#else
Joe Hershberger7c31bd12012-05-21 14:45:27 +0000693static int fec_send(struct eth_device *dev, void *packet, int length)
Jagan Teki484f0212016-12-06 00:00:49 +0100694#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400695{
696 unsigned int status;
Ye Lie2670912018-01-10 13:20:44 +0800697 u32 size;
698 ulong addr, end;
Marek Vasut5f1631d2012-08-29 03:49:49 +0000699 int timeout = FEC_XFER_TIMEOUT;
700 int ret = 0;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400701
702 /*
703 * This routine transmits one frame. This routine only accepts
704 * 6-byte Ethernet addresses.
705 */
Jagan Teki484f0212016-12-06 00:00:49 +0100706#ifdef CONFIG_DM_ETH
707 struct fec_priv *fec = dev_get_priv(dev);
708#else
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400709 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Jagan Teki484f0212016-12-06 00:00:49 +0100710#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400711
712 /*
713 * Check for valid length of data.
714 */
715 if ((length > 1500) || (length <= 0)) {
Stefano Babic889f2e22010-02-01 14:51:30 +0100716 printf("Payload (%d) too large\n", length);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400717 return -1;
718 }
719
720 /*
Eric Nelson3d2f7272012-03-15 18:33:25 +0000721 * Setup the transmit buffer. We are always using the first buffer for
722 * transmission, the second will be empty and only used to stop the DMA
723 * engine. We also flush the packet to RAM here to avoid cache trouble.
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400724 */
Eric Nelson3d2f7272012-03-15 18:33:25 +0000725#ifdef CONFIG_FEC_MXC_SWAP_PACKET
Marek Vasut6a5fd4c2011-11-08 23:18:10 +0000726 swap_packet((uint32_t *)packet, length);
727#endif
Eric Nelson3d2f7272012-03-15 18:33:25 +0000728
Ye Lie2670912018-01-10 13:20:44 +0800729 addr = (ulong)packet;
Marek Vasut4325d242012-08-26 10:19:21 +0000730 end = roundup(addr + length, ARCH_DMA_MINALIGN);
731 addr &= ~(ARCH_DMA_MINALIGN - 1);
732 flush_dcache_range(addr, end);
Eric Nelson3d2f7272012-03-15 18:33:25 +0000733
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400734 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
Ye Lie2670912018-01-10 13:20:44 +0800735 writel((uint32_t)addr, &fec->tbd_base[fec->tbd_index].data_pointer);
Eric Nelson3d2f7272012-03-15 18:33:25 +0000736
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400737 /*
738 * update BD's status now
739 * This block:
740 * - is always the last in a chain (means no chain)
741 * - should transmitt the CRC
742 * - might be the last BD in the list, so the address counter should
743 * wrap (-> keep the WRAP flag)
744 */
745 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
746 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
747 writew(status, &fec->tbd_base[fec->tbd_index].status);
748
749 /*
Eric Nelson3d2f7272012-03-15 18:33:25 +0000750 * Flush data cache. This code flushes both TX descriptors to RAM.
751 * After this code, the descriptors will be safely in RAM and we
752 * can start DMA.
753 */
754 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
Ye Lie2670912018-01-10 13:20:44 +0800755 addr = (ulong)fec->tbd_base;
Eric Nelson3d2f7272012-03-15 18:33:25 +0000756 flush_dcache_range(addr, addr + size);
757
758 /*
Marek Vasutd521b3c2013-07-12 01:03:04 +0200759 * Below we read the DMA descriptor's last four bytes back from the
760 * DRAM. This is important in order to make sure that all WRITE
761 * operations on the bus that were triggered by previous cache FLUSH
762 * have completed.
763 *
764 * Otherwise, on MX28, it is possible to observe a corruption of the
765 * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
766 * for the bus structure of MX28. The scenario is as follows:
767 *
768 * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
769 * to DRAM due to flush_dcache_range()
770 * 2) ARM core writes the FEC registers via AHB_ARB2
771 * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
772 *
773 * Note that 2) does sometimes finish before 1) due to reordering of
774 * WRITE accesses on the AHB bus, therefore triggering 3) before the
775 * DMA descriptor is fully written into DRAM. This results in occasional
776 * corruption of the DMA descriptor.
777 */
778 readl(addr + size - 4);
779
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100780 /* Enable SmartDMA transmit task */
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400781 fec_tx_task_enable(fec);
782
783 /*
Eric Nelson3d2f7272012-03-15 18:33:25 +0000784 * Wait until frame is sent. On each turn of the wait cycle, we must
785 * invalidate data cache to see what's really in RAM. Also, we need
786 * barrier here.
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400787 */
Marek Vasut9bf7bf02012-08-29 03:49:50 +0000788 while (--timeout) {
Marek Vasutc1582c02012-08-29 03:49:51 +0000789 if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
Marek Vasut5f1631d2012-08-29 03:49:49 +0000790 break;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400791 }
Eric Nelson3d2f7272012-03-15 18:33:25 +0000792
Fabio Estevamc34e99f2014-08-25 13:34:17 -0300793 if (!timeout) {
Marek Vasut9bf7bf02012-08-29 03:49:50 +0000794 ret = -EINVAL;
Fabio Estevamc34e99f2014-08-25 13:34:17 -0300795 goto out;
796 }
Marek Vasut9bf7bf02012-08-29 03:49:50 +0000797
Fabio Estevamc34e99f2014-08-25 13:34:17 -0300798 /*
799 * The TDAR bit is cleared when the descriptors are all out from TX
800 * but on mx6solox we noticed that the READY bit is still not cleared
801 * right after TDAR.
802 * These are two distinct signals, and in IC simulation, we found that
803 * TDAR always gets cleared prior than the READY bit of last BD becomes
804 * cleared.
805 * In mx6solox, we use a later version of FEC IP. It looks like that
806 * this intrinsic behaviour of TDAR bit has changed in this newer FEC
807 * version.
808 *
809 * Fix this by polling the READY bit of BD after the TDAR polling,
810 * which covers the mx6solox case and does not harm the other SoCs.
811 */
812 timeout = FEC_XFER_TIMEOUT;
813 while (--timeout) {
814 invalidate_dcache_range(addr, addr + size);
815 if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
816 FEC_TBD_READY))
817 break;
818 }
819
820 if (!timeout)
Marek Vasut9bf7bf02012-08-29 03:49:50 +0000821 ret = -EINVAL;
822
Fabio Estevamc34e99f2014-08-25 13:34:17 -0300823out:
Marek Vasut9bf7bf02012-08-29 03:49:50 +0000824 debug("fec_send: status 0x%x index %d ret %i\n",
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100825 readw(&fec->tbd_base[fec->tbd_index].status),
826 fec->tbd_index, ret);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400827 /* for next transmission use the other buffer */
828 if (fec->tbd_index)
829 fec->tbd_index = 0;
830 else
831 fec->tbd_index = 1;
832
Marek Vasut5f1631d2012-08-29 03:49:49 +0000833 return ret;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400834}
835
836/**
837 * Pull one frame from the card
838 * @param[in] dev Our ethernet device to handle
839 * @return Length of packet read
840 */
Jagan Teki484f0212016-12-06 00:00:49 +0100841#ifdef CONFIG_DM_ETH
842static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp)
843#else
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400844static int fec_recv(struct eth_device *dev)
Jagan Teki484f0212016-12-06 00:00:49 +0100845#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400846{
Jagan Teki484f0212016-12-06 00:00:49 +0100847#ifdef CONFIG_DM_ETH
848 struct fec_priv *fec = dev_get_priv(dev);
849#else
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400850 struct fec_priv *fec = (struct fec_priv *)dev->priv;
Jagan Teki484f0212016-12-06 00:00:49 +0100851#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400852 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
853 unsigned long ievent;
854 int frame_length, len = 0;
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400855 uint16_t bd_status;
Ye Lie2670912018-01-10 13:20:44 +0800856 ulong addr, size, end;
Eric Nelson3d2f7272012-03-15 18:33:25 +0000857 int i;
Ye Libd7e5382018-03-28 20:54:11 +0800858
859#ifdef CONFIG_DM_ETH
860 *packetp = memalign(ARCH_DMA_MINALIGN, FEC_MAX_PKT_SIZE);
861 if (*packetp == 0) {
862 printf("%s: error allocating packetp\n", __func__);
863 return -ENOMEM;
864 }
865#else
Fabio Estevamcc956082013-09-17 23:13:10 -0300866 ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
Ye Libd7e5382018-03-28 20:54:11 +0800867#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400868
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100869 /* Check if any critical events have happened */
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400870 ievent = readl(&fec->eth->ievent);
871 writel(ievent, &fec->eth->ievent);
Marek Vasut478e2d02011-10-24 23:40:03 +0000872 debug("fec_recv: ievent 0x%lx\n", ievent);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400873 if (ievent & FEC_IEVENT_BABR) {
Jagan Teki484f0212016-12-06 00:00:49 +0100874#ifdef CONFIG_DM_ETH
875 fecmxc_halt(dev);
876 fecmxc_init(dev);
877#else
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400878 fec_halt(dev);
879 fec_init(dev, fec->bd);
Jagan Teki484f0212016-12-06 00:00:49 +0100880#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400881 printf("some error: 0x%08lx\n", ievent);
882 return 0;
883 }
884 if (ievent & FEC_IEVENT_HBERR) {
885 /* Heartbeat error */
886 writel(0x00000001 | readl(&fec->eth->x_cntrl),
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100887 &fec->eth->x_cntrl);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400888 }
889 if (ievent & FEC_IEVENT_GRA) {
890 /* Graceful stop complete */
891 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
Jagan Teki484f0212016-12-06 00:00:49 +0100892#ifdef CONFIG_DM_ETH
893 fecmxc_halt(dev);
894#else
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400895 fec_halt(dev);
Jagan Teki484f0212016-12-06 00:00:49 +0100896#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400897 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100898 &fec->eth->x_cntrl);
Jagan Teki484f0212016-12-06 00:00:49 +0100899#ifdef CONFIG_DM_ETH
900 fecmxc_init(dev);
901#else
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400902 fec_init(dev, fec->bd);
Jagan Teki484f0212016-12-06 00:00:49 +0100903#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400904 }
905 }
906
907 /*
Eric Nelson3d2f7272012-03-15 18:33:25 +0000908 * Read the buffer status. Before the status can be read, the data cache
909 * must be invalidated, because the data in RAM might have been changed
910 * by DMA. The descriptors are properly aligned to cachelines so there's
911 * no need to worry they'd overlap.
912 *
913 * WARNING: By invalidating the descriptor here, we also invalidate
914 * the descriptors surrounding this one. Therefore we can NOT change the
915 * contents of this descriptor nor the surrounding ones. The problem is
916 * that in order to mark the descriptor as processed, we need to change
917 * the descriptor. The solution is to mark the whole cache line when all
918 * descriptors in the cache line are processed.
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400919 */
Ye Lie2670912018-01-10 13:20:44 +0800920 addr = (ulong)rbd;
Eric Nelson3d2f7272012-03-15 18:33:25 +0000921 addr &= ~(ARCH_DMA_MINALIGN - 1);
922 size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
923 invalidate_dcache_range(addr, addr + size);
924
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400925 bd_status = readw(&rbd->status);
926 debug("fec_recv: status 0x%x\n", bd_status);
927
928 if (!(bd_status & FEC_RBD_EMPTY)) {
929 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100930 ((readw(&rbd->data_length) - 4) > 14)) {
931 /* Get buffer address and size */
Albert ARIBAUD \(3ADEV\)13420302015-06-19 14:18:27 +0200932 addr = readl(&rbd->data_pointer);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400933 frame_length = readw(&rbd->data_length) - 4;
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100934 /* Invalidate data cache over the buffer */
Marek Vasut4325d242012-08-26 10:19:21 +0000935 end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
936 addr &= ~(ARCH_DMA_MINALIGN - 1);
937 invalidate_dcache_range(addr, end);
Eric Nelson3d2f7272012-03-15 18:33:25 +0000938
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100939 /* Fill the buffer and pass it to upper layers */
Eric Nelson3d2f7272012-03-15 18:33:25 +0000940#ifdef CONFIG_FEC_MXC_SWAP_PACKET
Albert ARIBAUD \(3ADEV\)13420302015-06-19 14:18:27 +0200941 swap_packet((uint32_t *)addr, frame_length);
Marek Vasut6a5fd4c2011-11-08 23:18:10 +0000942#endif
Ye Libd7e5382018-03-28 20:54:11 +0800943
944#ifdef CONFIG_DM_ETH
945 memcpy(*packetp, (char *)addr, frame_length);
946#else
Albert ARIBAUD \(3ADEV\)13420302015-06-19 14:18:27 +0200947 memcpy(buff, (char *)addr, frame_length);
Joe Hershberger9f09a362015-04-08 01:41:06 -0500948 net_process_received_packet(buff, frame_length);
Ye Libd7e5382018-03-28 20:54:11 +0800949#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400950 len = frame_length;
951 } else {
952 if (bd_status & FEC_RBD_ERR)
Ye Lie2670912018-01-10 13:20:44 +0800953 debug("error frame: 0x%08lx 0x%08x\n",
954 addr, bd_status);
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400955 }
Eric Nelson3d2f7272012-03-15 18:33:25 +0000956
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400957 /*
Eric Nelson3d2f7272012-03-15 18:33:25 +0000958 * Free the current buffer, restart the engine and move forward
959 * to the next buffer. Here we check if the whole cacheline of
960 * descriptors was already processed and if so, we mark it free
961 * as whole.
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400962 */
Eric Nelson3d2f7272012-03-15 18:33:25 +0000963 size = RXDESC_PER_CACHELINE - 1;
964 if ((fec->rbd_index & size) == size) {
965 i = fec->rbd_index - size;
Ye Lie2670912018-01-10 13:20:44 +0800966 addr = (ulong)&fec->rbd_base[i];
Eric Nelson3d2f7272012-03-15 18:33:25 +0000967 for (; i <= fec->rbd_index ; i++) {
968 fec_rbd_clean(i == (FEC_RBD_NUM - 1),
969 &fec->rbd_base[i]);
970 }
971 flush_dcache_range(addr,
Jagan Tekic6cd8d52016-12-06 00:00:50 +0100972 addr + ARCH_DMA_MINALIGN);
Eric Nelson3d2f7272012-03-15 18:33:25 +0000973 }
974
Ilya Yanoke93a4a52009-07-21 19:32:21 +0400975 fec_rx_task_enable(fec);
976 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
977 }
978 debug("fec_recv: stop\n");
979
980 return len;
981}
982
Troy Kisky4c2ddec2012-10-22 16:40:44 +0000983static void fec_set_dev_name(char *dest, int dev_id)
984{
985 sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
986}
987
Marek Vasut03880452013-10-12 20:36:25 +0200988static int fec_alloc_descs(struct fec_priv *fec)
989{
990 unsigned int size;
991 int i;
992 uint8_t *data;
Ye Lie2670912018-01-10 13:20:44 +0800993 ulong addr;
Marek Vasut03880452013-10-12 20:36:25 +0200994
995 /* Allocate TX descriptors. */
996 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
997 fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
998 if (!fec->tbd_base)
999 goto err_tx;
1000
1001 /* Allocate RX descriptors. */
1002 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
1003 fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
1004 if (!fec->rbd_base)
1005 goto err_rx;
1006
1007 memset(fec->rbd_base, 0, size);
1008
1009 /* Allocate RX buffers. */
1010
1011 /* Maximum RX buffer size. */
Fabio Estevam8b798b22014-08-25 13:34:16 -03001012 size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
Marek Vasut03880452013-10-12 20:36:25 +02001013 for (i = 0; i < FEC_RBD_NUM; i++) {
Fabio Estevam8b798b22014-08-25 13:34:16 -03001014 data = memalign(FEC_DMA_RX_MINALIGN, size);
Marek Vasut03880452013-10-12 20:36:25 +02001015 if (!data) {
1016 printf("%s: error allocating rxbuf %d\n", __func__, i);
1017 goto err_ring;
1018 }
1019
1020 memset(data, 0, size);
1021
Ye Lie2670912018-01-10 13:20:44 +08001022 addr = (ulong)data;
1023 fec->rbd_base[i].data_pointer = (uint32_t)addr;
Marek Vasut03880452013-10-12 20:36:25 +02001024 fec->rbd_base[i].status = FEC_RBD_EMPTY;
1025 fec->rbd_base[i].data_length = 0;
1026 /* Flush the buffer to memory. */
Ye Lie2670912018-01-10 13:20:44 +08001027 flush_dcache_range(addr, addr + size);
Marek Vasut03880452013-10-12 20:36:25 +02001028 }
1029
1030 /* Mark the last RBD to close the ring. */
1031 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
1032
1033 fec->rbd_index = 0;
1034 fec->tbd_index = 0;
1035
1036 return 0;
1037
1038err_ring:
Ye Lie2670912018-01-10 13:20:44 +08001039 for (; i >= 0; i--) {
1040 addr = fec->rbd_base[i].data_pointer;
1041 free((void *)addr);
1042 }
Marek Vasut03880452013-10-12 20:36:25 +02001043 free(fec->rbd_base);
1044err_rx:
1045 free(fec->tbd_base);
1046err_tx:
1047 return -ENOMEM;
1048}
1049
1050static void fec_free_descs(struct fec_priv *fec)
1051{
1052 int i;
Ye Lie2670912018-01-10 13:20:44 +08001053 ulong addr;
Marek Vasut03880452013-10-12 20:36:25 +02001054
Ye Lie2670912018-01-10 13:20:44 +08001055 for (i = 0; i < FEC_RBD_NUM; i++) {
1056 addr = fec->rbd_base[i].data_pointer;
1057 free((void *)addr);
1058 }
Marek Vasut03880452013-10-12 20:36:25 +02001059 free(fec->rbd_base);
1060 free(fec->tbd_base);
1061}
1062
Peng Fan0c59c4f2018-03-28 20:54:12 +08001063struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id)
Jagan Teki484f0212016-12-06 00:00:49 +01001064{
Peng Fan0c59c4f2018-03-28 20:54:12 +08001065 struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
Jagan Teki484f0212016-12-06 00:00:49 +01001066 struct mii_dev *bus;
1067 int ret;
1068
1069 bus = mdio_alloc();
1070 if (!bus) {
1071 printf("mdio_alloc failed\n");
1072 return NULL;
1073 }
1074 bus->read = fec_phy_read;
1075 bus->write = fec_phy_write;
1076 bus->priv = eth;
1077 fec_set_dev_name(bus->name, dev_id);
1078
1079 ret = mdio_register(bus);
1080 if (ret) {
1081 printf("mdio_register failed\n");
1082 free(bus);
1083 return NULL;
1084 }
1085 fec_mii_setspeed(eth);
1086 return bus;
1087}
1088
1089#ifndef CONFIG_DM_ETH
Troy Kiskydce4def2012-10-22 16:40:46 +00001090#ifdef CONFIG_PHYLIB
1091int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
1092 struct mii_dev *bus, struct phy_device *phydev)
1093#else
1094static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
1095 struct mii_dev *bus, int phy_id)
1096#endif
Ilya Yanoke93a4a52009-07-21 19:32:21 +04001097{
Ilya Yanoke93a4a52009-07-21 19:32:21 +04001098 struct eth_device *edev;
Marek Vasutedcd6c02011-09-16 01:13:47 +02001099 struct fec_priv *fec;
Ilya Yanoke93a4a52009-07-21 19:32:21 +04001100 unsigned char ethaddr[6];
Andy Duan8f8e4582017-04-10 19:44:35 +08001101 char mac[16];
Marek Vasut43b10302011-09-11 18:05:37 +00001102 uint32_t start;
1103 int ret = 0;
Ilya Yanoke93a4a52009-07-21 19:32:21 +04001104
1105 /* create and fill edev struct */
1106 edev = (struct eth_device *)malloc(sizeof(struct eth_device));
1107 if (!edev) {
Marek Vasutedcd6c02011-09-16 01:13:47 +02001108 puts("fec_mxc: not enough malloc memory for eth_device\n");
Marek Vasut43b10302011-09-11 18:05:37 +00001109 ret = -ENOMEM;
1110 goto err1;
Marek Vasutedcd6c02011-09-16 01:13:47 +02001111 }
1112
1113 fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
1114 if (!fec) {
1115 puts("fec_mxc: not enough malloc memory for fec_priv\n");
Marek Vasut43b10302011-09-11 18:05:37 +00001116 ret = -ENOMEM;
1117 goto err2;
Ilya Yanoke93a4a52009-07-21 19:32:21 +04001118 }
Marek Vasutedcd6c02011-09-16 01:13:47 +02001119
Nobuhiro Iwamatsu1843c5b2010-10-19 14:03:42 +09001120 memset(edev, 0, sizeof(*edev));
Marek Vasutedcd6c02011-09-16 01:13:47 +02001121 memset(fec, 0, sizeof(*fec));
1122
Marek Vasut03880452013-10-12 20:36:25 +02001123 ret = fec_alloc_descs(fec);
1124 if (ret)
1125 goto err3;
1126
Ilya Yanoke93a4a52009-07-21 19:32:21 +04001127 edev->priv = fec;
1128 edev->init = fec_init;
1129 edev->send = fec_send;
1130 edev->recv = fec_recv;
1131 edev->halt = fec_halt;
Heiko Schocher9ada5e62010-04-27 07:43:52 +02001132 edev->write_hwaddr = fec_set_hwaddr;
Ilya Yanoke93a4a52009-07-21 19:32:21 +04001133
Ye Lie2670912018-01-10 13:20:44 +08001134 fec->eth = (struct ethernet_regs *)(ulong)base_addr;
Ilya Yanoke93a4a52009-07-21 19:32:21 +04001135 fec->bd = bd;
1136
Marek Vasutdbb4fce2011-09-11 18:05:33 +00001137 fec->xcv_type = CONFIG_FEC_XCV_TYPE;
Ilya Yanoke93a4a52009-07-21 19:32:21 +04001138
1139 /* Reset chip. */
John Rigbye650e492010-01-25 23:12:55 -07001140 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
Marek Vasut43b10302011-09-11 18:05:37 +00001141 start = get_timer(0);
1142 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
1143 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
Vagrant Cascadian259b1fb2016-10-23 20:45:19 -07001144 printf("FEC MXC: Timeout resetting chip\n");
Marek Vasut03880452013-10-12 20:36:25 +02001145 goto err4;
Marek Vasut43b10302011-09-11 18:05:37 +00001146 }
Ilya Yanoke93a4a52009-07-21 19:32:21 +04001147 udelay(10);
Marek Vasut43b10302011-09-11 18:05:37 +00001148 }
Ilya Yanoke93a4a52009-07-21 19:32:21 +04001149
Marek Vasut335cbd22012-05-01 11:09:41 +00001150 fec_reg_setup(fec);
Troy Kisky4c2ddec2012-10-22 16:40:44 +00001151 fec_set_dev_name(edev->name, dev_id);
1152 fec->dev_id = (dev_id == -1) ? 0 : dev_id;
Troy Kiskydce4def2012-10-22 16:40:46 +00001153 fec->bus = bus;
1154 fec_mii_setspeed(bus->priv);
1155#ifdef CONFIG_PHYLIB
1156 fec->phydev = phydev;
1157 phy_connect_dev(phydev, edev);
1158 /* Configure phy */
1159 phy_config(phydev);
1160#else
Marek Vasutedcd6c02011-09-16 01:13:47 +02001161 fec->phy_id = phy_id;
Troy Kiskydce4def2012-10-22 16:40:46 +00001162#endif
1163 eth_register(edev);
Andy Duan8f8e4582017-04-10 19:44:35 +08001164 /* only support one eth device, the index number pointed by dev_id */
1165 edev->index = fec->dev_id;
Troy Kiskydce4def2012-10-22 16:40:46 +00001166
Andy Duan0eaaf832017-04-10 19:44:34 +08001167 if (fec_get_hwaddr(fec->dev_id, ethaddr) == 0) {
1168 debug("got MAC%d address from fuse: %pM\n", fec->dev_id, ethaddr);
Troy Kiskydce4def2012-10-22 16:40:46 +00001169 memcpy(edev->enetaddr, ethaddr, 6);
Andy Duan8f8e4582017-04-10 19:44:35 +08001170 if (fec->dev_id)
1171 sprintf(mac, "eth%daddr", fec->dev_id);
1172 else
1173 strcpy(mac, "ethaddr");
Simon Glass64b723f2017-08-03 12:22:12 -06001174 if (!env_get(mac))
Simon Glass8551d552017-08-03 12:22:11 -06001175 eth_env_set_enetaddr(mac, ethaddr);
Troy Kiskydce4def2012-10-22 16:40:46 +00001176 }
1177 return ret;
Marek Vasut03880452013-10-12 20:36:25 +02001178err4:
1179 fec_free_descs(fec);
Troy Kiskydce4def2012-10-22 16:40:46 +00001180err3:
1181 free(fec);
1182err2:
1183 free(edev);
1184err1:
1185 return ret;
1186}
1187
Troy Kiskydce4def2012-10-22 16:40:46 +00001188int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
1189{
1190 uint32_t base_mii;
1191 struct mii_dev *bus = NULL;
1192#ifdef CONFIG_PHYLIB
1193 struct phy_device *phydev = NULL;
1194#endif
1195 int ret;
1196
Peng Fana65e0362018-03-28 20:54:14 +08001197#ifdef CONFIG_FEC_MXC_MDIO_BASE
Troy Kisky2000c662012-02-07 14:08:47 +00001198 /*
1199 * The i.MX28 has two ethernet interfaces, but they are not equal.
1200 * Only the first one can access the MDIO bus.
1201 */
Peng Fana65e0362018-03-28 20:54:14 +08001202 base_mii = CONFIG_FEC_MXC_MDIO_BASE;
Troy Kisky2000c662012-02-07 14:08:47 +00001203#else
Troy Kiskydce4def2012-10-22 16:40:46 +00001204 base_mii = addr;
Troy Kisky2000c662012-02-07 14:08:47 +00001205#endif
Troy Kiskydce4def2012-10-22 16:40:46 +00001206 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
1207 bus = fec_get_miibus(base_mii, dev_id);
1208 if (!bus)
1209 return -ENOMEM;
Troy Kisky2c42b3c2012-10-22 16:40:45 +00001210#ifdef CONFIG_PHYLIB
Troy Kiskydce4def2012-10-22 16:40:46 +00001211 phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
Troy Kisky2c42b3c2012-10-22 16:40:45 +00001212 if (!phydev) {
Måns Rullgårdc6e4a862015-12-08 15:38:46 +00001213 mdio_unregister(bus);
Troy Kisky2c42b3c2012-10-22 16:40:45 +00001214 free(bus);
Troy Kiskydce4def2012-10-22 16:40:46 +00001215 return -ENOMEM;
Troy Kisky2c42b3c2012-10-22 16:40:45 +00001216 }
Troy Kiskydce4def2012-10-22 16:40:46 +00001217 ret = fec_probe(bd, dev_id, addr, bus, phydev);
1218#else
1219 ret = fec_probe(bd, dev_id, addr, bus, phy_id);
Troy Kisky2c42b3c2012-10-22 16:40:45 +00001220#endif
Troy Kiskydce4def2012-10-22 16:40:46 +00001221 if (ret) {
1222#ifdef CONFIG_PHYLIB
1223 free(phydev);
1224#endif
Måns Rullgårdc6e4a862015-12-08 15:38:46 +00001225 mdio_unregister(bus);
Troy Kiskydce4def2012-10-22 16:40:46 +00001226 free(bus);
1227 }
Marek Vasut43b10302011-09-11 18:05:37 +00001228 return ret;
Ilya Yanoke93a4a52009-07-21 19:32:21 +04001229}
1230
Troy Kisky4e0eae62012-10-22 16:40:42 +00001231#ifdef CONFIG_FEC_MXC_PHYADDR
1232int fecmxc_initialize(bd_t *bd)
1233{
1234 return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR,
1235 IMX_FEC_BASE);
Ilya Yanoke93a4a52009-07-21 19:32:21 +04001236}
Troy Kisky4e0eae62012-10-22 16:40:42 +00001237#endif
Marek Vasut539ecee2011-09-11 18:05:36 +00001238
Troy Kisky2000c662012-02-07 14:08:47 +00001239#ifndef CONFIG_PHYLIB
Marek Vasut539ecee2011-09-11 18:05:36 +00001240int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
1241{
1242 struct fec_priv *fec = (struct fec_priv *)dev->priv;
1243 fec->mii_postcall = cb;
1244 return 0;
Jagan Teki484f0212016-12-06 00:00:49 +01001245}
1246#endif
1247
1248#else
1249
Jagan Teki87e7f352016-12-06 00:00:51 +01001250static int fecmxc_read_rom_hwaddr(struct udevice *dev)
1251{
1252 struct fec_priv *priv = dev_get_priv(dev);
1253 struct eth_pdata *pdata = dev_get_platdata(dev);
1254
1255 return fec_get_hwaddr(priv->dev_id, pdata->enetaddr);
1256}
1257
Ye Libd7e5382018-03-28 20:54:11 +08001258static int fecmxc_free_pkt(struct udevice *dev, uchar *packet, int length)
1259{
1260 if (packet)
1261 free(packet);
1262
1263 return 0;
1264}
1265
Jagan Teki484f0212016-12-06 00:00:49 +01001266static const struct eth_ops fecmxc_ops = {
1267 .start = fecmxc_init,
1268 .send = fecmxc_send,
1269 .recv = fecmxc_recv,
Ye Libd7e5382018-03-28 20:54:11 +08001270 .free_pkt = fecmxc_free_pkt,
Jagan Teki484f0212016-12-06 00:00:49 +01001271 .stop = fecmxc_halt,
1272 .write_hwaddr = fecmxc_set_hwaddr,
Jagan Teki87e7f352016-12-06 00:00:51 +01001273 .read_rom_hwaddr = fecmxc_read_rom_hwaddr,
Jagan Teki484f0212016-12-06 00:00:49 +01001274};
1275
Martyn Welchd1ac23f2018-12-11 11:34:45 +00001276static int device_get_phy_addr(struct udevice *dev)
1277{
1278 struct ofnode_phandle_args phandle_args;
1279 int reg;
1280
1281 if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
1282 &phandle_args)) {
1283 debug("Failed to find phy-handle");
1284 return -ENODEV;
1285 }
1286
1287 reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
1288
1289 return reg;
1290}
1291
Jagan Teki484f0212016-12-06 00:00:49 +01001292static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
1293{
1294 struct phy_device *phydev;
Martyn Welchd1ac23f2018-12-11 11:34:45 +00001295 int addr;
Jagan Teki484f0212016-12-06 00:00:49 +01001296
Martyn Welchd1ac23f2018-12-11 11:34:45 +00001297 addr = device_get_phy_addr(dev);
Lukasz Majewski07b75a32018-04-15 21:45:54 +02001298#ifdef CONFIG_FEC_MXC_PHYADDR
Hannes Schmelzerf7694302019-02-15 10:30:18 +01001299 addr = CONFIG_FEC_MXC_PHYADDR;
Jagan Teki484f0212016-12-06 00:00:49 +01001300#endif
1301
Hannes Schmelzerf7694302019-02-15 10:30:18 +01001302 phydev = phy_connect(priv->bus, addr, dev, priv->interface);
Jagan Teki484f0212016-12-06 00:00:49 +01001303 if (!phydev)
1304 return -ENODEV;
1305
Jagan Teki484f0212016-12-06 00:00:49 +01001306 priv->phydev = phydev;
1307 phy_config(phydev);
1308
1309 return 0;
1310}
1311
Michael Trimarchi0e5cccf2018-06-17 15:22:39 +02001312#ifdef CONFIG_DM_GPIO
1313/* FEC GPIO reset */
1314static void fec_gpio_reset(struct fec_priv *priv)
1315{
1316 debug("fec_gpio_reset: fec_gpio_reset(dev)\n");
1317 if (dm_gpio_is_valid(&priv->phy_reset_gpio)) {
1318 dm_gpio_set_value(&priv->phy_reset_gpio, 1);
Martin Fuzzey9c3f97a2018-10-04 19:59:18 +02001319 mdelay(priv->reset_delay);
Michael Trimarchi0e5cccf2018-06-17 15:22:39 +02001320 dm_gpio_set_value(&priv->phy_reset_gpio, 0);
Andrejs Cainikovs24b6aac2019-03-01 13:27:59 +00001321 if (priv->reset_post_delay)
1322 mdelay(priv->reset_post_delay);
Michael Trimarchi0e5cccf2018-06-17 15:22:39 +02001323 }
1324}
1325#endif
1326
Jagan Teki484f0212016-12-06 00:00:49 +01001327static int fecmxc_probe(struct udevice *dev)
1328{
1329 struct eth_pdata *pdata = dev_get_platdata(dev);
1330 struct fec_priv *priv = dev_get_priv(dev);
1331 struct mii_dev *bus = NULL;
Jagan Teki484f0212016-12-06 00:00:49 +01001332 uint32_t start;
1333 int ret;
1334
Anatolij Gustschinb71fc5e2018-10-18 16:15:11 +02001335 if (IS_ENABLED(CONFIG_IMX8)) {
1336 ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
1337 if (ret < 0) {
1338 debug("Can't get FEC ipg clk: %d\n", ret);
1339 return ret;
1340 }
1341 ret = clk_enable(&priv->ipg_clk);
1342 if (ret < 0) {
1343 debug("Can't enable FEC ipg clk: %d\n", ret);
1344 return ret;
1345 }
1346
1347 priv->clk_rate = clk_get_rate(&priv->ipg_clk);
Peng Fandcf5e1b2019-10-25 09:48:02 +00001348 } else if (CONFIG_IS_ENABLED(CLK_CCF)) {
1349 ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
1350 if (ret < 0) {
1351 debug("Can't get FEC ipg clk: %d\n", ret);
1352 return ret;
1353 }
1354 ret = clk_enable(&priv->ipg_clk);
1355 if(ret)
1356 return ret;
1357
1358 ret = clk_get_by_name(dev, "ahb", &priv->ahb_clk);
1359 if (ret < 0) {
1360 debug("Can't get FEC ahb clk: %d\n", ret);
1361 return ret;
1362 }
1363 ret = clk_enable(&priv->ahb_clk);
1364 if (ret)
1365 return ret;
1366
1367 ret = clk_get_by_name(dev, "enet_out", &priv->clk_enet_out);
1368 if (!ret) {
1369 ret = clk_enable(&priv->clk_enet_out);
1370 if (ret)
1371 return ret;
1372 }
1373
1374 ret = clk_get_by_name(dev, "enet_clk_ref", &priv->clk_ref);
1375 if (!ret) {
1376 ret = clk_enable(&priv->clk_ref);
1377 if (ret)
1378 return ret;
1379 }
1380
1381 ret = clk_get_by_name(dev, "ptp", &priv->clk_ptp);
1382 if (!ret) {
1383 ret = clk_enable(&priv->clk_ptp);
1384 if (ret)
1385 return ret;
1386 }
1387
1388 priv->clk_rate = clk_get_rate(&priv->ipg_clk);
Anatolij Gustschinb71fc5e2018-10-18 16:15:11 +02001389 }
1390
Jagan Teki484f0212016-12-06 00:00:49 +01001391 ret = fec_alloc_descs(priv);
1392 if (ret)
1393 return ret;
1394
Martin Fuzzey9a6a2c92018-10-04 19:59:20 +02001395#ifdef CONFIG_DM_REGULATOR
1396 if (priv->phy_supply) {
Adam Fordb3301b62019-01-15 11:26:48 -06001397 ret = regulator_set_enable(priv->phy_supply, true);
Martin Fuzzey9a6a2c92018-10-04 19:59:20 +02001398 if (ret) {
1399 printf("%s: Error enabling phy supply\n", dev->name);
1400 return ret;
1401 }
1402 }
1403#endif
1404
Michael Trimarchi0e5cccf2018-06-17 15:22:39 +02001405#ifdef CONFIG_DM_GPIO
1406 fec_gpio_reset(priv);
1407#endif
Jagan Teki484f0212016-12-06 00:00:49 +01001408 /* Reset chip. */
Jagan Tekic6cd8d52016-12-06 00:00:50 +01001409 writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET,
1410 &priv->eth->ecntrl);
Jagan Teki484f0212016-12-06 00:00:49 +01001411 start = get_timer(0);
1412 while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) {
1413 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1414 printf("FEC MXC: Timeout reseting chip\n");
1415 goto err_timeout;
1416 }
1417 udelay(10);
1418 }
1419
1420 fec_reg_setup(priv);
Jagan Teki484f0212016-12-06 00:00:49 +01001421
Peng Fanbd3e8cb2018-03-28 20:54:13 +08001422 priv->dev_id = dev->seq;
Peng Fana65e0362018-03-28 20:54:14 +08001423#ifdef CONFIG_FEC_MXC_MDIO_BASE
1424 bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE, dev->seq);
1425#else
Peng Fanbd3e8cb2018-03-28 20:54:13 +08001426 bus = fec_get_miibus((ulong)priv->eth, dev->seq);
Peng Fana65e0362018-03-28 20:54:14 +08001427#endif
Lothar Waßmannd33e9ee2017-06-27 15:23:16 +02001428 if (!bus) {
1429 ret = -ENOMEM;
1430 goto err_mii;
1431 }
1432
1433 priv->bus = bus;
Lothar Waßmannd33e9ee2017-06-27 15:23:16 +02001434 priv->interface = pdata->phy_interface;
Martin Fuzzeyf08eb3d2018-10-04 19:59:21 +02001435 switch (priv->interface) {
1436 case PHY_INTERFACE_MODE_MII:
1437 priv->xcv_type = MII100;
1438 break;
1439 case PHY_INTERFACE_MODE_RMII:
1440 priv->xcv_type = RMII;
1441 break;
1442 case PHY_INTERFACE_MODE_RGMII:
1443 case PHY_INTERFACE_MODE_RGMII_ID:
1444 case PHY_INTERFACE_MODE_RGMII_RXID:
1445 case PHY_INTERFACE_MODE_RGMII_TXID:
1446 priv->xcv_type = RGMII;
1447 break;
1448 default:
1449 priv->xcv_type = CONFIG_FEC_XCV_TYPE;
1450 printf("Unsupported interface type %d defaulting to %d\n",
1451 priv->interface, priv->xcv_type);
1452 break;
1453 }
1454
Lothar Waßmannd33e9ee2017-06-27 15:23:16 +02001455 ret = fec_phy_init(priv, dev);
1456 if (ret)
1457 goto err_phy;
1458
Jagan Teki484f0212016-12-06 00:00:49 +01001459 return 0;
1460
Jagan Teki484f0212016-12-06 00:00:49 +01001461err_phy:
1462 mdio_unregister(bus);
1463 free(bus);
1464err_mii:
Ye Li5fa556c2018-03-28 20:54:16 +08001465err_timeout:
Jagan Teki484f0212016-12-06 00:00:49 +01001466 fec_free_descs(priv);
1467 return ret;
Marek Vasut539ecee2011-09-11 18:05:36 +00001468}
Jagan Teki484f0212016-12-06 00:00:49 +01001469
1470static int fecmxc_remove(struct udevice *dev)
1471{
1472 struct fec_priv *priv = dev_get_priv(dev);
1473
1474 free(priv->phydev);
1475 fec_free_descs(priv);
1476 mdio_unregister(priv->bus);
1477 mdio_free(priv->bus);
1478
Martin Fuzzey9a6a2c92018-10-04 19:59:20 +02001479#ifdef CONFIG_DM_REGULATOR
1480 if (priv->phy_supply)
1481 regulator_set_enable(priv->phy_supply, false);
1482#endif
1483
Jagan Teki484f0212016-12-06 00:00:49 +01001484 return 0;
1485}
1486
1487static int fecmxc_ofdata_to_platdata(struct udevice *dev)
1488{
Michael Trimarchi0e5cccf2018-06-17 15:22:39 +02001489 int ret = 0;
Jagan Teki484f0212016-12-06 00:00:49 +01001490 struct eth_pdata *pdata = dev_get_platdata(dev);
1491 struct fec_priv *priv = dev_get_priv(dev);
1492 const char *phy_mode;
1493
Simon Glassba1dea42017-05-17 17:18:05 -06001494 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
Jagan Teki484f0212016-12-06 00:00:49 +01001495 priv->eth = (struct ethernet_regs *)pdata->iobase;
1496
1497 pdata->phy_interface = -1;
Simon Glassdd79d6e2017-01-17 16:52:55 -07001498 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1499 NULL);
Jagan Teki484f0212016-12-06 00:00:49 +01001500 if (phy_mode)
1501 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
1502 if (pdata->phy_interface == -1) {
1503 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1504 return -EINVAL;
1505 }
1506
Martin Fuzzey9a6a2c92018-10-04 19:59:20 +02001507#ifdef CONFIG_DM_REGULATOR
1508 device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
1509#endif
1510
Michael Trimarchi0e5cccf2018-06-17 15:22:39 +02001511#ifdef CONFIG_DM_GPIO
1512 ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
Martin Fuzzey185e3b82018-10-04 19:59:19 +02001513 &priv->phy_reset_gpio, GPIOD_IS_OUT);
1514 if (ret < 0)
1515 return 0; /* property is optional, don't return error! */
Jagan Teki484f0212016-12-06 00:00:49 +01001516
Martin Fuzzey185e3b82018-10-04 19:59:19 +02001517 priv->reset_delay = dev_read_u32_default(dev, "phy-reset-duration", 1);
Michael Trimarchi0e5cccf2018-06-17 15:22:39 +02001518 if (priv->reset_delay > 1000) {
Martin Fuzzey185e3b82018-10-04 19:59:19 +02001519 printf("FEC MXC: phy reset duration should be <= 1000ms\n");
1520 /* property value wrong, use default value */
1521 priv->reset_delay = 1;
Michael Trimarchi0e5cccf2018-06-17 15:22:39 +02001522 }
Andrejs Cainikovs24b6aac2019-03-01 13:27:59 +00001523
1524 priv->reset_post_delay = dev_read_u32_default(dev,
1525 "phy-reset-post-delay",
1526 0);
1527 if (priv->reset_post_delay > 1000) {
1528 printf("FEC MXC: phy reset post delay should be <= 1000ms\n");
1529 /* property value wrong, use default value */
1530 priv->reset_post_delay = 0;
1531 }
Michael Trimarchi0e5cccf2018-06-17 15:22:39 +02001532#endif
1533
Martin Fuzzey185e3b82018-10-04 19:59:19 +02001534 return 0;
Jagan Teki484f0212016-12-06 00:00:49 +01001535}
1536
1537static const struct udevice_id fecmxc_ids[] = {
Lukasz Majewski8a8f5a62019-06-19 17:31:03 +02001538 { .compatible = "fsl,imx28-fec" },
Jagan Teki484f0212016-12-06 00:00:49 +01001539 { .compatible = "fsl,imx6q-fec" },
Peng Fan56406302018-03-28 20:54:15 +08001540 { .compatible = "fsl,imx6sl-fec" },
1541 { .compatible = "fsl,imx6sx-fec" },
1542 { .compatible = "fsl,imx6ul-fec" },
Lukasz Majewski47311222018-04-15 21:54:22 +02001543 { .compatible = "fsl,imx53-fec" },
Anatolij Gustschinb71fc5e2018-10-18 16:15:11 +02001544 { .compatible = "fsl,imx7d-fec" },
Lukasz Majewski6b94b0e2019-02-13 22:46:38 +01001545 { .compatible = "fsl,mvf600-fec" },
Jagan Teki484f0212016-12-06 00:00:49 +01001546 { }
1547};
1548
1549U_BOOT_DRIVER(fecmxc_gem) = {
1550 .name = "fecmxc",
1551 .id = UCLASS_ETH,
1552 .of_match = fecmxc_ids,
1553 .ofdata_to_platdata = fecmxc_ofdata_to_platdata,
1554 .probe = fecmxc_probe,
1555 .remove = fecmxc_remove,
1556 .ops = &fecmxc_ops,
1557 .priv_auto_alloc_size = sizeof(struct fec_priv),
1558 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1559};
Troy Kisky2000c662012-02-07 14:08:47 +00001560#endif