Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com> |
| 4 | * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org> |
| 5 | * (C) Copyright 2008 Armadeus Systems nc |
| 6 | * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> |
| 7 | * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de> |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #include <common.h> |
Simon Glass | 6333448 | 2019-11-14 12:57:39 -0700 | [diff] [blame] | 11 | #include <cpu_func.h> |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 12 | #include <dm.h> |
Simon Glass | 5e6201b | 2019-08-01 09:46:51 -0600 | [diff] [blame] | 13 | #include <env.h> |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 14 | #include <malloc.h> |
Simon Glass | 2dd337a | 2015-09-02 17:24:58 -0600 | [diff] [blame] | 15 | #include <memalign.h> |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 16 | #include <miiphy.h> |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 17 | #include <net.h> |
Jeroen Hofstee | 120f43f | 2014-10-08 22:57:40 +0200 | [diff] [blame] | 18 | #include <netdev.h> |
Martin Fuzzey | 9a6a2c9 | 2018-10-04 19:59:20 +0200 | [diff] [blame] | 19 | #include <power/regulator.h> |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 20 | |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 21 | #include <asm/io.h> |
Masahiro Yamada | 56a931c | 2016-09-21 11:28:55 +0900 | [diff] [blame] | 22 | #include <linux/errno.h> |
Marek Vasut | 4d85b03 | 2012-08-26 10:19:20 +0000 | [diff] [blame] | 23 | #include <linux/compiler.h> |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 24 | |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 25 | #include <asm/arch/clock.h> |
| 26 | #include <asm/arch/imx-regs.h> |
Stefano Babic | 33731bc | 2017-06-29 10:16:06 +0200 | [diff] [blame] | 27 | #include <asm/mach-imx/sys_proto.h> |
Michael Trimarchi | 0e5cccf | 2018-06-17 15:22:39 +0200 | [diff] [blame] | 28 | #include <asm-generic/gpio.h> |
| 29 | |
| 30 | #include "fec_mxc.h" |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 31 | |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 32 | DECLARE_GLOBAL_DATA_PTR; |
| 33 | |
Marek Vasut | 5f1631d | 2012-08-29 03:49:49 +0000 | [diff] [blame] | 34 | /* |
| 35 | * Timeout the transfer after 5 mS. This is usually a bit more, since |
| 36 | * the code in the tightloops this timeout is used in adds some overhead. |
| 37 | */ |
| 38 | #define FEC_XFER_TIMEOUT 5000 |
| 39 | |
Fabio Estevam | 8b798b2 | 2014-08-25 13:34:16 -0300 | [diff] [blame] | 40 | /* |
| 41 | * The standard 32-byte DMA alignment does not work on mx6solox, which requires |
| 42 | * 64-byte alignment in the DMA RX FEC buffer. |
| 43 | * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also |
| 44 | * satisfies the alignment on other SoCs (32-bytes) |
| 45 | */ |
| 46 | #define FEC_DMA_RX_MINALIGN 64 |
| 47 | |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 48 | #ifndef CONFIG_MII |
| 49 | #error "CONFIG_MII has to be defined!" |
| 50 | #endif |
| 51 | |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 52 | #ifndef CONFIG_FEC_XCV_TYPE |
| 53 | #define CONFIG_FEC_XCV_TYPE MII100 |
Marek Vasut | dbb4fce | 2011-09-11 18:05:33 +0000 | [diff] [blame] | 54 | #endif |
| 55 | |
Marek Vasut | 6a5fd4c | 2011-11-08 23:18:10 +0000 | [diff] [blame] | 56 | /* |
| 57 | * The i.MX28 operates with packets in big endian. We need to swap them before |
| 58 | * sending and after receiving. |
| 59 | */ |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 60 | #ifdef CONFIG_MX28 |
| 61 | #define CONFIG_FEC_MXC_SWAP_PACKET |
Marek Vasut | 6a5fd4c | 2011-11-08 23:18:10 +0000 | [diff] [blame] | 62 | #endif |
| 63 | |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 64 | #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd)) |
| 65 | |
| 66 | /* Check various alignment issues at compile time */ |
| 67 | #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0)) |
| 68 | #error "ARCH_DMA_MINALIGN must be multiple of 16!" |
| 69 | #endif |
| 70 | |
| 71 | #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \ |
| 72 | (PKTALIGN % ARCH_DMA_MINALIGN != 0)) |
| 73 | #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!" |
| 74 | #endif |
| 75 | |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 76 | #undef DEBUG |
| 77 | |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 78 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
Marek Vasut | 6a5fd4c | 2011-11-08 23:18:10 +0000 | [diff] [blame] | 79 | static void swap_packet(uint32_t *packet, int length) |
| 80 | { |
| 81 | int i; |
| 82 | |
| 83 | for (i = 0; i < DIV_ROUND_UP(length, 4); i++) |
| 84 | packet[i] = __swab32(packet[i]); |
| 85 | } |
| 86 | #endif |
| 87 | |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 88 | /* MII-interface related functions */ |
| 89 | static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr, |
| 90 | uint8_t regaddr) |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 91 | { |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 92 | uint32_t reg; /* convenient holder for the PHY register */ |
| 93 | uint32_t phy; /* convenient holder for the PHY */ |
| 94 | uint32_t start; |
Troy Kisky | 2000c66 | 2012-02-07 14:08:47 +0000 | [diff] [blame] | 95 | int val; |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 96 | |
| 97 | /* |
| 98 | * reading from any PHY's register is done by properly |
| 99 | * programming the FEC's MII data register. |
| 100 | */ |
Marek Vasut | bf2386b | 2011-09-11 18:05:34 +0000 | [diff] [blame] | 101 | writel(FEC_IEVENT_MII, ð->ievent); |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 102 | reg = regaddr << FEC_MII_DATA_RA_SHIFT; |
| 103 | phy = phyaddr << FEC_MII_DATA_PA_SHIFT; |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 104 | |
| 105 | writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | |
Marek Vasut | bf2386b | 2011-09-11 18:05:34 +0000 | [diff] [blame] | 106 | phy | reg, ð->mii_data); |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 107 | |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 108 | /* wait for the related interrupt */ |
Graeme Russ | f8b82ee | 2011-07-15 23:31:37 +0000 | [diff] [blame] | 109 | start = get_timer(0); |
Marek Vasut | bf2386b | 2011-09-11 18:05:34 +0000 | [diff] [blame] | 110 | while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 111 | if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { |
| 112 | printf("Read MDIO failed...\n"); |
| 113 | return -1; |
| 114 | } |
| 115 | } |
| 116 | |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 117 | /* clear mii interrupt bit */ |
Marek Vasut | bf2386b | 2011-09-11 18:05:34 +0000 | [diff] [blame] | 118 | writel(FEC_IEVENT_MII, ð->ievent); |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 119 | |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 120 | /* it's now safe to read the PHY's register */ |
Troy Kisky | 2000c66 | 2012-02-07 14:08:47 +0000 | [diff] [blame] | 121 | val = (unsigned short)readl(ð->mii_data); |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 122 | debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr, |
| 123 | regaddr, val); |
Troy Kisky | 2000c66 | 2012-02-07 14:08:47 +0000 | [diff] [blame] | 124 | return val; |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 125 | } |
| 126 | |
Peng Fan | dcf5e1b | 2019-10-25 09:48:02 +0000 | [diff] [blame] | 127 | #ifndef imx_get_fecclk |
| 128 | u32 __weak imx_get_fecclk(void) |
| 129 | { |
| 130 | return 0; |
| 131 | } |
| 132 | #endif |
| 133 | |
Anatolij Gustschin | b71fc5e | 2018-10-18 16:15:11 +0200 | [diff] [blame] | 134 | static int fec_get_clk_rate(void *udev, int idx) |
| 135 | { |
Anatolij Gustschin | b71fc5e | 2018-10-18 16:15:11 +0200 | [diff] [blame] | 136 | struct fec_priv *fec; |
| 137 | struct udevice *dev; |
| 138 | int ret; |
| 139 | |
Peng Fan | dcf5e1b | 2019-10-25 09:48:02 +0000 | [diff] [blame] | 140 | if (IS_ENABLED(CONFIG_IMX8) || |
| 141 | CONFIG_IS_ENABLED(CLK_CCF)) { |
| 142 | dev = udev; |
| 143 | if (!dev) { |
| 144 | ret = uclass_get_device(UCLASS_ETH, idx, &dev); |
| 145 | if (ret < 0) { |
| 146 | debug("Can't get FEC udev: %d\n", ret); |
| 147 | return ret; |
| 148 | } |
Anatolij Gustschin | b71fc5e | 2018-10-18 16:15:11 +0200 | [diff] [blame] | 149 | } |
Anatolij Gustschin | b71fc5e | 2018-10-18 16:15:11 +0200 | [diff] [blame] | 150 | |
Peng Fan | dcf5e1b | 2019-10-25 09:48:02 +0000 | [diff] [blame] | 151 | fec = dev_get_priv(dev); |
| 152 | if (fec) |
| 153 | return fec->clk_rate; |
Anatolij Gustschin | b71fc5e | 2018-10-18 16:15:11 +0200 | [diff] [blame] | 154 | |
Peng Fan | dcf5e1b | 2019-10-25 09:48:02 +0000 | [diff] [blame] | 155 | return -EINVAL; |
| 156 | } else { |
| 157 | return imx_get_fecclk(); |
| 158 | } |
Anatolij Gustschin | b71fc5e | 2018-10-18 16:15:11 +0200 | [diff] [blame] | 159 | } |
| 160 | |
Troy Kisky | 5e76265 | 2012-10-22 16:40:41 +0000 | [diff] [blame] | 161 | static void fec_mii_setspeed(struct ethernet_regs *eth) |
Stefano Babic | 889f2e2 | 2010-02-01 14:51:30 +0100 | [diff] [blame] | 162 | { |
| 163 | /* |
| 164 | * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock |
| 165 | * and do not drop the Preamble. |
Måns Rullgård | 4aeddb7 | 2015-12-08 15:38:45 +0000 | [diff] [blame] | 166 | * |
| 167 | * The i.MX28 and i.MX6 types have another field in the MSCR (aka |
| 168 | * MII_SPEED) register that defines the MDIO output hold time. Earlier |
| 169 | * versions are RAZ there, so just ignore the difference and write the |
| 170 | * register always. |
| 171 | * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. |
| 172 | * HOLDTIME + 1 is the number of clk cycles the fec is holding the |
| 173 | * output. |
| 174 | * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). |
| 175 | * Given that ceil(clkrate / 5000000) <= 64, the calculation for |
| 176 | * holdtime cannot result in a value greater than 3. |
Stefano Babic | 889f2e2 | 2010-02-01 14:51:30 +0100 | [diff] [blame] | 177 | */ |
Anatolij Gustschin | b71fc5e | 2018-10-18 16:15:11 +0200 | [diff] [blame] | 178 | u32 pclk; |
| 179 | u32 speed; |
| 180 | u32 hold; |
| 181 | int ret; |
| 182 | |
| 183 | ret = fec_get_clk_rate(NULL, 0); |
| 184 | if (ret < 0) { |
| 185 | printf("Can't find FEC0 clk rate: %d\n", ret); |
| 186 | return; |
| 187 | } |
| 188 | pclk = ret; |
| 189 | speed = DIV_ROUND_UP(pclk, 5000000); |
| 190 | hold = DIV_ROUND_UP(pclk, 100000000) - 1; |
| 191 | |
Markus Niebel | 1af8274 | 2014-02-05 10:54:11 +0100 | [diff] [blame] | 192 | #ifdef FEC_QUIRK_ENET_MAC |
| 193 | speed--; |
| 194 | #endif |
Måns Rullgård | 4aeddb7 | 2015-12-08 15:38:45 +0000 | [diff] [blame] | 195 | writel(speed << 1 | hold << 8, ð->mii_speed); |
Troy Kisky | 5e76265 | 2012-10-22 16:40:41 +0000 | [diff] [blame] | 196 | debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed)); |
Stefano Babic | 889f2e2 | 2010-02-01 14:51:30 +0100 | [diff] [blame] | 197 | } |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 198 | |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 199 | static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr, |
| 200 | uint8_t regaddr, uint16_t data) |
Troy Kisky | 2000c66 | 2012-02-07 14:08:47 +0000 | [diff] [blame] | 201 | { |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 202 | uint32_t reg; /* convenient holder for the PHY register */ |
| 203 | uint32_t phy; /* convenient holder for the PHY */ |
| 204 | uint32_t start; |
| 205 | |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 206 | reg = regaddr << FEC_MII_DATA_RA_SHIFT; |
| 207 | phy = phyaddr << FEC_MII_DATA_PA_SHIFT; |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 208 | |
| 209 | writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | |
Marek Vasut | bf2386b | 2011-09-11 18:05:34 +0000 | [diff] [blame] | 210 | FEC_MII_DATA_TA | phy | reg | data, ð->mii_data); |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 211 | |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 212 | /* wait for the MII interrupt */ |
Graeme Russ | f8b82ee | 2011-07-15 23:31:37 +0000 | [diff] [blame] | 213 | start = get_timer(0); |
Marek Vasut | bf2386b | 2011-09-11 18:05:34 +0000 | [diff] [blame] | 214 | while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 215 | if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { |
| 216 | printf("Write MDIO failed...\n"); |
| 217 | return -1; |
| 218 | } |
| 219 | } |
| 220 | |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 221 | /* clear MII interrupt bit */ |
Marek Vasut | bf2386b | 2011-09-11 18:05:34 +0000 | [diff] [blame] | 222 | writel(FEC_IEVENT_MII, ð->ievent); |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 223 | debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr, |
| 224 | regaddr, data); |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 225 | |
| 226 | return 0; |
| 227 | } |
| 228 | |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 229 | static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr, |
| 230 | int regaddr) |
Troy Kisky | 2000c66 | 2012-02-07 14:08:47 +0000 | [diff] [blame] | 231 | { |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 232 | return fec_mdio_read(bus->priv, phyaddr, regaddr); |
Troy Kisky | 2000c66 | 2012-02-07 14:08:47 +0000 | [diff] [blame] | 233 | } |
| 234 | |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 235 | static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr, |
| 236 | int regaddr, u16 data) |
Troy Kisky | 2000c66 | 2012-02-07 14:08:47 +0000 | [diff] [blame] | 237 | { |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 238 | return fec_mdio_write(bus->priv, phyaddr, regaddr, data); |
Troy Kisky | 2000c66 | 2012-02-07 14:08:47 +0000 | [diff] [blame] | 239 | } |
| 240 | |
| 241 | #ifndef CONFIG_PHYLIB |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 242 | static int miiphy_restart_aneg(struct eth_device *dev) |
| 243 | { |
Stefano Babic | d622817 | 2012-02-22 00:24:35 +0000 | [diff] [blame] | 244 | int ret = 0; |
| 245 | #if !defined(CONFIG_FEC_MXC_NO_ANEG) |
Marek Vasut | edcd6c0 | 2011-09-16 01:13:47 +0200 | [diff] [blame] | 246 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
Troy Kisky | 2000c66 | 2012-02-07 14:08:47 +0000 | [diff] [blame] | 247 | struct ethernet_regs *eth = fec->bus->priv; |
Marek Vasut | edcd6c0 | 2011-09-16 01:13:47 +0200 | [diff] [blame] | 248 | |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 249 | /* |
| 250 | * Wake up from sleep if necessary |
| 251 | * Reset PHY, then delay 300ns |
| 252 | */ |
John Rigby | e650e49 | 2010-01-25 23:12:55 -0700 | [diff] [blame] | 253 | #ifdef CONFIG_MX27 |
Troy Kisky | 2000c66 | 2012-02-07 14:08:47 +0000 | [diff] [blame] | 254 | fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF); |
John Rigby | e650e49 | 2010-01-25 23:12:55 -0700 | [diff] [blame] | 255 | #endif |
Troy Kisky | 2000c66 | 2012-02-07 14:08:47 +0000 | [diff] [blame] | 256 | fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET); |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 257 | udelay(1000); |
| 258 | |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 259 | /* Set the auto-negotiation advertisement register bits */ |
Troy Kisky | 2000c66 | 2012-02-07 14:08:47 +0000 | [diff] [blame] | 260 | fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE, |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 261 | LPA_100FULL | LPA_100HALF | LPA_10FULL | |
| 262 | LPA_10HALF | PHY_ANLPAR_PSB_802_3); |
Troy Kisky | 2000c66 | 2012-02-07 14:08:47 +0000 | [diff] [blame] | 263 | fec_mdio_write(eth, fec->phy_id, MII_BMCR, |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 264 | BMCR_ANENABLE | BMCR_ANRESTART); |
Marek Vasut | 539ecee | 2011-09-11 18:05:36 +0000 | [diff] [blame] | 265 | |
| 266 | if (fec->mii_postcall) |
| 267 | ret = fec->mii_postcall(fec->phy_id); |
| 268 | |
Stefano Babic | d622817 | 2012-02-22 00:24:35 +0000 | [diff] [blame] | 269 | #endif |
Marek Vasut | 539ecee | 2011-09-11 18:05:36 +0000 | [diff] [blame] | 270 | return ret; |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 271 | } |
| 272 | |
Hannes Schmelzer | 5a15c1a | 2016-06-22 12:07:14 +0200 | [diff] [blame] | 273 | #ifndef CONFIG_FEC_FIXED_SPEED |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 274 | static int miiphy_wait_aneg(struct eth_device *dev) |
| 275 | { |
| 276 | uint32_t start; |
Troy Kisky | 2000c66 | 2012-02-07 14:08:47 +0000 | [diff] [blame] | 277 | int status; |
Marek Vasut | edcd6c0 | 2011-09-16 01:13:47 +0200 | [diff] [blame] | 278 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
Troy Kisky | 2000c66 | 2012-02-07 14:08:47 +0000 | [diff] [blame] | 279 | struct ethernet_regs *eth = fec->bus->priv; |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 280 | |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 281 | /* Wait for AN completion */ |
Graeme Russ | f8b82ee | 2011-07-15 23:31:37 +0000 | [diff] [blame] | 282 | start = get_timer(0); |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 283 | do { |
| 284 | if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { |
| 285 | printf("%s: Autonegotiation timeout\n", dev->name); |
| 286 | return -1; |
| 287 | } |
| 288 | |
Troy Kisky | 2000c66 | 2012-02-07 14:08:47 +0000 | [diff] [blame] | 289 | status = fec_mdio_read(eth, fec->phy_id, MII_BMSR); |
| 290 | if (status < 0) { |
| 291 | printf("%s: Autonegotiation failed. status: %d\n", |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 292 | dev->name, status); |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 293 | return -1; |
| 294 | } |
Mike Frysinger | d63ee71 | 2010-12-23 15:40:12 -0500 | [diff] [blame] | 295 | } while (!(status & BMSR_LSTATUS)); |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 296 | |
| 297 | return 0; |
| 298 | } |
Hannes Schmelzer | 5a15c1a | 2016-06-22 12:07:14 +0200 | [diff] [blame] | 299 | #endif /* CONFIG_FEC_FIXED_SPEED */ |
Troy Kisky | 2000c66 | 2012-02-07 14:08:47 +0000 | [diff] [blame] | 300 | #endif |
| 301 | |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 302 | static int fec_rx_task_enable(struct fec_priv *fec) |
| 303 | { |
Marek Vasut | c1582c0 | 2012-08-29 03:49:51 +0000 | [diff] [blame] | 304 | writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active); |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 305 | return 0; |
| 306 | } |
| 307 | |
| 308 | static int fec_rx_task_disable(struct fec_priv *fec) |
| 309 | { |
| 310 | return 0; |
| 311 | } |
| 312 | |
| 313 | static int fec_tx_task_enable(struct fec_priv *fec) |
| 314 | { |
Marek Vasut | c1582c0 | 2012-08-29 03:49:51 +0000 | [diff] [blame] | 315 | writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active); |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 316 | return 0; |
| 317 | } |
| 318 | |
| 319 | static int fec_tx_task_disable(struct fec_priv *fec) |
| 320 | { |
| 321 | return 0; |
| 322 | } |
| 323 | |
| 324 | /** |
| 325 | * Initialize receive task's buffer descriptors |
| 326 | * @param[in] fec all we know about the device yet |
| 327 | * @param[in] count receive buffer count to be allocated |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 328 | * @param[in] dsize desired size of each receive buffer |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 329 | * @return 0 on success |
| 330 | * |
Marek Vasut | 0388045 | 2013-10-12 20:36:25 +0200 | [diff] [blame] | 331 | * Init all RX descriptors to default values. |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 332 | */ |
Marek Vasut | 0388045 | 2013-10-12 20:36:25 +0200 | [diff] [blame] | 333 | static void fec_rbd_init(struct fec_priv *fec, int count, int dsize) |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 334 | { |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 335 | uint32_t size; |
Ye Li | e267091 | 2018-01-10 13:20:44 +0800 | [diff] [blame] | 336 | ulong data; |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 337 | int i; |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 338 | |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 339 | /* |
Marek Vasut | 0388045 | 2013-10-12 20:36:25 +0200 | [diff] [blame] | 340 | * Reload the RX descriptors with default values and wipe |
| 341 | * the RX buffers. |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 342 | */ |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 343 | size = roundup(dsize, ARCH_DMA_MINALIGN); |
| 344 | for (i = 0; i < count; i++) { |
Ye Li | e267091 | 2018-01-10 13:20:44 +0800 | [diff] [blame] | 345 | data = fec->rbd_base[i].data_pointer; |
| 346 | memset((void *)data, 0, dsize); |
| 347 | flush_dcache_range(data, data + size); |
Marek Vasut | 0388045 | 2013-10-12 20:36:25 +0200 | [diff] [blame] | 348 | |
| 349 | fec->rbd_base[i].status = FEC_RBD_EMPTY; |
| 350 | fec->rbd_base[i].data_length = 0; |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 351 | } |
| 352 | |
| 353 | /* Mark the last RBD to close the ring. */ |
Marek Vasut | 0388045 | 2013-10-12 20:36:25 +0200 | [diff] [blame] | 354 | fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY; |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 355 | fec->rbd_index = 0; |
| 356 | |
Ye Li | e267091 | 2018-01-10 13:20:44 +0800 | [diff] [blame] | 357 | flush_dcache_range((ulong)fec->rbd_base, |
| 358 | (ulong)fec->rbd_base + size); |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 359 | } |
| 360 | |
| 361 | /** |
| 362 | * Initialize transmit task's buffer descriptors |
| 363 | * @param[in] fec all we know about the device yet |
| 364 | * |
| 365 | * Transmit buffers are created externally. We only have to init the BDs here.\n |
| 366 | * Note: There is a race condition in the hardware. When only one BD is in |
| 367 | * use it must be marked with the WRAP bit to use it for every transmitt. |
| 368 | * This bit in combination with the READY bit results into double transmit |
| 369 | * of each data buffer. It seems the state machine checks READY earlier then |
| 370 | * resetting it after the first transfer. |
| 371 | * Using two BDs solves this issue. |
| 372 | */ |
| 373 | static void fec_tbd_init(struct fec_priv *fec) |
| 374 | { |
Ye Li | e267091 | 2018-01-10 13:20:44 +0800 | [diff] [blame] | 375 | ulong addr = (ulong)fec->tbd_base; |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 376 | unsigned size = roundup(2 * sizeof(struct fec_bd), |
| 377 | ARCH_DMA_MINALIGN); |
Marek Vasut | 0388045 | 2013-10-12 20:36:25 +0200 | [diff] [blame] | 378 | |
| 379 | memset(fec->tbd_base, 0, size); |
| 380 | fec->tbd_base[0].status = 0; |
| 381 | fec->tbd_base[1].status = FEC_TBD_WRAP; |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 382 | fec->tbd_index = 0; |
Marek Vasut | 0388045 | 2013-10-12 20:36:25 +0200 | [diff] [blame] | 383 | flush_dcache_range(addr, addr + size); |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 384 | } |
| 385 | |
| 386 | /** |
| 387 | * Mark the given read buffer descriptor as free |
| 388 | * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0 |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 389 | * @param[in] prbd buffer descriptor to mark free again |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 390 | */ |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 391 | static void fec_rbd_clean(int last, struct fec_bd *prbd) |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 392 | { |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 393 | unsigned short flags = FEC_RBD_EMPTY; |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 394 | if (last) |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 395 | flags |= FEC_RBD_WRAP; |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 396 | writew(flags, &prbd->status); |
| 397 | writew(0, &prbd->data_length); |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 398 | } |
| 399 | |
Jagan Teki | bc5fb46 | 2016-12-06 00:00:48 +0100 | [diff] [blame] | 400 | static int fec_get_hwaddr(int dev_id, unsigned char *mac) |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 401 | { |
Fabio Estevam | 04fc128 | 2011-12-20 05:46:31 +0000 | [diff] [blame] | 402 | imx_get_mac_from_fuse(dev_id, mac); |
Joe Hershberger | 8ecdbed | 2015-04-08 01:41:04 -0500 | [diff] [blame] | 403 | return !is_valid_ethaddr(mac); |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 404 | } |
| 405 | |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 406 | #ifdef CONFIG_DM_ETH |
| 407 | static int fecmxc_set_hwaddr(struct udevice *dev) |
| 408 | #else |
Stefano Babic | 889f2e2 | 2010-02-01 14:51:30 +0100 | [diff] [blame] | 409 | static int fec_set_hwaddr(struct eth_device *dev) |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 410 | #endif |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 411 | { |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 412 | #ifdef CONFIG_DM_ETH |
| 413 | struct fec_priv *fec = dev_get_priv(dev); |
| 414 | struct eth_pdata *pdata = dev_get_platdata(dev); |
| 415 | uchar *mac = pdata->enetaddr; |
| 416 | #else |
Stefano Babic | 889f2e2 | 2010-02-01 14:51:30 +0100 | [diff] [blame] | 417 | uchar *mac = dev->enetaddr; |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 418 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 419 | #endif |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 420 | |
| 421 | writel(0, &fec->eth->iaddr1); |
| 422 | writel(0, &fec->eth->iaddr2); |
| 423 | writel(0, &fec->eth->gaddr1); |
| 424 | writel(0, &fec->eth->gaddr2); |
| 425 | |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 426 | /* Set physical address */ |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 427 | writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3], |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 428 | &fec->eth->paddr1); |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 429 | writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2); |
| 430 | |
| 431 | return 0; |
| 432 | } |
| 433 | |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 434 | /* Do initial configuration of the FEC registers */ |
Marek Vasut | 335cbd2 | 2012-05-01 11:09:41 +0000 | [diff] [blame] | 435 | static void fec_reg_setup(struct fec_priv *fec) |
| 436 | { |
| 437 | uint32_t rcntrl; |
| 438 | |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 439 | /* Set interrupt mask register */ |
Marek Vasut | 335cbd2 | 2012-05-01 11:09:41 +0000 | [diff] [blame] | 440 | writel(0x00000000, &fec->eth->imask); |
| 441 | |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 442 | /* Clear FEC-Lite interrupt event register(IEVENT) */ |
Marek Vasut | 335cbd2 | 2012-05-01 11:09:41 +0000 | [diff] [blame] | 443 | writel(0xffffffff, &fec->eth->ievent); |
| 444 | |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 445 | /* Set FEC-Lite receive control register(R_CNTRL): */ |
Marek Vasut | 335cbd2 | 2012-05-01 11:09:41 +0000 | [diff] [blame] | 446 | |
| 447 | /* Start with frame length = 1518, common for all modes. */ |
| 448 | rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT; |
benoit.thebaudeau@advans | acc7a28 | 2012-07-19 02:12:46 +0000 | [diff] [blame] | 449 | if (fec->xcv_type != SEVENWIRE) /* xMII modes */ |
| 450 | rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE; |
| 451 | if (fec->xcv_type == RGMII) |
Marek Vasut | 335cbd2 | 2012-05-01 11:09:41 +0000 | [diff] [blame] | 452 | rcntrl |= FEC_RCNTRL_RGMII; |
| 453 | else if (fec->xcv_type == RMII) |
| 454 | rcntrl |= FEC_RCNTRL_RMII; |
Marek Vasut | 335cbd2 | 2012-05-01 11:09:41 +0000 | [diff] [blame] | 455 | |
| 456 | writel(rcntrl, &fec->eth->r_cntrl); |
| 457 | } |
| 458 | |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 459 | /** |
| 460 | * Start the FEC engine |
| 461 | * @param[in] dev Our device to handle |
| 462 | */ |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 463 | #ifdef CONFIG_DM_ETH |
| 464 | static int fec_open(struct udevice *dev) |
| 465 | #else |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 466 | static int fec_open(struct eth_device *edev) |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 467 | #endif |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 468 | { |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 469 | #ifdef CONFIG_DM_ETH |
| 470 | struct fec_priv *fec = dev_get_priv(dev); |
| 471 | #else |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 472 | struct fec_priv *fec = (struct fec_priv *)edev->priv; |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 473 | #endif |
Troy Kisky | 0111213 | 2012-02-07 14:08:46 +0000 | [diff] [blame] | 474 | int speed; |
Ye Li | e267091 | 2018-01-10 13:20:44 +0800 | [diff] [blame] | 475 | ulong addr, size; |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 476 | int i; |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 477 | |
| 478 | debug("fec_open: fec_open(dev)\n"); |
| 479 | /* full-duplex, heartbeat disabled */ |
| 480 | writel(1 << 2, &fec->eth->x_cntrl); |
| 481 | fec->rbd_index = 0; |
| 482 | |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 483 | /* Invalidate all descriptors */ |
| 484 | for (i = 0; i < FEC_RBD_NUM - 1; i++) |
| 485 | fec_rbd_clean(0, &fec->rbd_base[i]); |
| 486 | fec_rbd_clean(1, &fec->rbd_base[i]); |
| 487 | |
| 488 | /* Flush the descriptors into RAM */ |
| 489 | size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), |
| 490 | ARCH_DMA_MINALIGN); |
Ye Li | e267091 | 2018-01-10 13:20:44 +0800 | [diff] [blame] | 491 | addr = (ulong)fec->rbd_base; |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 492 | flush_dcache_range(addr, addr + size); |
| 493 | |
Troy Kisky | 0111213 | 2012-02-07 14:08:46 +0000 | [diff] [blame] | 494 | #ifdef FEC_QUIRK_ENET_MAC |
Jason Liu | bbcef6c | 2011-12-16 05:17:07 +0000 | [diff] [blame] | 495 | /* Enable ENET HW endian SWAP */ |
| 496 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP, |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 497 | &fec->eth->ecntrl); |
Jason Liu | bbcef6c | 2011-12-16 05:17:07 +0000 | [diff] [blame] | 498 | /* Enable ENET store and forward mode */ |
| 499 | writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD, |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 500 | &fec->eth->x_wmrk); |
Jason Liu | bbcef6c | 2011-12-16 05:17:07 +0000 | [diff] [blame] | 501 | #endif |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 502 | /* Enable FEC-Lite controller */ |
John Rigby | e650e49 | 2010-01-25 23:12:55 -0700 | [diff] [blame] | 503 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 504 | &fec->eth->ecntrl); |
| 505 | |
Fabio Estevam | 84c1f52 | 2013-09-13 00:36:27 -0300 | [diff] [blame] | 506 | #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) |
John Rigby | 99d5fed | 2010-01-25 23:12:57 -0700 | [diff] [blame] | 507 | udelay(100); |
John Rigby | 99d5fed | 2010-01-25 23:12:57 -0700 | [diff] [blame] | 508 | |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 509 | /* setup the MII gasket for RMII mode */ |
John Rigby | 99d5fed | 2010-01-25 23:12:57 -0700 | [diff] [blame] | 510 | /* disable the gasket */ |
| 511 | writew(0, &fec->eth->miigsk_enr); |
| 512 | |
| 513 | /* wait for the gasket to be disabled */ |
| 514 | while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) |
| 515 | udelay(2); |
| 516 | |
| 517 | /* configure gasket for RMII, 50 MHz, no loopback, and no echo */ |
| 518 | writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr); |
| 519 | |
| 520 | /* re-enable the gasket */ |
| 521 | writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr); |
| 522 | |
| 523 | /* wait until MII gasket is ready */ |
| 524 | int max_loops = 10; |
| 525 | while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) { |
| 526 | if (--max_loops <= 0) { |
| 527 | printf("WAIT for MII Gasket ready timed out\n"); |
| 528 | break; |
| 529 | } |
| 530 | } |
| 531 | #endif |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 532 | |
Troy Kisky | 2000c66 | 2012-02-07 14:08:47 +0000 | [diff] [blame] | 533 | #ifdef CONFIG_PHYLIB |
Troy Kisky | 2c42b3c | 2012-10-22 16:40:45 +0000 | [diff] [blame] | 534 | { |
Troy Kisky | 2000c66 | 2012-02-07 14:08:47 +0000 | [diff] [blame] | 535 | /* Start up the PHY */ |
Timur Tabi | 4238746 | 2012-07-09 08:52:43 +0000 | [diff] [blame] | 536 | int ret = phy_startup(fec->phydev); |
| 537 | |
| 538 | if (ret) { |
| 539 | printf("Could not initialize PHY %s\n", |
| 540 | fec->phydev->dev->name); |
| 541 | return ret; |
| 542 | } |
Troy Kisky | 2000c66 | 2012-02-07 14:08:47 +0000 | [diff] [blame] | 543 | speed = fec->phydev->speed; |
Troy Kisky | 2000c66 | 2012-02-07 14:08:47 +0000 | [diff] [blame] | 544 | } |
Hannes Schmelzer | 5a15c1a | 2016-06-22 12:07:14 +0200 | [diff] [blame] | 545 | #elif CONFIG_FEC_FIXED_SPEED |
| 546 | speed = CONFIG_FEC_FIXED_SPEED; |
Troy Kisky | 2000c66 | 2012-02-07 14:08:47 +0000 | [diff] [blame] | 547 | #else |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 548 | miiphy_wait_aneg(edev); |
Troy Kisky | 0111213 | 2012-02-07 14:08:46 +0000 | [diff] [blame] | 549 | speed = miiphy_speed(edev->name, fec->phy_id); |
Marek Vasut | edcd6c0 | 2011-09-16 01:13:47 +0200 | [diff] [blame] | 550 | miiphy_duplex(edev->name, fec->phy_id); |
Troy Kisky | 2000c66 | 2012-02-07 14:08:47 +0000 | [diff] [blame] | 551 | #endif |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 552 | |
Troy Kisky | 0111213 | 2012-02-07 14:08:46 +0000 | [diff] [blame] | 553 | #ifdef FEC_QUIRK_ENET_MAC |
| 554 | { |
| 555 | u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED; |
Alison Wang | 89d932a | 2013-05-27 22:55:43 +0000 | [diff] [blame] | 556 | u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T; |
Troy Kisky | 0111213 | 2012-02-07 14:08:46 +0000 | [diff] [blame] | 557 | if (speed == _1000BASET) |
| 558 | ecr |= FEC_ECNTRL_SPEED; |
| 559 | else if (speed != _100BASET) |
| 560 | rcr |= FEC_RCNTRL_RMII_10T; |
| 561 | writel(ecr, &fec->eth->ecntrl); |
| 562 | writel(rcr, &fec->eth->r_cntrl); |
| 563 | } |
| 564 | #endif |
| 565 | debug("%s:Speed=%i\n", __func__, speed); |
| 566 | |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 567 | /* Enable SmartDMA receive task */ |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 568 | fec_rx_task_enable(fec); |
| 569 | |
| 570 | udelay(100000); |
| 571 | return 0; |
| 572 | } |
| 573 | |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 574 | #ifdef CONFIG_DM_ETH |
| 575 | static int fecmxc_init(struct udevice *dev) |
| 576 | #else |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 577 | static int fec_init(struct eth_device *dev, bd_t *bd) |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 578 | #endif |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 579 | { |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 580 | #ifdef CONFIG_DM_ETH |
| 581 | struct fec_priv *fec = dev_get_priv(dev); |
| 582 | #else |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 583 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 584 | #endif |
Ye Li | e267091 | 2018-01-10 13:20:44 +0800 | [diff] [blame] | 585 | u8 *mib_ptr = (uint8_t *)&fec->eth->rmon_t_drop; |
| 586 | u8 *i; |
| 587 | ulong addr; |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 588 | |
John Rigby | a4a3055 | 2010-10-13 14:31:08 -0600 | [diff] [blame] | 589 | /* Initialize MAC address */ |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 590 | #ifdef CONFIG_DM_ETH |
| 591 | fecmxc_set_hwaddr(dev); |
| 592 | #else |
John Rigby | a4a3055 | 2010-10-13 14:31:08 -0600 | [diff] [blame] | 593 | fec_set_hwaddr(dev); |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 594 | #endif |
John Rigby | a4a3055 | 2010-10-13 14:31:08 -0600 | [diff] [blame] | 595 | |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 596 | /* Setup transmit descriptors, there are two in total. */ |
Marek Vasut | 0388045 | 2013-10-12 20:36:25 +0200 | [diff] [blame] | 597 | fec_tbd_init(fec); |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 598 | |
Marek Vasut | 0388045 | 2013-10-12 20:36:25 +0200 | [diff] [blame] | 599 | /* Setup receive descriptors. */ |
| 600 | fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE); |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 601 | |
Marek Vasut | 335cbd2 | 2012-05-01 11:09:41 +0000 | [diff] [blame] | 602 | fec_reg_setup(fec); |
Marek Vasut | b8f8856 | 2011-09-11 18:05:31 +0000 | [diff] [blame] | 603 | |
benoit.thebaudeau@advans | 551bb36 | 2012-07-19 02:12:58 +0000 | [diff] [blame] | 604 | if (fec->xcv_type != SEVENWIRE) |
Troy Kisky | 5e76265 | 2012-10-22 16:40:41 +0000 | [diff] [blame] | 605 | fec_mii_setspeed(fec->bus->priv); |
Marek Vasut | b8f8856 | 2011-09-11 18:05:31 +0000 | [diff] [blame] | 606 | |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 607 | /* Set Opcode/Pause Duration Register */ |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 608 | writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ |
| 609 | writel(0x2, &fec->eth->x_wmrk); |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 610 | |
| 611 | /* Set multicast address filter */ |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 612 | writel(0x00000000, &fec->eth->gaddr1); |
| 613 | writel(0x00000000, &fec->eth->gaddr2); |
| 614 | |
Peng Fan | bf8e58b | 2018-01-10 13:20:43 +0800 | [diff] [blame] | 615 | /* Do not access reserved register */ |
Peng Fan | 6146a08 | 2019-04-15 05:18:33 +0000 | [diff] [blame] | 616 | if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m()) { |
Peng Fan | 13433fd | 2015-08-12 17:46:51 +0800 | [diff] [blame] | 617 | /* clear MIB RAM */ |
| 618 | for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) |
| 619 | writel(0, i); |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 620 | |
Peng Fan | 13433fd | 2015-08-12 17:46:51 +0800 | [diff] [blame] | 621 | /* FIFO receive start register */ |
| 622 | writel(0x520, &fec->eth->r_fstart); |
| 623 | } |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 624 | |
| 625 | /* size and address of each buffer */ |
| 626 | writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr); |
Ye Li | e267091 | 2018-01-10 13:20:44 +0800 | [diff] [blame] | 627 | |
| 628 | addr = (ulong)fec->tbd_base; |
| 629 | writel((uint32_t)addr, &fec->eth->etdsr); |
| 630 | |
| 631 | addr = (ulong)fec->rbd_base; |
| 632 | writel((uint32_t)addr, &fec->eth->erdsr); |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 633 | |
Troy Kisky | 2000c66 | 2012-02-07 14:08:47 +0000 | [diff] [blame] | 634 | #ifndef CONFIG_PHYLIB |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 635 | if (fec->xcv_type != SEVENWIRE) |
| 636 | miiphy_restart_aneg(dev); |
Troy Kisky | 2000c66 | 2012-02-07 14:08:47 +0000 | [diff] [blame] | 637 | #endif |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 638 | fec_open(dev); |
| 639 | return 0; |
| 640 | } |
| 641 | |
| 642 | /** |
| 643 | * Halt the FEC engine |
| 644 | * @param[in] dev Our device to handle |
| 645 | */ |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 646 | #ifdef CONFIG_DM_ETH |
| 647 | static void fecmxc_halt(struct udevice *dev) |
| 648 | #else |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 649 | static void fec_halt(struct eth_device *dev) |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 650 | #endif |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 651 | { |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 652 | #ifdef CONFIG_DM_ETH |
| 653 | struct fec_priv *fec = dev_get_priv(dev); |
| 654 | #else |
Marek Vasut | edcd6c0 | 2011-09-16 01:13:47 +0200 | [diff] [blame] | 655 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 656 | #endif |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 657 | int counter = 0xffff; |
| 658 | |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 659 | /* issue graceful stop command to the FEC transmitter if necessary */ |
John Rigby | e650e49 | 2010-01-25 23:12:55 -0700 | [diff] [blame] | 660 | writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl), |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 661 | &fec->eth->x_cntrl); |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 662 | |
| 663 | debug("eth_halt: wait for stop regs\n"); |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 664 | /* wait for graceful stop to register */ |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 665 | while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA))) |
John Rigby | e650e49 | 2010-01-25 23:12:55 -0700 | [diff] [blame] | 666 | udelay(1); |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 667 | |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 668 | /* Disable SmartDMA tasks */ |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 669 | fec_tx_task_disable(fec); |
| 670 | fec_rx_task_disable(fec); |
| 671 | |
| 672 | /* |
| 673 | * Disable the Ethernet Controller |
| 674 | * Note: this will also reset the BD index counter! |
| 675 | */ |
John Rigby | 99d5fed | 2010-01-25 23:12:57 -0700 | [diff] [blame] | 676 | writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 677 | &fec->eth->ecntrl); |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 678 | fec->rbd_index = 0; |
| 679 | fec->tbd_index = 0; |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 680 | debug("eth_halt: done\n"); |
| 681 | } |
| 682 | |
| 683 | /** |
| 684 | * Transmit one frame |
| 685 | * @param[in] dev Our ethernet device to handle |
| 686 | * @param[in] packet Pointer to the data to be transmitted |
| 687 | * @param[in] length Data count in bytes |
| 688 | * @return 0 on success |
| 689 | */ |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 690 | #ifdef CONFIG_DM_ETH |
| 691 | static int fecmxc_send(struct udevice *dev, void *packet, int length) |
| 692 | #else |
Joe Hershberger | 7c31bd1 | 2012-05-21 14:45:27 +0000 | [diff] [blame] | 693 | static int fec_send(struct eth_device *dev, void *packet, int length) |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 694 | #endif |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 695 | { |
| 696 | unsigned int status; |
Ye Li | e267091 | 2018-01-10 13:20:44 +0800 | [diff] [blame] | 697 | u32 size; |
| 698 | ulong addr, end; |
Marek Vasut | 5f1631d | 2012-08-29 03:49:49 +0000 | [diff] [blame] | 699 | int timeout = FEC_XFER_TIMEOUT; |
| 700 | int ret = 0; |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 701 | |
| 702 | /* |
| 703 | * This routine transmits one frame. This routine only accepts |
| 704 | * 6-byte Ethernet addresses. |
| 705 | */ |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 706 | #ifdef CONFIG_DM_ETH |
| 707 | struct fec_priv *fec = dev_get_priv(dev); |
| 708 | #else |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 709 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 710 | #endif |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 711 | |
| 712 | /* |
| 713 | * Check for valid length of data. |
| 714 | */ |
| 715 | if ((length > 1500) || (length <= 0)) { |
Stefano Babic | 889f2e2 | 2010-02-01 14:51:30 +0100 | [diff] [blame] | 716 | printf("Payload (%d) too large\n", length); |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 717 | return -1; |
| 718 | } |
| 719 | |
| 720 | /* |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 721 | * Setup the transmit buffer. We are always using the first buffer for |
| 722 | * transmission, the second will be empty and only used to stop the DMA |
| 723 | * engine. We also flush the packet to RAM here to avoid cache trouble. |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 724 | */ |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 725 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
Marek Vasut | 6a5fd4c | 2011-11-08 23:18:10 +0000 | [diff] [blame] | 726 | swap_packet((uint32_t *)packet, length); |
| 727 | #endif |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 728 | |
Ye Li | e267091 | 2018-01-10 13:20:44 +0800 | [diff] [blame] | 729 | addr = (ulong)packet; |
Marek Vasut | 4325d24 | 2012-08-26 10:19:21 +0000 | [diff] [blame] | 730 | end = roundup(addr + length, ARCH_DMA_MINALIGN); |
| 731 | addr &= ~(ARCH_DMA_MINALIGN - 1); |
| 732 | flush_dcache_range(addr, end); |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 733 | |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 734 | writew(length, &fec->tbd_base[fec->tbd_index].data_length); |
Ye Li | e267091 | 2018-01-10 13:20:44 +0800 | [diff] [blame] | 735 | writel((uint32_t)addr, &fec->tbd_base[fec->tbd_index].data_pointer); |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 736 | |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 737 | /* |
| 738 | * update BD's status now |
| 739 | * This block: |
| 740 | * - is always the last in a chain (means no chain) |
| 741 | * - should transmitt the CRC |
| 742 | * - might be the last BD in the list, so the address counter should |
| 743 | * wrap (-> keep the WRAP flag) |
| 744 | */ |
| 745 | status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP; |
| 746 | status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; |
| 747 | writew(status, &fec->tbd_base[fec->tbd_index].status); |
| 748 | |
| 749 | /* |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 750 | * Flush data cache. This code flushes both TX descriptors to RAM. |
| 751 | * After this code, the descriptors will be safely in RAM and we |
| 752 | * can start DMA. |
| 753 | */ |
| 754 | size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); |
Ye Li | e267091 | 2018-01-10 13:20:44 +0800 | [diff] [blame] | 755 | addr = (ulong)fec->tbd_base; |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 756 | flush_dcache_range(addr, addr + size); |
| 757 | |
| 758 | /* |
Marek Vasut | d521b3c | 2013-07-12 01:03:04 +0200 | [diff] [blame] | 759 | * Below we read the DMA descriptor's last four bytes back from the |
| 760 | * DRAM. This is important in order to make sure that all WRITE |
| 761 | * operations on the bus that were triggered by previous cache FLUSH |
| 762 | * have completed. |
| 763 | * |
| 764 | * Otherwise, on MX28, it is possible to observe a corruption of the |
| 765 | * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM |
| 766 | * for the bus structure of MX28. The scenario is as follows: |
| 767 | * |
| 768 | * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going |
| 769 | * to DRAM due to flush_dcache_range() |
| 770 | * 2) ARM core writes the FEC registers via AHB_ARB2 |
| 771 | * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3 |
| 772 | * |
| 773 | * Note that 2) does sometimes finish before 1) due to reordering of |
| 774 | * WRITE accesses on the AHB bus, therefore triggering 3) before the |
| 775 | * DMA descriptor is fully written into DRAM. This results in occasional |
| 776 | * corruption of the DMA descriptor. |
| 777 | */ |
| 778 | readl(addr + size - 4); |
| 779 | |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 780 | /* Enable SmartDMA transmit task */ |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 781 | fec_tx_task_enable(fec); |
| 782 | |
| 783 | /* |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 784 | * Wait until frame is sent. On each turn of the wait cycle, we must |
| 785 | * invalidate data cache to see what's really in RAM. Also, we need |
| 786 | * barrier here. |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 787 | */ |
Marek Vasut | 9bf7bf0 | 2012-08-29 03:49:50 +0000 | [diff] [blame] | 788 | while (--timeout) { |
Marek Vasut | c1582c0 | 2012-08-29 03:49:51 +0000 | [diff] [blame] | 789 | if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR)) |
Marek Vasut | 5f1631d | 2012-08-29 03:49:49 +0000 | [diff] [blame] | 790 | break; |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 791 | } |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 792 | |
Fabio Estevam | c34e99f | 2014-08-25 13:34:17 -0300 | [diff] [blame] | 793 | if (!timeout) { |
Marek Vasut | 9bf7bf0 | 2012-08-29 03:49:50 +0000 | [diff] [blame] | 794 | ret = -EINVAL; |
Fabio Estevam | c34e99f | 2014-08-25 13:34:17 -0300 | [diff] [blame] | 795 | goto out; |
| 796 | } |
Marek Vasut | 9bf7bf0 | 2012-08-29 03:49:50 +0000 | [diff] [blame] | 797 | |
Fabio Estevam | c34e99f | 2014-08-25 13:34:17 -0300 | [diff] [blame] | 798 | /* |
| 799 | * The TDAR bit is cleared when the descriptors are all out from TX |
| 800 | * but on mx6solox we noticed that the READY bit is still not cleared |
| 801 | * right after TDAR. |
| 802 | * These are two distinct signals, and in IC simulation, we found that |
| 803 | * TDAR always gets cleared prior than the READY bit of last BD becomes |
| 804 | * cleared. |
| 805 | * In mx6solox, we use a later version of FEC IP. It looks like that |
| 806 | * this intrinsic behaviour of TDAR bit has changed in this newer FEC |
| 807 | * version. |
| 808 | * |
| 809 | * Fix this by polling the READY bit of BD after the TDAR polling, |
| 810 | * which covers the mx6solox case and does not harm the other SoCs. |
| 811 | */ |
| 812 | timeout = FEC_XFER_TIMEOUT; |
| 813 | while (--timeout) { |
| 814 | invalidate_dcache_range(addr, addr + size); |
| 815 | if (!(readw(&fec->tbd_base[fec->tbd_index].status) & |
| 816 | FEC_TBD_READY)) |
| 817 | break; |
| 818 | } |
| 819 | |
| 820 | if (!timeout) |
Marek Vasut | 9bf7bf0 | 2012-08-29 03:49:50 +0000 | [diff] [blame] | 821 | ret = -EINVAL; |
| 822 | |
Fabio Estevam | c34e99f | 2014-08-25 13:34:17 -0300 | [diff] [blame] | 823 | out: |
Marek Vasut | 9bf7bf0 | 2012-08-29 03:49:50 +0000 | [diff] [blame] | 824 | debug("fec_send: status 0x%x index %d ret %i\n", |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 825 | readw(&fec->tbd_base[fec->tbd_index].status), |
| 826 | fec->tbd_index, ret); |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 827 | /* for next transmission use the other buffer */ |
| 828 | if (fec->tbd_index) |
| 829 | fec->tbd_index = 0; |
| 830 | else |
| 831 | fec->tbd_index = 1; |
| 832 | |
Marek Vasut | 5f1631d | 2012-08-29 03:49:49 +0000 | [diff] [blame] | 833 | return ret; |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 834 | } |
| 835 | |
| 836 | /** |
| 837 | * Pull one frame from the card |
| 838 | * @param[in] dev Our ethernet device to handle |
| 839 | * @return Length of packet read |
| 840 | */ |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 841 | #ifdef CONFIG_DM_ETH |
| 842 | static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp) |
| 843 | #else |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 844 | static int fec_recv(struct eth_device *dev) |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 845 | #endif |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 846 | { |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 847 | #ifdef CONFIG_DM_ETH |
| 848 | struct fec_priv *fec = dev_get_priv(dev); |
| 849 | #else |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 850 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 851 | #endif |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 852 | struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index]; |
| 853 | unsigned long ievent; |
| 854 | int frame_length, len = 0; |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 855 | uint16_t bd_status; |
Ye Li | e267091 | 2018-01-10 13:20:44 +0800 | [diff] [blame] | 856 | ulong addr, size, end; |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 857 | int i; |
Ye Li | bd7e538 | 2018-03-28 20:54:11 +0800 | [diff] [blame] | 858 | |
| 859 | #ifdef CONFIG_DM_ETH |
| 860 | *packetp = memalign(ARCH_DMA_MINALIGN, FEC_MAX_PKT_SIZE); |
| 861 | if (*packetp == 0) { |
| 862 | printf("%s: error allocating packetp\n", __func__); |
| 863 | return -ENOMEM; |
| 864 | } |
| 865 | #else |
Fabio Estevam | cc95608 | 2013-09-17 23:13:10 -0300 | [diff] [blame] | 866 | ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE); |
Ye Li | bd7e538 | 2018-03-28 20:54:11 +0800 | [diff] [blame] | 867 | #endif |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 868 | |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 869 | /* Check if any critical events have happened */ |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 870 | ievent = readl(&fec->eth->ievent); |
| 871 | writel(ievent, &fec->eth->ievent); |
Marek Vasut | 478e2d0 | 2011-10-24 23:40:03 +0000 | [diff] [blame] | 872 | debug("fec_recv: ievent 0x%lx\n", ievent); |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 873 | if (ievent & FEC_IEVENT_BABR) { |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 874 | #ifdef CONFIG_DM_ETH |
| 875 | fecmxc_halt(dev); |
| 876 | fecmxc_init(dev); |
| 877 | #else |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 878 | fec_halt(dev); |
| 879 | fec_init(dev, fec->bd); |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 880 | #endif |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 881 | printf("some error: 0x%08lx\n", ievent); |
| 882 | return 0; |
| 883 | } |
| 884 | if (ievent & FEC_IEVENT_HBERR) { |
| 885 | /* Heartbeat error */ |
| 886 | writel(0x00000001 | readl(&fec->eth->x_cntrl), |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 887 | &fec->eth->x_cntrl); |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 888 | } |
| 889 | if (ievent & FEC_IEVENT_GRA) { |
| 890 | /* Graceful stop complete */ |
| 891 | if (readl(&fec->eth->x_cntrl) & 0x00000001) { |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 892 | #ifdef CONFIG_DM_ETH |
| 893 | fecmxc_halt(dev); |
| 894 | #else |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 895 | fec_halt(dev); |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 896 | #endif |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 897 | writel(~0x00000001 & readl(&fec->eth->x_cntrl), |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 898 | &fec->eth->x_cntrl); |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 899 | #ifdef CONFIG_DM_ETH |
| 900 | fecmxc_init(dev); |
| 901 | #else |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 902 | fec_init(dev, fec->bd); |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 903 | #endif |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 904 | } |
| 905 | } |
| 906 | |
| 907 | /* |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 908 | * Read the buffer status. Before the status can be read, the data cache |
| 909 | * must be invalidated, because the data in RAM might have been changed |
| 910 | * by DMA. The descriptors are properly aligned to cachelines so there's |
| 911 | * no need to worry they'd overlap. |
| 912 | * |
| 913 | * WARNING: By invalidating the descriptor here, we also invalidate |
| 914 | * the descriptors surrounding this one. Therefore we can NOT change the |
| 915 | * contents of this descriptor nor the surrounding ones. The problem is |
| 916 | * that in order to mark the descriptor as processed, we need to change |
| 917 | * the descriptor. The solution is to mark the whole cache line when all |
| 918 | * descriptors in the cache line are processed. |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 919 | */ |
Ye Li | e267091 | 2018-01-10 13:20:44 +0800 | [diff] [blame] | 920 | addr = (ulong)rbd; |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 921 | addr &= ~(ARCH_DMA_MINALIGN - 1); |
| 922 | size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN); |
| 923 | invalidate_dcache_range(addr, addr + size); |
| 924 | |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 925 | bd_status = readw(&rbd->status); |
| 926 | debug("fec_recv: status 0x%x\n", bd_status); |
| 927 | |
| 928 | if (!(bd_status & FEC_RBD_EMPTY)) { |
| 929 | if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) && |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 930 | ((readw(&rbd->data_length) - 4) > 14)) { |
| 931 | /* Get buffer address and size */ |
Albert ARIBAUD \(3ADEV\) | 1342030 | 2015-06-19 14:18:27 +0200 | [diff] [blame] | 932 | addr = readl(&rbd->data_pointer); |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 933 | frame_length = readw(&rbd->data_length) - 4; |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 934 | /* Invalidate data cache over the buffer */ |
Marek Vasut | 4325d24 | 2012-08-26 10:19:21 +0000 | [diff] [blame] | 935 | end = roundup(addr + frame_length, ARCH_DMA_MINALIGN); |
| 936 | addr &= ~(ARCH_DMA_MINALIGN - 1); |
| 937 | invalidate_dcache_range(addr, end); |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 938 | |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 939 | /* Fill the buffer and pass it to upper layers */ |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 940 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
Albert ARIBAUD \(3ADEV\) | 1342030 | 2015-06-19 14:18:27 +0200 | [diff] [blame] | 941 | swap_packet((uint32_t *)addr, frame_length); |
Marek Vasut | 6a5fd4c | 2011-11-08 23:18:10 +0000 | [diff] [blame] | 942 | #endif |
Ye Li | bd7e538 | 2018-03-28 20:54:11 +0800 | [diff] [blame] | 943 | |
| 944 | #ifdef CONFIG_DM_ETH |
| 945 | memcpy(*packetp, (char *)addr, frame_length); |
| 946 | #else |
Albert ARIBAUD \(3ADEV\) | 1342030 | 2015-06-19 14:18:27 +0200 | [diff] [blame] | 947 | memcpy(buff, (char *)addr, frame_length); |
Joe Hershberger | 9f09a36 | 2015-04-08 01:41:06 -0500 | [diff] [blame] | 948 | net_process_received_packet(buff, frame_length); |
Ye Li | bd7e538 | 2018-03-28 20:54:11 +0800 | [diff] [blame] | 949 | #endif |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 950 | len = frame_length; |
| 951 | } else { |
| 952 | if (bd_status & FEC_RBD_ERR) |
Ye Li | e267091 | 2018-01-10 13:20:44 +0800 | [diff] [blame] | 953 | debug("error frame: 0x%08lx 0x%08x\n", |
| 954 | addr, bd_status); |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 955 | } |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 956 | |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 957 | /* |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 958 | * Free the current buffer, restart the engine and move forward |
| 959 | * to the next buffer. Here we check if the whole cacheline of |
| 960 | * descriptors was already processed and if so, we mark it free |
| 961 | * as whole. |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 962 | */ |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 963 | size = RXDESC_PER_CACHELINE - 1; |
| 964 | if ((fec->rbd_index & size) == size) { |
| 965 | i = fec->rbd_index - size; |
Ye Li | e267091 | 2018-01-10 13:20:44 +0800 | [diff] [blame] | 966 | addr = (ulong)&fec->rbd_base[i]; |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 967 | for (; i <= fec->rbd_index ; i++) { |
| 968 | fec_rbd_clean(i == (FEC_RBD_NUM - 1), |
| 969 | &fec->rbd_base[i]); |
| 970 | } |
| 971 | flush_dcache_range(addr, |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 972 | addr + ARCH_DMA_MINALIGN); |
Eric Nelson | 3d2f727 | 2012-03-15 18:33:25 +0000 | [diff] [blame] | 973 | } |
| 974 | |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 975 | fec_rx_task_enable(fec); |
| 976 | fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM; |
| 977 | } |
| 978 | debug("fec_recv: stop\n"); |
| 979 | |
| 980 | return len; |
| 981 | } |
| 982 | |
Troy Kisky | 4c2ddec | 2012-10-22 16:40:44 +0000 | [diff] [blame] | 983 | static void fec_set_dev_name(char *dest, int dev_id) |
| 984 | { |
| 985 | sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id); |
| 986 | } |
| 987 | |
Marek Vasut | 0388045 | 2013-10-12 20:36:25 +0200 | [diff] [blame] | 988 | static int fec_alloc_descs(struct fec_priv *fec) |
| 989 | { |
| 990 | unsigned int size; |
| 991 | int i; |
| 992 | uint8_t *data; |
Ye Li | e267091 | 2018-01-10 13:20:44 +0800 | [diff] [blame] | 993 | ulong addr; |
Marek Vasut | 0388045 | 2013-10-12 20:36:25 +0200 | [diff] [blame] | 994 | |
| 995 | /* Allocate TX descriptors. */ |
| 996 | size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); |
| 997 | fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size); |
| 998 | if (!fec->tbd_base) |
| 999 | goto err_tx; |
| 1000 | |
| 1001 | /* Allocate RX descriptors. */ |
| 1002 | size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); |
| 1003 | fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size); |
| 1004 | if (!fec->rbd_base) |
| 1005 | goto err_rx; |
| 1006 | |
| 1007 | memset(fec->rbd_base, 0, size); |
| 1008 | |
| 1009 | /* Allocate RX buffers. */ |
| 1010 | |
| 1011 | /* Maximum RX buffer size. */ |
Fabio Estevam | 8b798b2 | 2014-08-25 13:34:16 -0300 | [diff] [blame] | 1012 | size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN); |
Marek Vasut | 0388045 | 2013-10-12 20:36:25 +0200 | [diff] [blame] | 1013 | for (i = 0; i < FEC_RBD_NUM; i++) { |
Fabio Estevam | 8b798b2 | 2014-08-25 13:34:16 -0300 | [diff] [blame] | 1014 | data = memalign(FEC_DMA_RX_MINALIGN, size); |
Marek Vasut | 0388045 | 2013-10-12 20:36:25 +0200 | [diff] [blame] | 1015 | if (!data) { |
| 1016 | printf("%s: error allocating rxbuf %d\n", __func__, i); |
| 1017 | goto err_ring; |
| 1018 | } |
| 1019 | |
| 1020 | memset(data, 0, size); |
| 1021 | |
Ye Li | e267091 | 2018-01-10 13:20:44 +0800 | [diff] [blame] | 1022 | addr = (ulong)data; |
| 1023 | fec->rbd_base[i].data_pointer = (uint32_t)addr; |
Marek Vasut | 0388045 | 2013-10-12 20:36:25 +0200 | [diff] [blame] | 1024 | fec->rbd_base[i].status = FEC_RBD_EMPTY; |
| 1025 | fec->rbd_base[i].data_length = 0; |
| 1026 | /* Flush the buffer to memory. */ |
Ye Li | e267091 | 2018-01-10 13:20:44 +0800 | [diff] [blame] | 1027 | flush_dcache_range(addr, addr + size); |
Marek Vasut | 0388045 | 2013-10-12 20:36:25 +0200 | [diff] [blame] | 1028 | } |
| 1029 | |
| 1030 | /* Mark the last RBD to close the ring. */ |
| 1031 | fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY; |
| 1032 | |
| 1033 | fec->rbd_index = 0; |
| 1034 | fec->tbd_index = 0; |
| 1035 | |
| 1036 | return 0; |
| 1037 | |
| 1038 | err_ring: |
Ye Li | e267091 | 2018-01-10 13:20:44 +0800 | [diff] [blame] | 1039 | for (; i >= 0; i--) { |
| 1040 | addr = fec->rbd_base[i].data_pointer; |
| 1041 | free((void *)addr); |
| 1042 | } |
Marek Vasut | 0388045 | 2013-10-12 20:36:25 +0200 | [diff] [blame] | 1043 | free(fec->rbd_base); |
| 1044 | err_rx: |
| 1045 | free(fec->tbd_base); |
| 1046 | err_tx: |
| 1047 | return -ENOMEM; |
| 1048 | } |
| 1049 | |
| 1050 | static void fec_free_descs(struct fec_priv *fec) |
| 1051 | { |
| 1052 | int i; |
Ye Li | e267091 | 2018-01-10 13:20:44 +0800 | [diff] [blame] | 1053 | ulong addr; |
Marek Vasut | 0388045 | 2013-10-12 20:36:25 +0200 | [diff] [blame] | 1054 | |
Ye Li | e267091 | 2018-01-10 13:20:44 +0800 | [diff] [blame] | 1055 | for (i = 0; i < FEC_RBD_NUM; i++) { |
| 1056 | addr = fec->rbd_base[i].data_pointer; |
| 1057 | free((void *)addr); |
| 1058 | } |
Marek Vasut | 0388045 | 2013-10-12 20:36:25 +0200 | [diff] [blame] | 1059 | free(fec->rbd_base); |
| 1060 | free(fec->tbd_base); |
| 1061 | } |
| 1062 | |
Peng Fan | 0c59c4f | 2018-03-28 20:54:12 +0800 | [diff] [blame] | 1063 | struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id) |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 1064 | { |
Peng Fan | 0c59c4f | 2018-03-28 20:54:12 +0800 | [diff] [blame] | 1065 | struct ethernet_regs *eth = (struct ethernet_regs *)base_addr; |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 1066 | struct mii_dev *bus; |
| 1067 | int ret; |
| 1068 | |
| 1069 | bus = mdio_alloc(); |
| 1070 | if (!bus) { |
| 1071 | printf("mdio_alloc failed\n"); |
| 1072 | return NULL; |
| 1073 | } |
| 1074 | bus->read = fec_phy_read; |
| 1075 | bus->write = fec_phy_write; |
| 1076 | bus->priv = eth; |
| 1077 | fec_set_dev_name(bus->name, dev_id); |
| 1078 | |
| 1079 | ret = mdio_register(bus); |
| 1080 | if (ret) { |
| 1081 | printf("mdio_register failed\n"); |
| 1082 | free(bus); |
| 1083 | return NULL; |
| 1084 | } |
| 1085 | fec_mii_setspeed(eth); |
| 1086 | return bus; |
| 1087 | } |
| 1088 | |
| 1089 | #ifndef CONFIG_DM_ETH |
Troy Kisky | dce4def | 2012-10-22 16:40:46 +0000 | [diff] [blame] | 1090 | #ifdef CONFIG_PHYLIB |
| 1091 | int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, |
| 1092 | struct mii_dev *bus, struct phy_device *phydev) |
| 1093 | #else |
| 1094 | static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, |
| 1095 | struct mii_dev *bus, int phy_id) |
| 1096 | #endif |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 1097 | { |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 1098 | struct eth_device *edev; |
Marek Vasut | edcd6c0 | 2011-09-16 01:13:47 +0200 | [diff] [blame] | 1099 | struct fec_priv *fec; |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 1100 | unsigned char ethaddr[6]; |
Andy Duan | 8f8e458 | 2017-04-10 19:44:35 +0800 | [diff] [blame] | 1101 | char mac[16]; |
Marek Vasut | 43b1030 | 2011-09-11 18:05:37 +0000 | [diff] [blame] | 1102 | uint32_t start; |
| 1103 | int ret = 0; |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 1104 | |
| 1105 | /* create and fill edev struct */ |
| 1106 | edev = (struct eth_device *)malloc(sizeof(struct eth_device)); |
| 1107 | if (!edev) { |
Marek Vasut | edcd6c0 | 2011-09-16 01:13:47 +0200 | [diff] [blame] | 1108 | puts("fec_mxc: not enough malloc memory for eth_device\n"); |
Marek Vasut | 43b1030 | 2011-09-11 18:05:37 +0000 | [diff] [blame] | 1109 | ret = -ENOMEM; |
| 1110 | goto err1; |
Marek Vasut | edcd6c0 | 2011-09-16 01:13:47 +0200 | [diff] [blame] | 1111 | } |
| 1112 | |
| 1113 | fec = (struct fec_priv *)malloc(sizeof(struct fec_priv)); |
| 1114 | if (!fec) { |
| 1115 | puts("fec_mxc: not enough malloc memory for fec_priv\n"); |
Marek Vasut | 43b1030 | 2011-09-11 18:05:37 +0000 | [diff] [blame] | 1116 | ret = -ENOMEM; |
| 1117 | goto err2; |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 1118 | } |
Marek Vasut | edcd6c0 | 2011-09-16 01:13:47 +0200 | [diff] [blame] | 1119 | |
Nobuhiro Iwamatsu | 1843c5b | 2010-10-19 14:03:42 +0900 | [diff] [blame] | 1120 | memset(edev, 0, sizeof(*edev)); |
Marek Vasut | edcd6c0 | 2011-09-16 01:13:47 +0200 | [diff] [blame] | 1121 | memset(fec, 0, sizeof(*fec)); |
| 1122 | |
Marek Vasut | 0388045 | 2013-10-12 20:36:25 +0200 | [diff] [blame] | 1123 | ret = fec_alloc_descs(fec); |
| 1124 | if (ret) |
| 1125 | goto err3; |
| 1126 | |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 1127 | edev->priv = fec; |
| 1128 | edev->init = fec_init; |
| 1129 | edev->send = fec_send; |
| 1130 | edev->recv = fec_recv; |
| 1131 | edev->halt = fec_halt; |
Heiko Schocher | 9ada5e6 | 2010-04-27 07:43:52 +0200 | [diff] [blame] | 1132 | edev->write_hwaddr = fec_set_hwaddr; |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 1133 | |
Ye Li | e267091 | 2018-01-10 13:20:44 +0800 | [diff] [blame] | 1134 | fec->eth = (struct ethernet_regs *)(ulong)base_addr; |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 1135 | fec->bd = bd; |
| 1136 | |
Marek Vasut | dbb4fce | 2011-09-11 18:05:33 +0000 | [diff] [blame] | 1137 | fec->xcv_type = CONFIG_FEC_XCV_TYPE; |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 1138 | |
| 1139 | /* Reset chip. */ |
John Rigby | e650e49 | 2010-01-25 23:12:55 -0700 | [diff] [blame] | 1140 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl); |
Marek Vasut | 43b1030 | 2011-09-11 18:05:37 +0000 | [diff] [blame] | 1141 | start = get_timer(0); |
| 1142 | while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) { |
| 1143 | if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { |
Vagrant Cascadian | 259b1fb | 2016-10-23 20:45:19 -0700 | [diff] [blame] | 1144 | printf("FEC MXC: Timeout resetting chip\n"); |
Marek Vasut | 0388045 | 2013-10-12 20:36:25 +0200 | [diff] [blame] | 1145 | goto err4; |
Marek Vasut | 43b1030 | 2011-09-11 18:05:37 +0000 | [diff] [blame] | 1146 | } |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 1147 | udelay(10); |
Marek Vasut | 43b1030 | 2011-09-11 18:05:37 +0000 | [diff] [blame] | 1148 | } |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 1149 | |
Marek Vasut | 335cbd2 | 2012-05-01 11:09:41 +0000 | [diff] [blame] | 1150 | fec_reg_setup(fec); |
Troy Kisky | 4c2ddec | 2012-10-22 16:40:44 +0000 | [diff] [blame] | 1151 | fec_set_dev_name(edev->name, dev_id); |
| 1152 | fec->dev_id = (dev_id == -1) ? 0 : dev_id; |
Troy Kisky | dce4def | 2012-10-22 16:40:46 +0000 | [diff] [blame] | 1153 | fec->bus = bus; |
| 1154 | fec_mii_setspeed(bus->priv); |
| 1155 | #ifdef CONFIG_PHYLIB |
| 1156 | fec->phydev = phydev; |
| 1157 | phy_connect_dev(phydev, edev); |
| 1158 | /* Configure phy */ |
| 1159 | phy_config(phydev); |
| 1160 | #else |
Marek Vasut | edcd6c0 | 2011-09-16 01:13:47 +0200 | [diff] [blame] | 1161 | fec->phy_id = phy_id; |
Troy Kisky | dce4def | 2012-10-22 16:40:46 +0000 | [diff] [blame] | 1162 | #endif |
| 1163 | eth_register(edev); |
Andy Duan | 8f8e458 | 2017-04-10 19:44:35 +0800 | [diff] [blame] | 1164 | /* only support one eth device, the index number pointed by dev_id */ |
| 1165 | edev->index = fec->dev_id; |
Troy Kisky | dce4def | 2012-10-22 16:40:46 +0000 | [diff] [blame] | 1166 | |
Andy Duan | 0eaaf83 | 2017-04-10 19:44:34 +0800 | [diff] [blame] | 1167 | if (fec_get_hwaddr(fec->dev_id, ethaddr) == 0) { |
| 1168 | debug("got MAC%d address from fuse: %pM\n", fec->dev_id, ethaddr); |
Troy Kisky | dce4def | 2012-10-22 16:40:46 +0000 | [diff] [blame] | 1169 | memcpy(edev->enetaddr, ethaddr, 6); |
Andy Duan | 8f8e458 | 2017-04-10 19:44:35 +0800 | [diff] [blame] | 1170 | if (fec->dev_id) |
| 1171 | sprintf(mac, "eth%daddr", fec->dev_id); |
| 1172 | else |
| 1173 | strcpy(mac, "ethaddr"); |
Simon Glass | 64b723f | 2017-08-03 12:22:12 -0600 | [diff] [blame] | 1174 | if (!env_get(mac)) |
Simon Glass | 8551d55 | 2017-08-03 12:22:11 -0600 | [diff] [blame] | 1175 | eth_env_set_enetaddr(mac, ethaddr); |
Troy Kisky | dce4def | 2012-10-22 16:40:46 +0000 | [diff] [blame] | 1176 | } |
| 1177 | return ret; |
Marek Vasut | 0388045 | 2013-10-12 20:36:25 +0200 | [diff] [blame] | 1178 | err4: |
| 1179 | fec_free_descs(fec); |
Troy Kisky | dce4def | 2012-10-22 16:40:46 +0000 | [diff] [blame] | 1180 | err3: |
| 1181 | free(fec); |
| 1182 | err2: |
| 1183 | free(edev); |
| 1184 | err1: |
| 1185 | return ret; |
| 1186 | } |
| 1187 | |
Troy Kisky | dce4def | 2012-10-22 16:40:46 +0000 | [diff] [blame] | 1188 | int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr) |
| 1189 | { |
| 1190 | uint32_t base_mii; |
| 1191 | struct mii_dev *bus = NULL; |
| 1192 | #ifdef CONFIG_PHYLIB |
| 1193 | struct phy_device *phydev = NULL; |
| 1194 | #endif |
| 1195 | int ret; |
| 1196 | |
Peng Fan | a65e036 | 2018-03-28 20:54:14 +0800 | [diff] [blame] | 1197 | #ifdef CONFIG_FEC_MXC_MDIO_BASE |
Troy Kisky | 2000c66 | 2012-02-07 14:08:47 +0000 | [diff] [blame] | 1198 | /* |
| 1199 | * The i.MX28 has two ethernet interfaces, but they are not equal. |
| 1200 | * Only the first one can access the MDIO bus. |
| 1201 | */ |
Peng Fan | a65e036 | 2018-03-28 20:54:14 +0800 | [diff] [blame] | 1202 | base_mii = CONFIG_FEC_MXC_MDIO_BASE; |
Troy Kisky | 2000c66 | 2012-02-07 14:08:47 +0000 | [diff] [blame] | 1203 | #else |
Troy Kisky | dce4def | 2012-10-22 16:40:46 +0000 | [diff] [blame] | 1204 | base_mii = addr; |
Troy Kisky | 2000c66 | 2012-02-07 14:08:47 +0000 | [diff] [blame] | 1205 | #endif |
Troy Kisky | dce4def | 2012-10-22 16:40:46 +0000 | [diff] [blame] | 1206 | debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr); |
| 1207 | bus = fec_get_miibus(base_mii, dev_id); |
| 1208 | if (!bus) |
| 1209 | return -ENOMEM; |
Troy Kisky | 2c42b3c | 2012-10-22 16:40:45 +0000 | [diff] [blame] | 1210 | #ifdef CONFIG_PHYLIB |
Troy Kisky | dce4def | 2012-10-22 16:40:46 +0000 | [diff] [blame] | 1211 | phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII); |
Troy Kisky | 2c42b3c | 2012-10-22 16:40:45 +0000 | [diff] [blame] | 1212 | if (!phydev) { |
Måns Rullgård | c6e4a86 | 2015-12-08 15:38:46 +0000 | [diff] [blame] | 1213 | mdio_unregister(bus); |
Troy Kisky | 2c42b3c | 2012-10-22 16:40:45 +0000 | [diff] [blame] | 1214 | free(bus); |
Troy Kisky | dce4def | 2012-10-22 16:40:46 +0000 | [diff] [blame] | 1215 | return -ENOMEM; |
Troy Kisky | 2c42b3c | 2012-10-22 16:40:45 +0000 | [diff] [blame] | 1216 | } |
Troy Kisky | dce4def | 2012-10-22 16:40:46 +0000 | [diff] [blame] | 1217 | ret = fec_probe(bd, dev_id, addr, bus, phydev); |
| 1218 | #else |
| 1219 | ret = fec_probe(bd, dev_id, addr, bus, phy_id); |
Troy Kisky | 2c42b3c | 2012-10-22 16:40:45 +0000 | [diff] [blame] | 1220 | #endif |
Troy Kisky | dce4def | 2012-10-22 16:40:46 +0000 | [diff] [blame] | 1221 | if (ret) { |
| 1222 | #ifdef CONFIG_PHYLIB |
| 1223 | free(phydev); |
| 1224 | #endif |
Måns Rullgård | c6e4a86 | 2015-12-08 15:38:46 +0000 | [diff] [blame] | 1225 | mdio_unregister(bus); |
Troy Kisky | dce4def | 2012-10-22 16:40:46 +0000 | [diff] [blame] | 1226 | free(bus); |
| 1227 | } |
Marek Vasut | 43b1030 | 2011-09-11 18:05:37 +0000 | [diff] [blame] | 1228 | return ret; |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 1229 | } |
| 1230 | |
Troy Kisky | 4e0eae6 | 2012-10-22 16:40:42 +0000 | [diff] [blame] | 1231 | #ifdef CONFIG_FEC_MXC_PHYADDR |
| 1232 | int fecmxc_initialize(bd_t *bd) |
| 1233 | { |
| 1234 | return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR, |
| 1235 | IMX_FEC_BASE); |
Ilya Yanok | e93a4a5 | 2009-07-21 19:32:21 +0400 | [diff] [blame] | 1236 | } |
Troy Kisky | 4e0eae6 | 2012-10-22 16:40:42 +0000 | [diff] [blame] | 1237 | #endif |
Marek Vasut | 539ecee | 2011-09-11 18:05:36 +0000 | [diff] [blame] | 1238 | |
Troy Kisky | 2000c66 | 2012-02-07 14:08:47 +0000 | [diff] [blame] | 1239 | #ifndef CONFIG_PHYLIB |
Marek Vasut | 539ecee | 2011-09-11 18:05:36 +0000 | [diff] [blame] | 1240 | int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)) |
| 1241 | { |
| 1242 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
| 1243 | fec->mii_postcall = cb; |
| 1244 | return 0; |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 1245 | } |
| 1246 | #endif |
| 1247 | |
| 1248 | #else |
| 1249 | |
Jagan Teki | 87e7f35 | 2016-12-06 00:00:51 +0100 | [diff] [blame] | 1250 | static int fecmxc_read_rom_hwaddr(struct udevice *dev) |
| 1251 | { |
| 1252 | struct fec_priv *priv = dev_get_priv(dev); |
| 1253 | struct eth_pdata *pdata = dev_get_platdata(dev); |
| 1254 | |
| 1255 | return fec_get_hwaddr(priv->dev_id, pdata->enetaddr); |
| 1256 | } |
| 1257 | |
Ye Li | bd7e538 | 2018-03-28 20:54:11 +0800 | [diff] [blame] | 1258 | static int fecmxc_free_pkt(struct udevice *dev, uchar *packet, int length) |
| 1259 | { |
| 1260 | if (packet) |
| 1261 | free(packet); |
| 1262 | |
| 1263 | return 0; |
| 1264 | } |
| 1265 | |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 1266 | static const struct eth_ops fecmxc_ops = { |
| 1267 | .start = fecmxc_init, |
| 1268 | .send = fecmxc_send, |
| 1269 | .recv = fecmxc_recv, |
Ye Li | bd7e538 | 2018-03-28 20:54:11 +0800 | [diff] [blame] | 1270 | .free_pkt = fecmxc_free_pkt, |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 1271 | .stop = fecmxc_halt, |
| 1272 | .write_hwaddr = fecmxc_set_hwaddr, |
Jagan Teki | 87e7f35 | 2016-12-06 00:00:51 +0100 | [diff] [blame] | 1273 | .read_rom_hwaddr = fecmxc_read_rom_hwaddr, |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 1274 | }; |
| 1275 | |
Martyn Welch | d1ac23f | 2018-12-11 11:34:45 +0000 | [diff] [blame] | 1276 | static int device_get_phy_addr(struct udevice *dev) |
| 1277 | { |
| 1278 | struct ofnode_phandle_args phandle_args; |
| 1279 | int reg; |
| 1280 | |
| 1281 | if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, |
| 1282 | &phandle_args)) { |
| 1283 | debug("Failed to find phy-handle"); |
| 1284 | return -ENODEV; |
| 1285 | } |
| 1286 | |
| 1287 | reg = ofnode_read_u32_default(phandle_args.node, "reg", 0); |
| 1288 | |
| 1289 | return reg; |
| 1290 | } |
| 1291 | |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 1292 | static int fec_phy_init(struct fec_priv *priv, struct udevice *dev) |
| 1293 | { |
| 1294 | struct phy_device *phydev; |
Martyn Welch | d1ac23f | 2018-12-11 11:34:45 +0000 | [diff] [blame] | 1295 | int addr; |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 1296 | |
Martyn Welch | d1ac23f | 2018-12-11 11:34:45 +0000 | [diff] [blame] | 1297 | addr = device_get_phy_addr(dev); |
Lukasz Majewski | 07b75a3 | 2018-04-15 21:45:54 +0200 | [diff] [blame] | 1298 | #ifdef CONFIG_FEC_MXC_PHYADDR |
Hannes Schmelzer | f769430 | 2019-02-15 10:30:18 +0100 | [diff] [blame] | 1299 | addr = CONFIG_FEC_MXC_PHYADDR; |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 1300 | #endif |
| 1301 | |
Hannes Schmelzer | f769430 | 2019-02-15 10:30:18 +0100 | [diff] [blame] | 1302 | phydev = phy_connect(priv->bus, addr, dev, priv->interface); |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 1303 | if (!phydev) |
| 1304 | return -ENODEV; |
| 1305 | |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 1306 | priv->phydev = phydev; |
| 1307 | phy_config(phydev); |
| 1308 | |
| 1309 | return 0; |
| 1310 | } |
| 1311 | |
Michael Trimarchi | 0e5cccf | 2018-06-17 15:22:39 +0200 | [diff] [blame] | 1312 | #ifdef CONFIG_DM_GPIO |
| 1313 | /* FEC GPIO reset */ |
| 1314 | static void fec_gpio_reset(struct fec_priv *priv) |
| 1315 | { |
| 1316 | debug("fec_gpio_reset: fec_gpio_reset(dev)\n"); |
| 1317 | if (dm_gpio_is_valid(&priv->phy_reset_gpio)) { |
| 1318 | dm_gpio_set_value(&priv->phy_reset_gpio, 1); |
Martin Fuzzey | 9c3f97a | 2018-10-04 19:59:18 +0200 | [diff] [blame] | 1319 | mdelay(priv->reset_delay); |
Michael Trimarchi | 0e5cccf | 2018-06-17 15:22:39 +0200 | [diff] [blame] | 1320 | dm_gpio_set_value(&priv->phy_reset_gpio, 0); |
Andrejs Cainikovs | 24b6aac | 2019-03-01 13:27:59 +0000 | [diff] [blame] | 1321 | if (priv->reset_post_delay) |
| 1322 | mdelay(priv->reset_post_delay); |
Michael Trimarchi | 0e5cccf | 2018-06-17 15:22:39 +0200 | [diff] [blame] | 1323 | } |
| 1324 | } |
| 1325 | #endif |
| 1326 | |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 1327 | static int fecmxc_probe(struct udevice *dev) |
| 1328 | { |
| 1329 | struct eth_pdata *pdata = dev_get_platdata(dev); |
| 1330 | struct fec_priv *priv = dev_get_priv(dev); |
| 1331 | struct mii_dev *bus = NULL; |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 1332 | uint32_t start; |
| 1333 | int ret; |
| 1334 | |
Anatolij Gustschin | b71fc5e | 2018-10-18 16:15:11 +0200 | [diff] [blame] | 1335 | if (IS_ENABLED(CONFIG_IMX8)) { |
| 1336 | ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk); |
| 1337 | if (ret < 0) { |
| 1338 | debug("Can't get FEC ipg clk: %d\n", ret); |
| 1339 | return ret; |
| 1340 | } |
| 1341 | ret = clk_enable(&priv->ipg_clk); |
| 1342 | if (ret < 0) { |
| 1343 | debug("Can't enable FEC ipg clk: %d\n", ret); |
| 1344 | return ret; |
| 1345 | } |
| 1346 | |
| 1347 | priv->clk_rate = clk_get_rate(&priv->ipg_clk); |
Peng Fan | dcf5e1b | 2019-10-25 09:48:02 +0000 | [diff] [blame] | 1348 | } else if (CONFIG_IS_ENABLED(CLK_CCF)) { |
| 1349 | ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk); |
| 1350 | if (ret < 0) { |
| 1351 | debug("Can't get FEC ipg clk: %d\n", ret); |
| 1352 | return ret; |
| 1353 | } |
| 1354 | ret = clk_enable(&priv->ipg_clk); |
| 1355 | if(ret) |
| 1356 | return ret; |
| 1357 | |
| 1358 | ret = clk_get_by_name(dev, "ahb", &priv->ahb_clk); |
| 1359 | if (ret < 0) { |
| 1360 | debug("Can't get FEC ahb clk: %d\n", ret); |
| 1361 | return ret; |
| 1362 | } |
| 1363 | ret = clk_enable(&priv->ahb_clk); |
| 1364 | if (ret) |
| 1365 | return ret; |
| 1366 | |
| 1367 | ret = clk_get_by_name(dev, "enet_out", &priv->clk_enet_out); |
| 1368 | if (!ret) { |
| 1369 | ret = clk_enable(&priv->clk_enet_out); |
| 1370 | if (ret) |
| 1371 | return ret; |
| 1372 | } |
| 1373 | |
| 1374 | ret = clk_get_by_name(dev, "enet_clk_ref", &priv->clk_ref); |
| 1375 | if (!ret) { |
| 1376 | ret = clk_enable(&priv->clk_ref); |
| 1377 | if (ret) |
| 1378 | return ret; |
| 1379 | } |
| 1380 | |
| 1381 | ret = clk_get_by_name(dev, "ptp", &priv->clk_ptp); |
| 1382 | if (!ret) { |
| 1383 | ret = clk_enable(&priv->clk_ptp); |
| 1384 | if (ret) |
| 1385 | return ret; |
| 1386 | } |
| 1387 | |
| 1388 | priv->clk_rate = clk_get_rate(&priv->ipg_clk); |
Anatolij Gustschin | b71fc5e | 2018-10-18 16:15:11 +0200 | [diff] [blame] | 1389 | } |
| 1390 | |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 1391 | ret = fec_alloc_descs(priv); |
| 1392 | if (ret) |
| 1393 | return ret; |
| 1394 | |
Martin Fuzzey | 9a6a2c9 | 2018-10-04 19:59:20 +0200 | [diff] [blame] | 1395 | #ifdef CONFIG_DM_REGULATOR |
| 1396 | if (priv->phy_supply) { |
Adam Ford | b3301b6 | 2019-01-15 11:26:48 -0600 | [diff] [blame] | 1397 | ret = regulator_set_enable(priv->phy_supply, true); |
Martin Fuzzey | 9a6a2c9 | 2018-10-04 19:59:20 +0200 | [diff] [blame] | 1398 | if (ret) { |
| 1399 | printf("%s: Error enabling phy supply\n", dev->name); |
| 1400 | return ret; |
| 1401 | } |
| 1402 | } |
| 1403 | #endif |
| 1404 | |
Michael Trimarchi | 0e5cccf | 2018-06-17 15:22:39 +0200 | [diff] [blame] | 1405 | #ifdef CONFIG_DM_GPIO |
| 1406 | fec_gpio_reset(priv); |
| 1407 | #endif |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 1408 | /* Reset chip. */ |
Jagan Teki | c6cd8d5 | 2016-12-06 00:00:50 +0100 | [diff] [blame] | 1409 | writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET, |
| 1410 | &priv->eth->ecntrl); |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 1411 | start = get_timer(0); |
| 1412 | while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) { |
| 1413 | if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { |
| 1414 | printf("FEC MXC: Timeout reseting chip\n"); |
| 1415 | goto err_timeout; |
| 1416 | } |
| 1417 | udelay(10); |
| 1418 | } |
| 1419 | |
| 1420 | fec_reg_setup(priv); |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 1421 | |
Peng Fan | bd3e8cb | 2018-03-28 20:54:13 +0800 | [diff] [blame] | 1422 | priv->dev_id = dev->seq; |
Peng Fan | a65e036 | 2018-03-28 20:54:14 +0800 | [diff] [blame] | 1423 | #ifdef CONFIG_FEC_MXC_MDIO_BASE |
| 1424 | bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE, dev->seq); |
| 1425 | #else |
Peng Fan | bd3e8cb | 2018-03-28 20:54:13 +0800 | [diff] [blame] | 1426 | bus = fec_get_miibus((ulong)priv->eth, dev->seq); |
Peng Fan | a65e036 | 2018-03-28 20:54:14 +0800 | [diff] [blame] | 1427 | #endif |
Lothar Waßmann | d33e9ee | 2017-06-27 15:23:16 +0200 | [diff] [blame] | 1428 | if (!bus) { |
| 1429 | ret = -ENOMEM; |
| 1430 | goto err_mii; |
| 1431 | } |
| 1432 | |
| 1433 | priv->bus = bus; |
Lothar Waßmann | d33e9ee | 2017-06-27 15:23:16 +0200 | [diff] [blame] | 1434 | priv->interface = pdata->phy_interface; |
Martin Fuzzey | f08eb3d | 2018-10-04 19:59:21 +0200 | [diff] [blame] | 1435 | switch (priv->interface) { |
| 1436 | case PHY_INTERFACE_MODE_MII: |
| 1437 | priv->xcv_type = MII100; |
| 1438 | break; |
| 1439 | case PHY_INTERFACE_MODE_RMII: |
| 1440 | priv->xcv_type = RMII; |
| 1441 | break; |
| 1442 | case PHY_INTERFACE_MODE_RGMII: |
| 1443 | case PHY_INTERFACE_MODE_RGMII_ID: |
| 1444 | case PHY_INTERFACE_MODE_RGMII_RXID: |
| 1445 | case PHY_INTERFACE_MODE_RGMII_TXID: |
| 1446 | priv->xcv_type = RGMII; |
| 1447 | break; |
| 1448 | default: |
| 1449 | priv->xcv_type = CONFIG_FEC_XCV_TYPE; |
| 1450 | printf("Unsupported interface type %d defaulting to %d\n", |
| 1451 | priv->interface, priv->xcv_type); |
| 1452 | break; |
| 1453 | } |
| 1454 | |
Lothar Waßmann | d33e9ee | 2017-06-27 15:23:16 +0200 | [diff] [blame] | 1455 | ret = fec_phy_init(priv, dev); |
| 1456 | if (ret) |
| 1457 | goto err_phy; |
| 1458 | |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 1459 | return 0; |
| 1460 | |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 1461 | err_phy: |
| 1462 | mdio_unregister(bus); |
| 1463 | free(bus); |
| 1464 | err_mii: |
Ye Li | 5fa556c | 2018-03-28 20:54:16 +0800 | [diff] [blame] | 1465 | err_timeout: |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 1466 | fec_free_descs(priv); |
| 1467 | return ret; |
Marek Vasut | 539ecee | 2011-09-11 18:05:36 +0000 | [diff] [blame] | 1468 | } |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 1469 | |
| 1470 | static int fecmxc_remove(struct udevice *dev) |
| 1471 | { |
| 1472 | struct fec_priv *priv = dev_get_priv(dev); |
| 1473 | |
| 1474 | free(priv->phydev); |
| 1475 | fec_free_descs(priv); |
| 1476 | mdio_unregister(priv->bus); |
| 1477 | mdio_free(priv->bus); |
| 1478 | |
Martin Fuzzey | 9a6a2c9 | 2018-10-04 19:59:20 +0200 | [diff] [blame] | 1479 | #ifdef CONFIG_DM_REGULATOR |
| 1480 | if (priv->phy_supply) |
| 1481 | regulator_set_enable(priv->phy_supply, false); |
| 1482 | #endif |
| 1483 | |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 1484 | return 0; |
| 1485 | } |
| 1486 | |
| 1487 | static int fecmxc_ofdata_to_platdata(struct udevice *dev) |
| 1488 | { |
Michael Trimarchi | 0e5cccf | 2018-06-17 15:22:39 +0200 | [diff] [blame] | 1489 | int ret = 0; |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 1490 | struct eth_pdata *pdata = dev_get_platdata(dev); |
| 1491 | struct fec_priv *priv = dev_get_priv(dev); |
| 1492 | const char *phy_mode; |
| 1493 | |
Simon Glass | ba1dea4 | 2017-05-17 17:18:05 -0600 | [diff] [blame] | 1494 | pdata->iobase = (phys_addr_t)devfdt_get_addr(dev); |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 1495 | priv->eth = (struct ethernet_regs *)pdata->iobase; |
| 1496 | |
| 1497 | pdata->phy_interface = -1; |
Simon Glass | dd79d6e | 2017-01-17 16:52:55 -0700 | [diff] [blame] | 1498 | phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", |
| 1499 | NULL); |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 1500 | if (phy_mode) |
| 1501 | pdata->phy_interface = phy_get_interface_by_name(phy_mode); |
| 1502 | if (pdata->phy_interface == -1) { |
| 1503 | debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); |
| 1504 | return -EINVAL; |
| 1505 | } |
| 1506 | |
Martin Fuzzey | 9a6a2c9 | 2018-10-04 19:59:20 +0200 | [diff] [blame] | 1507 | #ifdef CONFIG_DM_REGULATOR |
| 1508 | device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply); |
| 1509 | #endif |
| 1510 | |
Michael Trimarchi | 0e5cccf | 2018-06-17 15:22:39 +0200 | [diff] [blame] | 1511 | #ifdef CONFIG_DM_GPIO |
| 1512 | ret = gpio_request_by_name(dev, "phy-reset-gpios", 0, |
Martin Fuzzey | 185e3b8 | 2018-10-04 19:59:19 +0200 | [diff] [blame] | 1513 | &priv->phy_reset_gpio, GPIOD_IS_OUT); |
| 1514 | if (ret < 0) |
| 1515 | return 0; /* property is optional, don't return error! */ |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 1516 | |
Martin Fuzzey | 185e3b8 | 2018-10-04 19:59:19 +0200 | [diff] [blame] | 1517 | priv->reset_delay = dev_read_u32_default(dev, "phy-reset-duration", 1); |
Michael Trimarchi | 0e5cccf | 2018-06-17 15:22:39 +0200 | [diff] [blame] | 1518 | if (priv->reset_delay > 1000) { |
Martin Fuzzey | 185e3b8 | 2018-10-04 19:59:19 +0200 | [diff] [blame] | 1519 | printf("FEC MXC: phy reset duration should be <= 1000ms\n"); |
| 1520 | /* property value wrong, use default value */ |
| 1521 | priv->reset_delay = 1; |
Michael Trimarchi | 0e5cccf | 2018-06-17 15:22:39 +0200 | [diff] [blame] | 1522 | } |
Andrejs Cainikovs | 24b6aac | 2019-03-01 13:27:59 +0000 | [diff] [blame] | 1523 | |
| 1524 | priv->reset_post_delay = dev_read_u32_default(dev, |
| 1525 | "phy-reset-post-delay", |
| 1526 | 0); |
| 1527 | if (priv->reset_post_delay > 1000) { |
| 1528 | printf("FEC MXC: phy reset post delay should be <= 1000ms\n"); |
| 1529 | /* property value wrong, use default value */ |
| 1530 | priv->reset_post_delay = 0; |
| 1531 | } |
Michael Trimarchi | 0e5cccf | 2018-06-17 15:22:39 +0200 | [diff] [blame] | 1532 | #endif |
| 1533 | |
Martin Fuzzey | 185e3b8 | 2018-10-04 19:59:19 +0200 | [diff] [blame] | 1534 | return 0; |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 1535 | } |
| 1536 | |
| 1537 | static const struct udevice_id fecmxc_ids[] = { |
Lukasz Majewski | 8a8f5a6 | 2019-06-19 17:31:03 +0200 | [diff] [blame] | 1538 | { .compatible = "fsl,imx28-fec" }, |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 1539 | { .compatible = "fsl,imx6q-fec" }, |
Peng Fan | 5640630 | 2018-03-28 20:54:15 +0800 | [diff] [blame] | 1540 | { .compatible = "fsl,imx6sl-fec" }, |
| 1541 | { .compatible = "fsl,imx6sx-fec" }, |
| 1542 | { .compatible = "fsl,imx6ul-fec" }, |
Lukasz Majewski | 4731122 | 2018-04-15 21:54:22 +0200 | [diff] [blame] | 1543 | { .compatible = "fsl,imx53-fec" }, |
Anatolij Gustschin | b71fc5e | 2018-10-18 16:15:11 +0200 | [diff] [blame] | 1544 | { .compatible = "fsl,imx7d-fec" }, |
Lukasz Majewski | 6b94b0e | 2019-02-13 22:46:38 +0100 | [diff] [blame] | 1545 | { .compatible = "fsl,mvf600-fec" }, |
Jagan Teki | 484f021 | 2016-12-06 00:00:49 +0100 | [diff] [blame] | 1546 | { } |
| 1547 | }; |
| 1548 | |
| 1549 | U_BOOT_DRIVER(fecmxc_gem) = { |
| 1550 | .name = "fecmxc", |
| 1551 | .id = UCLASS_ETH, |
| 1552 | .of_match = fecmxc_ids, |
| 1553 | .ofdata_to_platdata = fecmxc_ofdata_to_platdata, |
| 1554 | .probe = fecmxc_probe, |
| 1555 | .remove = fecmxc_remove, |
| 1556 | .ops = &fecmxc_ops, |
| 1557 | .priv_auto_alloc_size = sizeof(struct fec_priv), |
| 1558 | .platdata_auto_alloc_size = sizeof(struct eth_pdata), |
| 1559 | }; |
Troy Kisky | 2000c66 | 2012-02-07 14:08:47 +0000 | [diff] [blame] | 1560 | #endif |