| commit | 13433fd6e1f369f09a310aed9161d34e9da1e484 | [log] [tgz] |
|---|---|---|
| author | Peng Fan <Peng.Fan@freescale.com> | Wed Aug 12 17:46:51 2015 +0800 |
| committer | Stefano Babic <sbabic@denx.de> | Wed Sep 02 15:29:14 2015 +0200 |
| tree | fe3c76a86e3b12ebc28eb407b9e24a5d405b5d05 | |
| parent | 967a83be7c77559d43bac80e2aa6e43b3c060f49 [diff] |
net: fec: do not access reserved register for i.MX6UL The MIB RAM and FIFO receive start register does not exist on i.MX6UL. Accessing these register will cause enet not work well. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Fugang Duan <B38611@freescale.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Stefano Babic <sbabic@denx.de>