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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenk591dda52002-11-18 00:14:45 +00002/*
3 * (C) Copyright 2002
Albert ARIBAUD60fbc8d2011-08-04 18:45:45 +02004 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
wdenk591dda52002-11-18 00:14:45 +00005 */
6
wdenkef5fe752003-03-12 10:41:04 +00007#ifndef _U_BOOT_I386_H_
8#define _U_BOOT_I386_H_ 1
wdenk591dda52002-11-18 00:14:45 +00009
Simon Glass162b09c2017-05-17 08:22:56 -060010struct global_data;
11
Bin Menga3c9fb02015-06-07 11:33:13 +080012extern char gdt_rom[];
13
wdenk591dda52002-11-18 00:14:45 +000014/* cpu/.../cpu.c */
Simon Glass19a8b122014-11-06 13:20:06 -070015int arch_cpu_init(void);
Graeme Russ121931c2011-02-12 15:11:35 +110016int x86_cpu_init_f(void);
Graeme Russ078395c2009-11-24 20:04:21 +110017int cpu_init_f(void);
Simon Glass162b09c2017-05-17 08:22:56 -060018void setup_gdt(struct global_data *id, u64 *gdt_addr);
Bin Menga3c9fb02015-06-07 11:33:13 +080019/*
20 * Setup FSP execution environment GDT to use the one we used in
21 * arch/x86/cpu/start16.S and reload the segment registers.
22 */
23void setup_fsp_gdt(void);
Graeme Russ6e256002011-12-27 22:46:43 +110024int init_cache(void);
Gabe Black846d08e2012-10-20 12:33:10 +000025int cleanup_before_linux(void);
Graeme Russ7679d1f2009-02-24 21:14:45 +110026
27/* cpu/.../timer.c */
28void timer_isr(void *);
29typedef void (timer_fnc_t) (void);
30int register_timer_isr (timer_fnc_t *isr_func);
Simon Glass11d7a5b2013-04-17 16:13:36 +000031unsigned long get_tbclk_mhz(void);
32void timer_set_base(uint64_t base);
Bin Mengb29a08c2015-10-22 19:13:30 -070033int i8254_init(void);
Graeme Russ7679d1f2009-02-24 21:14:45 +110034
Graeme Russ77290ee2009-02-24 21:13:40 +110035/* cpu/.../interrupts.c */
36int cpu_init_interrupts(void);
37
Simon Glass83374332014-11-06 13:20:08 -070038int cleanup_before_linux(void);
39int x86_cleanup_before_linux(void);
40void x86_enable_caches(void);
41void x86_disable_caches(void);
42int x86_init_cache(void);
Simon Glass83374332014-11-06 13:20:08 -070043ulong board_get_usable_ram_top(ulong total_size);
Simon Glass543bb142014-11-10 18:00:26 -070044int default_print_cpuinfo(void);
Simon Glass83374332014-11-06 13:20:08 -070045
Simon Glass4661c2c2015-01-27 22:13:42 -070046/* Set up a UART which can be used with printch(), printhex8(), etc. */
Stefan Roesea377b7c2016-01-19 14:24:12 +010047int setup_internal_uart(int enable);
Simon Glass4661c2c2015-01-27 22:13:42 -070048
Graeme Russa8d06b42010-04-24 00:05:48 +100049void setup_pcat_compatibility(void);
50
wdenkabda5ca2003-05-31 18:35:21 +000051void isa_unmap_rom(u32 addr);
52u32 isa_map_rom(u32 bus_addr, int size);
53
Graeme Russcbfce1d2011-04-13 19:43:28 +100054/* arch/x86/lib/... */
wdenkabda5ca2003-05-31 18:35:21 +000055int video_bios_init(void);
wdenk591dda52002-11-18 00:14:45 +000056
Bin Mengcf200302017-04-21 07:24:39 -070057/* arch/x86/lib/fsp/... */
58
59/**
60 * fsp_save_s3_stack() - save stack address to CMOS for next S3 boot
61 *
62 * At the end of pre-relocation phase, save the new stack address
63 * to CMOS and use it as the stack on next S3 boot for fsp_init()
64 * continuation function.
65 *
66 * @return: 0 if OK, -ve on error
67 */
68int fsp_save_s3_stack(void);
69
Graeme Russd7755b42012-01-01 15:06:39 +110070void board_init_f_r_trampoline(ulong) __attribute__ ((noreturn));
71void board_init_f_r(void) __attribute__ ((noreturn));
wdenk591dda52002-11-18 00:14:45 +000072
Bin Meng15305362015-04-24 18:10:06 +080073int arch_misc_init(void);
74
Vadim Bendebury1d82bac2012-10-23 18:04:32 +000075/* Read the time stamp counter */
Simon Glass42081ce2013-06-11 11:14:52 -070076static inline __attribute__((no_instrument_function)) uint64_t rdtsc(void)
Vadim Bendebury1d82bac2012-10-23 18:04:32 +000077{
78 uint32_t high, low;
79 __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high));
80 return (((uint64_t)high) << 32) | low;
81}
82
83/* board/... */
84void timer_set_tsc_base(uint64_t new_base);
85uint64_t timer_get_tsc(void);
86
Simon Glass268eefd2014-11-12 22:42:28 -070087void quick_ram_check(void);
88
Simon Glass1b6b9b92014-12-29 19:32:24 -070089#define PCI_VGA_RAM_IMAGE_START 0xc0000
90
wdenkef5fe752003-03-12 10:41:04 +000091#endif /* _U_BOOT_I386_H_ */