blob: 22a79da2333eb2161ef5ee69aaf40c5f800e38d7 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Stefan Roesed987ea62014-11-07 13:50:31 +01002/*
3 * Designware master SPI core controller driver
4 *
5 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
Sean Andersondebbff82020-10-16 18:57:51 -04006 * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
Stefan Roesed987ea62014-11-07 13:50:31 +01007 *
Stefan Roese571e2a42014-11-16 12:47:01 +01008 * Very loosely based on the Linux driver:
9 * drivers/spi/spi-dw.c, which is:
Stefan Roesed987ea62014-11-07 13:50:31 +010010 * Copyright (c) 2009, Intel Corporation.
Stefan Roesed987ea62014-11-07 13:50:31 +010011 */
12
Sean Anderson0dfb3ac2020-10-16 18:57:44 -040013#define LOG_CATEGORY UCLASS_SPI
Tom Riniabb9a042024-05-18 20:20:43 -060014#include <common.h>
Eugeniy Paltsev8b841e32017-12-28 15:09:03 +030015#include <clk.h>
Stefan Roesed987ea62014-11-07 13:50:31 +010016#include <dm.h>
Sean Anderson16edba32020-10-16 18:57:53 -040017#include <dm/device_compat.h>
Stefan Roesed987ea62014-11-07 13:50:31 +010018#include <errno.h>
Stefan Roesed987ea62014-11-07 13:50:31 +010019#include <fdtdec.h>
Sean Anderson16edba32020-10-16 18:57:53 -040020#include <log.h>
21#include <malloc.h>
Ley Foon Tanfc3382d2018-09-07 14:25:29 +080022#include <reset.h>
Sean Anderson16edba32020-10-16 18:57:53 -040023#include <spi.h>
24#include <spi-mem.h>
25#include <asm/io.h>
26#include <asm-generic/gpio.h>
Sean Andersondebbff82020-10-16 18:57:51 -040027#include <linux/bitfield.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060028#include <linux/bitops.h>
Stefan Roesed987ea62014-11-07 13:50:31 +010029#include <linux/compat.h>
Eugeniy Paltsev7215ad22018-03-22 13:50:43 +030030#include <linux/iopoll.h>
Sean Anderson16edba32020-10-16 18:57:53 -040031#include <linux/sizes.h>
Stefan Roesed987ea62014-11-07 13:50:31 +010032
Stefan Roesed987ea62014-11-07 13:50:31 +010033/* Register offsets */
Sean Anderson75ea2f62020-10-16 18:57:47 -040034#define DW_SPI_CTRLR0 0x00
35#define DW_SPI_CTRLR1 0x04
Stefan Roesed987ea62014-11-07 13:50:31 +010036#define DW_SPI_SSIENR 0x08
37#define DW_SPI_MWCR 0x0c
38#define DW_SPI_SER 0x10
39#define DW_SPI_BAUDR 0x14
Sean Anderson75ea2f62020-10-16 18:57:47 -040040#define DW_SPI_TXFTLR 0x18
41#define DW_SPI_RXFTLR 0x1c
Stefan Roesed987ea62014-11-07 13:50:31 +010042#define DW_SPI_TXFLR 0x20
43#define DW_SPI_RXFLR 0x24
44#define DW_SPI_SR 0x28
45#define DW_SPI_IMR 0x2c
46#define DW_SPI_ISR 0x30
47#define DW_SPI_RISR 0x34
48#define DW_SPI_TXOICR 0x38
49#define DW_SPI_RXOICR 0x3c
50#define DW_SPI_RXUICR 0x40
51#define DW_SPI_MSTICR 0x44
52#define DW_SPI_ICR 0x48
53#define DW_SPI_DMACR 0x4c
54#define DW_SPI_DMATDLR 0x50
55#define DW_SPI_DMARDLR 0x54
56#define DW_SPI_IDR 0x58
57#define DW_SPI_VERSION 0x5c
58#define DW_SPI_DR 0x60
59
60/* Bit fields in CTRLR0 */
Sean Andersondebbff82020-10-16 18:57:51 -040061/*
62 * Only present when SSI_MAX_XFER_SIZE=16. This is the default, and the only
63 * option before version 3.23a.
64 */
65#define CTRLR0_DFS_MASK GENMASK(3, 0)
66
67#define CTRLR0_FRF_MASK GENMASK(5, 4)
68#define CTRLR0_FRF_SPI 0x0
69#define CTRLR0_FRF_SSP 0x1
70#define CTRLR0_FRF_MICROWIRE 0x2
71#define CTRLR0_FRF_RESV 0x3
Stefan Roesed987ea62014-11-07 13:50:31 +010072
Sean Andersondebbff82020-10-16 18:57:51 -040073#define CTRLR0_MODE_MASK GENMASK(7, 6)
74#define CTRLR0_MODE_SCPH 0x1
75#define CTRLR0_MODE_SCPOL 0x2
Stefan Roesed987ea62014-11-07 13:50:31 +010076
Sean Andersondebbff82020-10-16 18:57:51 -040077#define CTRLR0_TMOD_MASK GENMASK(9, 8)
78#define CTRLR0_TMOD_TR 0x0 /* xmit & recv */
79#define CTRLR0_TMOD_TO 0x1 /* xmit only */
80#define CTRLR0_TMOD_RO 0x2 /* recv only */
81#define CTRLR0_TMOD_EPROMREAD 0x3 /* eeprom read mode */
Stefan Roesed987ea62014-11-07 13:50:31 +010082
Sean Andersondebbff82020-10-16 18:57:51 -040083#define CTRLR0_SLVOE_OFFSET 10
84#define CTRLR0_SRL_OFFSET 11
85#define CTRLR0_CFS_MASK GENMASK(15, 12)
Stefan Roesed987ea62014-11-07 13:50:31 +010086
Sean Andersondebbff82020-10-16 18:57:51 -040087/* Only present when SSI_MAX_XFER_SIZE=32 */
88#define CTRLR0_DFS_32_MASK GENMASK(20, 16)
Stefan Roesed987ea62014-11-07 13:50:31 +010089
Sean Andersondebbff82020-10-16 18:57:51 -040090/* The next field is only present on versions after 4.00a */
91#define CTRLR0_SPI_FRF_MASK GENMASK(22, 21)
92#define CTRLR0_SPI_FRF_BYTE 0x0
93#define CTRLR0_SPI_FRF_DUAL 0x1
94#define CTRLR0_SPI_FRF_QUAD 0x2
Stefan Roesed987ea62014-11-07 13:50:31 +010095
Sean Andersondebbff82020-10-16 18:57:51 -040096/* Bit fields in CTRLR0 based on DWC_ssi_databook.pdf v1.01a */
97#define DWC_SSI_CTRLR0_DFS_MASK GENMASK(4, 0)
98#define DWC_SSI_CTRLR0_FRF_MASK GENMASK(7, 6)
99#define DWC_SSI_CTRLR0_MODE_MASK GENMASK(9, 8)
100#define DWC_SSI_CTRLR0_TMOD_MASK GENMASK(11, 10)
101#define DWC_SSI_CTRLR0_SRL_OFFSET 13
102#define DWC_SSI_CTRLR0_SPI_FRF_MASK GENMASK(23, 22)
Stefan Roesed987ea62014-11-07 13:50:31 +0100103
104/* Bit fields in SR, 7 bits */
Jagan Tekifac44912015-10-23 01:01:36 +0530105#define SR_MASK GENMASK(6, 0) /* cover 7 bits */
Jagan Tekib17746d2015-10-23 01:36:23 +0530106#define SR_BUSY BIT(0)
107#define SR_TF_NOT_FULL BIT(1)
108#define SR_TF_EMPT BIT(2)
109#define SR_RF_NOT_EMPT BIT(3)
110#define SR_RF_FULL BIT(4)
111#define SR_TX_ERR BIT(5)
112#define SR_DCOL BIT(6)
Stefan Roesed987ea62014-11-07 13:50:31 +0100113
Maksim Kiselev6cf56182023-12-21 13:13:30 +0300114/* Bit field in RISR */
115#define RISR_INT_RXOI BIT(3)
116
Stefan Roese571e2a42014-11-16 12:47:01 +0100117#define RX_TIMEOUT 1000 /* timeout in ms */
Stefan Roesed987ea62014-11-07 13:50:31 +0100118
Simon Glassb75b15b2020-12-03 16:55:23 -0700119struct dw_spi_plat {
Stefan Roesed987ea62014-11-07 13:50:31 +0100120 s32 frequency; /* Default clock frequency, -1 for none */
121 void __iomem *regs;
122};
123
124struct dw_spi_priv {
Eugeniy Paltsev8b841e32017-12-28 15:09:03 +0300125 struct clk clk;
Sean Andersone11c0b12020-10-16 18:57:49 -0400126 struct reset_ctl_bulk resets;
Eugeniy Paltseva7b4de12018-03-22 13:50:46 +0300127 struct gpio_desc cs_gpio; /* External chip-select gpio */
128
Sean Andersondebbff82020-10-16 18:57:51 -0400129 u32 (*update_cr0)(struct dw_spi_priv *priv);
Stefan Roesed987ea62014-11-07 13:50:31 +0100130
Sean Andersone11c0b12020-10-16 18:57:49 -0400131 void __iomem *regs;
132 unsigned long bus_clk_rate;
133 unsigned int freq; /* Default frequency */
134 unsigned int mode;
Stefan Roesed987ea62014-11-07 13:50:31 +0100135
Sean Andersone11c0b12020-10-16 18:57:49 -0400136 const void *tx;
137 const void *tx_end;
Stefan Roesed987ea62014-11-07 13:50:31 +0100138 void *rx;
139 void *rx_end;
Sean Andersone11c0b12020-10-16 18:57:49 -0400140 u32 fifo_len; /* depth of the FIFO buffer */
Sean Andersondebbff82020-10-16 18:57:51 -0400141 u32 max_xfer; /* Maximum transfer size (in bits) */
Ley Foon Tanfc3382d2018-09-07 14:25:29 +0800142
Sean Andersone11c0b12020-10-16 18:57:49 -0400143 int bits_per_word;
144 int len;
145 u8 cs; /* chip select pin */
146 u8 tmode; /* TR/TO/RO/EEPROM */
147 u8 type; /* SPI/SSP/MicroWire */
Stefan Roesed987ea62014-11-07 13:50:31 +0100148};
149
Eugeniy Paltseve0c89232018-03-22 13:50:47 +0300150static inline u32 dw_read(struct dw_spi_priv *priv, u32 offset)
Stefan Roesed987ea62014-11-07 13:50:31 +0100151{
152 return __raw_readl(priv->regs + offset);
153}
154
Eugeniy Paltseve0c89232018-03-22 13:50:47 +0300155static inline void dw_write(struct dw_spi_priv *priv, u32 offset, u32 val)
Stefan Roesed987ea62014-11-07 13:50:31 +0100156{
157 __raw_writel(val, priv->regs + offset);
158}
159
Sean Andersondebbff82020-10-16 18:57:51 -0400160static u32 dw_spi_dw16_update_cr0(struct dw_spi_priv *priv)
161{
162 return FIELD_PREP(CTRLR0_DFS_MASK, priv->bits_per_word - 1)
163 | FIELD_PREP(CTRLR0_FRF_MASK, priv->type)
164 | FIELD_PREP(CTRLR0_MODE_MASK, priv->mode)
165 | FIELD_PREP(CTRLR0_TMOD_MASK, priv->tmode);
166}
167
168static u32 dw_spi_dw32_update_cr0(struct dw_spi_priv *priv)
169{
170 return FIELD_PREP(CTRLR0_DFS_32_MASK, priv->bits_per_word - 1)
171 | FIELD_PREP(CTRLR0_FRF_MASK, priv->type)
172 | FIELD_PREP(CTRLR0_MODE_MASK, priv->mode)
173 | FIELD_PREP(CTRLR0_TMOD_MASK, priv->tmode);
174}
175
176static u32 dw_spi_dwc_update_cr0(struct dw_spi_priv *priv)
177{
178 return FIELD_PREP(DWC_SSI_CTRLR0_DFS_MASK, priv->bits_per_word - 1)
179 | FIELD_PREP(DWC_SSI_CTRLR0_FRF_MASK, priv->type)
180 | FIELD_PREP(DWC_SSI_CTRLR0_MODE_MASK, priv->mode)
181 | FIELD_PREP(DWC_SSI_CTRLR0_TMOD_MASK, priv->tmode);
182}
183
184static int dw_spi_apb_init(struct udevice *bus, struct dw_spi_priv *priv)
185{
186 /* If we read zeros from DFS, then we need to use DFS_32 instead */
187 dw_write(priv, DW_SPI_SSIENR, 0);
188 dw_write(priv, DW_SPI_CTRLR0, 0xffffffff);
189 if (FIELD_GET(CTRLR0_DFS_MASK, dw_read(priv, DW_SPI_CTRLR0))) {
190 priv->max_xfer = 16;
191 priv->update_cr0 = dw_spi_dw16_update_cr0;
192 } else {
193 priv->max_xfer = 32;
194 priv->update_cr0 = dw_spi_dw32_update_cr0;
195 }
196
197 return 0;
198}
199
Damien Le Moal96b2bdd2022-03-01 10:35:43 +0000200static int dw_spi_apb_k210_init(struct udevice *bus, struct dw_spi_priv *priv)
201{
202 /*
203 * The Canaan Kendryte K210 SoC DW apb_ssi v4 spi controller is
204 * documented to have a 32 word deep TX and RX FIFO, which
205 * spi_hw_init() detects. However, when the RX FIFO is filled up to
206 * 32 entries (RXFLR = 32), an RX FIFO overrun error occurs. Avoid
207 * this problem by force setting fifo_len to 31.
208 */
209 priv->fifo_len = 31;
210
211 return dw_spi_apb_init(bus, priv);
212}
213
Sean Andersondebbff82020-10-16 18:57:51 -0400214static int dw_spi_dwc_init(struct udevice *bus, struct dw_spi_priv *priv)
215{
216 priv->max_xfer = 32;
217 priv->update_cr0 = dw_spi_dwc_update_cr0;
218 return 0;
219}
220
Eugeniy Paltseva7b4de12018-03-22 13:50:46 +0300221static int request_gpio_cs(struct udevice *bus)
222{
Simon Glassfa4689a2019-12-06 21:41:35 -0700223#if CONFIG_IS_ENABLED(DM_GPIO) && !defined(CONFIG_SPL_BUILD)
Eugeniy Paltseva7b4de12018-03-22 13:50:46 +0300224 struct dw_spi_priv *priv = dev_get_priv(bus);
225 int ret;
226
227 /* External chip select gpio line is optional */
Sean Anderson17f69fb2020-10-16 18:57:45 -0400228 ret = gpio_request_by_name(bus, "cs-gpios", 0, &priv->cs_gpio,
229 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
Eugeniy Paltseva7b4de12018-03-22 13:50:46 +0300230 if (ret == -ENOENT)
231 return 0;
232
233 if (ret < 0) {
Sean Anderson0dfb3ac2020-10-16 18:57:44 -0400234 dev_err(bus, "Couldn't request gpio! (error %d)\n", ret);
Eugeniy Paltseva7b4de12018-03-22 13:50:46 +0300235 return ret;
236 }
237
238 if (dm_gpio_is_valid(&priv->cs_gpio)) {
239 dm_gpio_set_dir_flags(&priv->cs_gpio,
240 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
241 }
242
Sean Anderson0dfb3ac2020-10-16 18:57:44 -0400243 dev_dbg(bus, "Using external gpio for CS management\n");
Eugeniy Paltseva7b4de12018-03-22 13:50:46 +0300244#endif
245 return 0;
246}
247
Simon Glassaad29ae2020-12-03 16:55:21 -0700248static int dw_spi_of_to_plat(struct udevice *bus)
Stefan Roesed987ea62014-11-07 13:50:31 +0100249{
Simon Glass95588622020-12-22 19:30:28 -0700250 struct dw_spi_plat *plat = dev_get_plat(bus);
Stefan Roesed987ea62014-11-07 13:50:31 +0100251
Masahiro Yamada1096ae12020-07-17 14:36:46 +0900252 plat->regs = dev_read_addr_ptr(bus);
Sean Anderson72097a72020-10-16 18:57:46 -0400253 if (!plat->regs)
254 return -EINVAL;
Stefan Roesed987ea62014-11-07 13:50:31 +0100255
256 /* Use 500KHz as a suitable default */
Simon Goldschmidt70cd31b2019-05-09 22:11:57 +0200257 plat->frequency = dev_read_u32_default(bus, "spi-max-frequency",
258 500000);
Stefan Roesed987ea62014-11-07 13:50:31 +0100259
Sean Andersondebbff82020-10-16 18:57:51 -0400260 if (dev_read_bool(bus, "spi-slave"))
261 return -EINVAL;
Stefan Roesed987ea62014-11-07 13:50:31 +0100262
Sean Anderson0dfb3ac2020-10-16 18:57:44 -0400263 dev_info(bus, "max-frequency=%d\n", plat->frequency);
Stefan Roesed987ea62014-11-07 13:50:31 +0100264
265 return request_gpio_cs(bus);
Stefan Roesed987ea62014-11-07 13:50:31 +0100266}
267
268/* Restart the controller, disable all interrupts, clean rx fifo */
Sean Anderson0dfb3ac2020-10-16 18:57:44 -0400269static void spi_hw_init(struct udevice *bus, struct dw_spi_priv *priv)
Stefan Roesed987ea62014-11-07 13:50:31 +0100270{
Sean Andersonf2520822020-10-16 18:57:48 -0400271 dw_write(priv, DW_SPI_SSIENR, 0);
Sean Anderson5a6f4552022-03-01 10:35:43 +0000272 dw_write(priv, DW_SPI_IMR, 0);
Sean Andersonf2520822020-10-16 18:57:48 -0400273 dw_write(priv, DW_SPI_SSIENR, 1);
Stefan Roesed987ea62014-11-07 13:50:31 +0100274
275 /*
276 * Try to detect the FIFO depth if not set by interface driver,
277 * the depth could be from 2 to 256 from HW spec
278 */
279 if (!priv->fifo_len) {
280 u32 fifo;
281
Axel Lin83cfd372015-02-26 10:45:22 +0800282 for (fifo = 1; fifo < 256; fifo++) {
Sean Anderson75ea2f62020-10-16 18:57:47 -0400283 dw_write(priv, DW_SPI_TXFTLR, fifo);
284 if (fifo != dw_read(priv, DW_SPI_TXFTLR))
Stefan Roesed987ea62014-11-07 13:50:31 +0100285 break;
286 }
287
Axel Lin83cfd372015-02-26 10:45:22 +0800288 priv->fifo_len = (fifo == 1) ? 0 : fifo;
Sean Anderson75ea2f62020-10-16 18:57:47 -0400289 dw_write(priv, DW_SPI_TXFTLR, 0);
Stefan Roesed987ea62014-11-07 13:50:31 +0100290 }
Sean Anderson0dfb3ac2020-10-16 18:57:44 -0400291 dev_dbg(bus, "fifo_len=%d\n", priv->fifo_len);
Stefan Roesed987ea62014-11-07 13:50:31 +0100292}
293
Eugeniy Paltsev8b841e32017-12-28 15:09:03 +0300294/*
295 * We define dw_spi_get_clk function as 'weak' as some targets
296 * (like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API
297 * and implement dw_spi_get_clk their own way in their clock manager.
298 */
299__weak int dw_spi_get_clk(struct udevice *bus, ulong *rate)
300{
301 struct dw_spi_priv *priv = dev_get_priv(bus);
302 int ret;
303
304 ret = clk_get_by_index(bus, 0, &priv->clk);
305 if (ret)
306 return ret;
307
308 ret = clk_enable(&priv->clk);
309 if (ret && ret != -ENOSYS && ret != -ENOTSUPP)
310 return ret;
311
312 *rate = clk_get_rate(&priv->clk);
313 if (!*rate)
314 goto err_rate;
315
Sean Anderson0dfb3ac2020-10-16 18:57:44 -0400316 dev_dbg(bus, "Got clock via device tree: %lu Hz\n", *rate);
Eugeniy Paltsev8b841e32017-12-28 15:09:03 +0300317
318 return 0;
319
320err_rate:
321 clk_disable(&priv->clk);
Eugeniy Paltsev8b841e32017-12-28 15:09:03 +0300322
323 return -EINVAL;
324}
325
Ley Foon Tanfc3382d2018-09-07 14:25:29 +0800326static int dw_spi_reset(struct udevice *bus)
327{
328 int ret;
329 struct dw_spi_priv *priv = dev_get_priv(bus);
330
331 ret = reset_get_bulk(bus, &priv->resets);
332 if (ret) {
333 /*
334 * Return 0 if error due to !CONFIG_DM_RESET and reset
335 * DT property is not present.
336 */
337 if (ret == -ENOENT || ret == -ENOTSUPP)
338 return 0;
339
Sean Anderson0dfb3ac2020-10-16 18:57:44 -0400340 dev_warn(bus, "Couldn't find/assert reset device (error %d)\n",
341 ret);
Ley Foon Tanfc3382d2018-09-07 14:25:29 +0800342 return ret;
343 }
344
345 ret = reset_deassert_bulk(&priv->resets);
346 if (ret) {
347 reset_release_bulk(&priv->resets);
Sean Anderson0dfb3ac2020-10-16 18:57:44 -0400348 dev_err(bus, "Failed to de-assert reset for SPI (error %d)\n",
349 ret);
Ley Foon Tanfc3382d2018-09-07 14:25:29 +0800350 return ret;
351 }
352
353 return 0;
354}
355
Sean Andersondebbff82020-10-16 18:57:51 -0400356typedef int (*dw_spi_init_t)(struct udevice *bus, struct dw_spi_priv *priv);
357
Stefan Roesed987ea62014-11-07 13:50:31 +0100358static int dw_spi_probe(struct udevice *bus)
359{
Sean Andersondebbff82020-10-16 18:57:51 -0400360 dw_spi_init_t init = (dw_spi_init_t)dev_get_driver_data(bus);
Simon Glassb75b15b2020-12-03 16:55:23 -0700361 struct dw_spi_plat *plat = dev_get_plat(bus);
Stefan Roesed987ea62014-11-07 13:50:31 +0100362 struct dw_spi_priv *priv = dev_get_priv(bus);
Eugeniy Paltsev8b841e32017-12-28 15:09:03 +0300363 int ret;
Sean Andersondebbff82020-10-16 18:57:51 -0400364 u32 version;
Stefan Roesed987ea62014-11-07 13:50:31 +0100365
366 priv->regs = plat->regs;
367 priv->freq = plat->frequency;
368
Eugeniy Paltsev8b841e32017-12-28 15:09:03 +0300369 ret = dw_spi_get_clk(bus, &priv->bus_clk_rate);
370 if (ret)
371 return ret;
372
Ley Foon Tanfc3382d2018-09-07 14:25:29 +0800373 ret = dw_spi_reset(bus);
374 if (ret)
375 return ret;
376
Sean Andersondebbff82020-10-16 18:57:51 -0400377 if (!init)
378 return -EINVAL;
379 ret = init(bus, priv);
380 if (ret)
381 return ret;
382
383 version = dw_read(priv, DW_SPI_VERSION);
384 dev_dbg(bus, "ssi_version_id=%c.%c%c%c ssi_max_xfer_size=%u\n",
385 version >> 24, version >> 16, version >> 8, version,
386 priv->max_xfer);
387
Stefan Roesed987ea62014-11-07 13:50:31 +0100388 /* Currently only bits_per_word == 8 supported */
389 priv->bits_per_word = 8;
Stefan Roesed987ea62014-11-07 13:50:31 +0100390
391 priv->tmode = 0; /* Tx & Rx */
392
393 /* Basic HW init */
Sean Anderson0dfb3ac2020-10-16 18:57:44 -0400394 spi_hw_init(bus, priv);
Stefan Roesed987ea62014-11-07 13:50:31 +0100395
396 return 0;
397}
398
399/* Return the max entries we can fill into tx fifo */
400static inline u32 tx_max(struct dw_spi_priv *priv)
401{
402 u32 tx_left, tx_room, rxtx_gap;
403
Stefan Roese571e2a42014-11-16 12:47:01 +0100404 tx_left = (priv->tx_end - priv->tx) / (priv->bits_per_word >> 3);
Eugeniy Paltseve0c89232018-03-22 13:50:47 +0300405 tx_room = priv->fifo_len - dw_read(priv, DW_SPI_TXFLR);
Stefan Roesed987ea62014-11-07 13:50:31 +0100406
407 /*
408 * Another concern is about the tx/rx mismatch, we
Stefan Roese571e2a42014-11-16 12:47:01 +0100409 * thought about using (priv->fifo_len - rxflr - txflr) as
Stefan Roesed987ea62014-11-07 13:50:31 +0100410 * one maximum value for tx, but it doesn't cover the
411 * data which is out of tx/rx fifo and inside the
412 * shift registers. So a control from sw point of
413 * view is taken.
414 */
415 rxtx_gap = ((priv->rx_end - priv->rx) - (priv->tx_end - priv->tx)) /
Stefan Roese571e2a42014-11-16 12:47:01 +0100416 (priv->bits_per_word >> 3);
Stefan Roesed987ea62014-11-07 13:50:31 +0100417
418 return min3(tx_left, tx_room, (u32)(priv->fifo_len - rxtx_gap));
419}
420
421/* Return the max entries we should read out of rx fifo */
422static inline u32 rx_max(struct dw_spi_priv *priv)
423{
Stefan Roese571e2a42014-11-16 12:47:01 +0100424 u32 rx_left = (priv->rx_end - priv->rx) / (priv->bits_per_word >> 3);
Stefan Roesed987ea62014-11-07 13:50:31 +0100425
Eugeniy Paltseve0c89232018-03-22 13:50:47 +0300426 return min_t(u32, rx_left, dw_read(priv, DW_SPI_RXFLR));
Stefan Roesed987ea62014-11-07 13:50:31 +0100427}
428
429static void dw_writer(struct dw_spi_priv *priv)
430{
431 u32 max = tx_max(priv);
Sean Andersondebbff82020-10-16 18:57:51 -0400432 u32 txw = 0xFFFFFFFF;
Stefan Roesed987ea62014-11-07 13:50:31 +0100433
434 while (max--) {
435 /* Set the tx word if the transfer's original "tx" is not null */
436 if (priv->tx_end - priv->len) {
Stefan Roese571e2a42014-11-16 12:47:01 +0100437 if (priv->bits_per_word == 8)
Stefan Roesed987ea62014-11-07 13:50:31 +0100438 txw = *(u8 *)(priv->tx);
439 else
440 txw = *(u16 *)(priv->tx);
441 }
Eugeniy Paltseve0c89232018-03-22 13:50:47 +0300442 dw_write(priv, DW_SPI_DR, txw);
Sean Anderson0dfb3ac2020-10-16 18:57:44 -0400443 log_content("tx=0x%02x\n", txw);
Stefan Roese571e2a42014-11-16 12:47:01 +0100444 priv->tx += priv->bits_per_word >> 3;
Stefan Roesed987ea62014-11-07 13:50:31 +0100445 }
446}
447
Eugeniy Paltsevc5c6d452018-03-22 13:50:45 +0300448static void dw_reader(struct dw_spi_priv *priv)
Stefan Roesed987ea62014-11-07 13:50:31 +0100449{
Eugeniy Paltsevc5c6d452018-03-22 13:50:45 +0300450 u32 max = rx_max(priv);
Stefan Roesed987ea62014-11-07 13:50:31 +0100451 u16 rxw;
452
Stefan Roesed987ea62014-11-07 13:50:31 +0100453 while (max--) {
Eugeniy Paltseve0c89232018-03-22 13:50:47 +0300454 rxw = dw_read(priv, DW_SPI_DR);
Sean Anderson0dfb3ac2020-10-16 18:57:44 -0400455 log_content("rx=0x%02x\n", rxw);
Stefan Roese571e2a42014-11-16 12:47:01 +0100456
Eugeniy Paltsevc5c6d452018-03-22 13:50:45 +0300457 /* Care about rx if the transfer's original "rx" is not null */
Stefan Roesed987ea62014-11-07 13:50:31 +0100458 if (priv->rx_end - priv->len) {
Stefan Roese571e2a42014-11-16 12:47:01 +0100459 if (priv->bits_per_word == 8)
Stefan Roesed987ea62014-11-07 13:50:31 +0100460 *(u8 *)(priv->rx) = rxw;
461 else
462 *(u16 *)(priv->rx) = rxw;
463 }
Stefan Roese571e2a42014-11-16 12:47:01 +0100464 priv->rx += priv->bits_per_word >> 3;
Stefan Roesed987ea62014-11-07 13:50:31 +0100465 }
Stefan Roesed987ea62014-11-07 13:50:31 +0100466}
467
468static int poll_transfer(struct dw_spi_priv *priv)
469{
Stefan Roesed987ea62014-11-07 13:50:31 +0100470 do {
471 dw_writer(priv);
Eugeniy Paltsevc5c6d452018-03-22 13:50:45 +0300472 dw_reader(priv);
Stefan Roesed987ea62014-11-07 13:50:31 +0100473 } while (priv->rx_end > priv->rx);
474
475 return 0;
476}
477
Gregory CLEMENTf2893372018-10-09 14:14:07 +0200478/*
479 * We define external_cs_manage function as 'weak' as some targets
480 * (like MSCC Ocelot) don't control the external CS pin using a GPIO
481 * controller. These SoCs use specific registers to control by
482 * software the SPI pins (and especially the CS).
483 */
484__weak void external_cs_manage(struct udevice *dev, bool on)
Eugeniy Paltseva7b4de12018-03-22 13:50:46 +0300485{
Simon Glassfa4689a2019-12-06 21:41:35 -0700486#if CONFIG_IS_ENABLED(DM_GPIO) && !defined(CONFIG_SPL_BUILD)
Eugeniy Paltseva7b4de12018-03-22 13:50:46 +0300487 struct dw_spi_priv *priv = dev_get_priv(dev->parent);
488
489 if (!dm_gpio_is_valid(&priv->cs_gpio))
490 return;
491
492 dm_gpio_set_value(&priv->cs_gpio, on ? 1 : 0);
493#endif
494}
495
Stefan Roesed987ea62014-11-07 13:50:31 +0100496static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
497 const void *dout, void *din, unsigned long flags)
498{
499 struct udevice *bus = dev->parent;
500 struct dw_spi_priv *priv = dev_get_priv(bus);
501 const u8 *tx = dout;
502 u8 *rx = din;
503 int ret = 0;
504 u32 cr0 = 0;
Eugeniy Paltsev7215ad22018-03-22 13:50:43 +0300505 u32 val;
Stefan Roesed987ea62014-11-07 13:50:31 +0100506 u32 cs;
507
508 /* spi core configured to do 8 bit transfers */
509 if (bitlen % 8) {
Sean Anderson0dfb3ac2020-10-16 18:57:44 -0400510 dev_err(dev, "Non byte aligned SPI transfer.\n");
Stefan Roesed987ea62014-11-07 13:50:31 +0100511 return -1;
512 }
513
Eugeniy Paltseva7b4de12018-03-22 13:50:46 +0300514 /* Start the transaction if necessary. */
515 if (flags & SPI_XFER_BEGIN)
516 external_cs_manage(dev, false);
517
Stefan Roesed987ea62014-11-07 13:50:31 +0100518 if (rx && tx)
Sean Andersondebbff82020-10-16 18:57:51 -0400519 priv->tmode = CTRLR0_TMOD_TR;
Stefan Roesed987ea62014-11-07 13:50:31 +0100520 else if (rx)
Sean Andersondebbff82020-10-16 18:57:51 -0400521 priv->tmode = CTRLR0_TMOD_RO;
Stefan Roesed987ea62014-11-07 13:50:31 +0100522 else
Eugeniy Paltsev31f50132018-03-22 13:50:44 +0300523 /*
Sean Andersondebbff82020-10-16 18:57:51 -0400524 * In transmit only mode (CTRL0_TMOD_TO) input FIFO never gets
Eugeniy Paltsev31f50132018-03-22 13:50:44 +0300525 * any data which breaks our logic in poll_transfer() above.
526 */
Sean Andersondebbff82020-10-16 18:57:51 -0400527 priv->tmode = CTRLR0_TMOD_TR;
Stefan Roesed987ea62014-11-07 13:50:31 +0100528
Sean Andersondebbff82020-10-16 18:57:51 -0400529 cr0 = priv->update_cr0(priv);
Stefan Roesed987ea62014-11-07 13:50:31 +0100530
Stefan Roese571e2a42014-11-16 12:47:01 +0100531 priv->len = bitlen >> 3;
Stefan Roesed987ea62014-11-07 13:50:31 +0100532
533 priv->tx = (void *)tx;
534 priv->tx_end = priv->tx + priv->len;
535 priv->rx = rx;
536 priv->rx_end = priv->rx + priv->len;
537
538 /* Disable controller before writing control registers */
Sean Andersonf2520822020-10-16 18:57:48 -0400539 dw_write(priv, DW_SPI_SSIENR, 0);
Stefan Roesed987ea62014-11-07 13:50:31 +0100540
Sean Anderson0dfb3ac2020-10-16 18:57:44 -0400541 dev_dbg(dev, "cr0=%08x rx=%p tx=%p len=%d [bytes]\n", cr0, rx, tx,
542 priv->len);
Stefan Roesed987ea62014-11-07 13:50:31 +0100543 /* Reprogram cr0 only if changed */
Sean Anderson75ea2f62020-10-16 18:57:47 -0400544 if (dw_read(priv, DW_SPI_CTRLR0) != cr0)
545 dw_write(priv, DW_SPI_CTRLR0, cr0);
Stefan Roesed987ea62014-11-07 13:50:31 +0100546
547 /*
548 * Configure the desired SS (slave select 0...3) in the controller
549 * The DW SPI controller will activate and deactivate this CS
550 * automatically. So no cs_activate() etc is needed in this driver.
551 */
552 cs = spi_chip_select(dev);
Eugeniy Paltseve0c89232018-03-22 13:50:47 +0300553 dw_write(priv, DW_SPI_SER, 1 << cs);
Stefan Roesed987ea62014-11-07 13:50:31 +0100554
555 /* Enable controller after writing control registers */
Sean Andersonf2520822020-10-16 18:57:48 -0400556 dw_write(priv, DW_SPI_SSIENR, 1);
Stefan Roesed987ea62014-11-07 13:50:31 +0100557
558 /* Start transfer in a polling loop */
559 ret = poll_transfer(priv);
560
Eugeniy Paltsev7215ad22018-03-22 13:50:43 +0300561 /*
562 * Wait for current transmit operation to complete.
563 * Otherwise if some data still exists in Tx FIFO it can be
564 * silently flushed, i.e. dropped on disabling of the controller,
565 * which happens when writing 0 to DW_SPI_SSIENR which happens
566 * in the beginning of new transfer.
567 */
568 if (readl_poll_timeout(priv->regs + DW_SPI_SR, val,
Eugeniy Paltsev208be8f2018-04-19 17:47:41 +0300569 (val & SR_TF_EMPT) && !(val & SR_BUSY),
Eugeniy Paltsev7215ad22018-03-22 13:50:43 +0300570 RX_TIMEOUT * 1000)) {
571 ret = -ETIMEDOUT;
572 }
573
Eugeniy Paltseva7b4de12018-03-22 13:50:46 +0300574 /* Stop the transaction if necessary */
575 if (flags & SPI_XFER_END)
576 external_cs_manage(dev, true);
577
Stefan Roesed987ea62014-11-07 13:50:31 +0100578 return ret;
579}
580
Sean Anderson16edba32020-10-16 18:57:53 -0400581/*
582 * This function is necessary for reading SPI flash with the native CS
583 * c.f. https://lkml.org/lkml/2015/12/23/132
584 */
585static int dw_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
586{
587 bool read = op->data.dir == SPI_MEM_DATA_IN;
588 int pos, i, ret = 0;
589 struct udevice *bus = slave->dev->parent;
590 struct dw_spi_priv *priv = dev_get_priv(bus);
Niklas Casselb7e92072022-02-08 22:52:43 +0000591 u8 op_len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
Sean Anderson16edba32020-10-16 18:57:53 -0400592 u8 op_buf[op_len];
Maksim Kiselev6cf56182023-12-21 13:13:30 +0300593 u32 cr0, sts;
Sean Anderson16edba32020-10-16 18:57:53 -0400594
595 if (read)
596 priv->tmode = CTRLR0_TMOD_EPROMREAD;
597 else
598 priv->tmode = CTRLR0_TMOD_TO;
599
600 cr0 = priv->update_cr0(priv);
601 dev_dbg(bus, "cr0=%08x buf=%p len=%u [bytes]\n", cr0, op->data.buf.in,
602 op->data.nbytes);
603
604 dw_write(priv, DW_SPI_SSIENR, 0);
605 dw_write(priv, DW_SPI_CTRLR0, cr0);
606 if (read)
607 dw_write(priv, DW_SPI_CTRLR1, op->data.nbytes - 1);
608 dw_write(priv, DW_SPI_SSIENR, 1);
609
610 /* From spi_mem_exec_op */
611 pos = 0;
612 op_buf[pos++] = op->cmd.opcode;
613 if (op->addr.nbytes) {
614 for (i = 0; i < op->addr.nbytes; i++)
615 op_buf[pos + i] = op->addr.val >>
616 (8 * (op->addr.nbytes - i - 1));
617
618 pos += op->addr.nbytes;
619 }
620 if (op->dummy.nbytes)
621 memset(op_buf + pos, 0xff, op->dummy.nbytes);
622
623 external_cs_manage(slave->dev, false);
624
625 priv->tx = &op_buf;
626 priv->tx_end = priv->tx + op_len;
627 priv->rx = NULL;
628 priv->rx_end = NULL;
629 while (priv->tx != priv->tx_end)
630 dw_writer(priv);
631
632 /*
633 * XXX: The following are tight loops! Enabling debug messages may cause
634 * them to fail because we are not reading/writing the fifo fast enough.
635 */
636 if (read) {
Maksim Kiselev6cf56182023-12-21 13:13:30 +0300637 void *prev_rx = priv->rx = op->data.buf.in;
Sean Anderson16edba32020-10-16 18:57:53 -0400638 priv->rx_end = priv->rx + op->data.nbytes;
639
640 dw_write(priv, DW_SPI_SER, 1 << spi_chip_select(slave->dev));
Maksim Kiselev6cf56182023-12-21 13:13:30 +0300641 while (priv->rx != priv->rx_end) {
Sean Anderson16edba32020-10-16 18:57:53 -0400642 dw_reader(priv);
Maksim Kiselev6cf56182023-12-21 13:13:30 +0300643 if (prev_rx == priv->rx) {
644 sts = dw_read(priv, DW_SPI_RISR);
645 if (sts & RISR_INT_RXOI) {
646 dev_err(bus, "FIFO overflow on Rx\n");
647 return -EIO;
648 }
649 }
650 prev_rx = priv->rx;
651 }
Sean Anderson16edba32020-10-16 18:57:53 -0400652 } else {
653 u32 val;
654
655 priv->tx = op->data.buf.out;
656 priv->tx_end = priv->tx + op->data.nbytes;
657
658 /* Fill up the write fifo before starting the transfer */
659 dw_writer(priv);
660 dw_write(priv, DW_SPI_SER, 1 << spi_chip_select(slave->dev));
661 while (priv->tx != priv->tx_end)
662 dw_writer(priv);
663
664 if (readl_poll_timeout(priv->regs + DW_SPI_SR, val,
665 (val & SR_TF_EMPT) && !(val & SR_BUSY),
666 RX_TIMEOUT * 1000)) {
667 ret = -ETIMEDOUT;
668 }
669 }
670
671 dw_write(priv, DW_SPI_SER, 0);
672 external_cs_manage(slave->dev, true);
673
674 dev_dbg(bus, "%u bytes xfered\n", op->data.nbytes);
Stefan Roesed987ea62014-11-07 13:50:31 +0100675 return ret;
676}
677
Sean Anderson16edba32020-10-16 18:57:53 -0400678/* The size of ctrl1 limits data transfers to 64K */
679static int dw_spi_adjust_op_size(struct spi_slave *slave, struct spi_mem_op *op)
680{
681 op->data.nbytes = min(op->data.nbytes, (unsigned int)SZ_64K);
682
683 return 0;
684}
685
686static const struct spi_controller_mem_ops dw_spi_mem_ops = {
687 .exec_op = dw_spi_exec_op,
688 .adjust_op_size = dw_spi_adjust_op_size,
689};
690
Stefan Roesed987ea62014-11-07 13:50:31 +0100691static int dw_spi_set_speed(struct udevice *bus, uint speed)
692{
Simon Glass95588622020-12-22 19:30:28 -0700693 struct dw_spi_plat *plat = dev_get_plat(bus);
Stefan Roesed987ea62014-11-07 13:50:31 +0100694 struct dw_spi_priv *priv = dev_get_priv(bus);
695 u16 clk_div;
696
697 if (speed > plat->frequency)
698 speed = plat->frequency;
699
700 /* Disable controller before writing control registers */
Sean Andersonf2520822020-10-16 18:57:48 -0400701 dw_write(priv, DW_SPI_SSIENR, 0);
Stefan Roesed987ea62014-11-07 13:50:31 +0100702
703 /* clk_div doesn't support odd number */
Eugeniy Paltsev8b841e32017-12-28 15:09:03 +0300704 clk_div = priv->bus_clk_rate / speed;
Stefan Roesed987ea62014-11-07 13:50:31 +0100705 clk_div = (clk_div + 1) & 0xfffe;
Eugeniy Paltseve0c89232018-03-22 13:50:47 +0300706 dw_write(priv, DW_SPI_BAUDR, clk_div);
Stefan Roesed987ea62014-11-07 13:50:31 +0100707
708 /* Enable controller after writing control registers */
Sean Andersonf2520822020-10-16 18:57:48 -0400709 dw_write(priv, DW_SPI_SSIENR, 1);
Stefan Roesed987ea62014-11-07 13:50:31 +0100710
711 priv->freq = speed;
Sean Anderson0dfb3ac2020-10-16 18:57:44 -0400712 dev_dbg(bus, "speed=%d clk_div=%d\n", priv->freq, clk_div);
Stefan Roesed987ea62014-11-07 13:50:31 +0100713
714 return 0;
715}
716
717static int dw_spi_set_mode(struct udevice *bus, uint mode)
718{
719 struct dw_spi_priv *priv = dev_get_priv(bus);
720
721 /*
722 * Can't set mode yet. Since this depends on if rx, tx, or
723 * rx & tx is requested. So we have to defer this to the
724 * real transfer function.
725 */
726 priv->mode = mode;
Sean Anderson0dfb3ac2020-10-16 18:57:44 -0400727 dev_dbg(bus, "mode=%d\n", priv->mode);
Stefan Roesed987ea62014-11-07 13:50:31 +0100728
729 return 0;
730}
731
Ley Foon Tanfc3382d2018-09-07 14:25:29 +0800732static int dw_spi_remove(struct udevice *bus)
733{
734 struct dw_spi_priv *priv = dev_get_priv(bus);
Ley Foon Tand95ab402018-09-19 16:27:19 +0800735 int ret;
736
737 ret = reset_release_bulk(&priv->resets);
738 if (ret)
739 return ret;
740
741#if CONFIG_IS_ENABLED(CLK)
742 ret = clk_disable(&priv->clk);
743 if (ret)
744 return ret;
Ley Foon Tand95ab402018-09-19 16:27:19 +0800745#endif
746 return 0;
Ley Foon Tanfc3382d2018-09-07 14:25:29 +0800747}
748
Stefan Roesed987ea62014-11-07 13:50:31 +0100749static const struct dm_spi_ops dw_spi_ops = {
750 .xfer = dw_spi_xfer,
Sean Anderson16edba32020-10-16 18:57:53 -0400751 .mem_ops = &dw_spi_mem_ops,
Stefan Roesed987ea62014-11-07 13:50:31 +0100752 .set_speed = dw_spi_set_speed,
753 .set_mode = dw_spi_set_mode,
754 /*
755 * cs_info is not needed, since we require all chip selects to be
756 * in the device tree explicitly
757 */
758};
759
760static const struct udevice_id dw_spi_ids[] = {
Sean Andersondebbff82020-10-16 18:57:51 -0400761 /* Generic compatible strings */
762
763 { .compatible = "snps,dw-apb-ssi", .data = (ulong)dw_spi_apb_init },
764 { .compatible = "snps,dw-apb-ssi-3.20a", .data = (ulong)dw_spi_apb_init },
765 { .compatible = "snps,dw-apb-ssi-3.22a", .data = (ulong)dw_spi_apb_init },
766 /* First version with SSI_MAX_XFER_SIZE */
767 { .compatible = "snps,dw-apb-ssi-3.23a", .data = (ulong)dw_spi_apb_init },
768 /* First version with Dual/Quad SPI; unused by this driver */
769 { .compatible = "snps,dw-apb-ssi-4.00a", .data = (ulong)dw_spi_apb_init },
770 { .compatible = "snps,dw-apb-ssi-4.01", .data = (ulong)dw_spi_apb_init },
771 { .compatible = "snps,dwc-ssi-1.01a", .data = (ulong)dw_spi_dwc_init },
772
773 /* Compatible strings for specific SoCs */
774
775 /*
776 * Both the Cyclone V and Arria V share a device tree and have the same
777 * version of this device. This compatible string is used for those
778 * devices, and is not used for sofpgas in general.
779 */
780 { .compatible = "altr,socfpga-spi", .data = (ulong)dw_spi_apb_init },
781 { .compatible = "altr,socfpga-arria10-spi", .data = (ulong)dw_spi_apb_init },
Damien Le Moal96b2bdd2022-03-01 10:35:43 +0000782 { .compatible = "canaan,k210-spi", .data = (ulong)dw_spi_apb_k210_init},
Damien Le Moal6e5a8b72022-03-01 10:35:39 +0000783 { .compatible = "canaan,k210-ssi", .data = (ulong)dw_spi_dwc_init },
Sean Andersondebbff82020-10-16 18:57:51 -0400784 { .compatible = "intel,stratix10-spi", .data = (ulong)dw_spi_apb_init },
785 { .compatible = "intel,agilex-spi", .data = (ulong)dw_spi_apb_init },
786 { .compatible = "mscc,ocelot-spi", .data = (ulong)dw_spi_apb_init },
787 { .compatible = "mscc,jaguar2-spi", .data = (ulong)dw_spi_apb_init },
788 { .compatible = "snps,axs10x-spi", .data = (ulong)dw_spi_apb_init },
789 { .compatible = "snps,hsdk-spi", .data = (ulong)dw_spi_apb_init },
Stefan Roesed987ea62014-11-07 13:50:31 +0100790 { }
791};
792
793U_BOOT_DRIVER(dw_spi) = {
794 .name = "dw_spi",
795 .id = UCLASS_SPI,
796 .of_match = dw_spi_ids,
797 .ops = &dw_spi_ops,
Simon Glassaad29ae2020-12-03 16:55:21 -0700798 .of_to_plat = dw_spi_of_to_plat,
Simon Glassb75b15b2020-12-03 16:55:23 -0700799 .plat_auto = sizeof(struct dw_spi_plat),
Simon Glass8a2b47f2020-12-03 16:55:17 -0700800 .priv_auto = sizeof(struct dw_spi_priv),
Stefan Roesed987ea62014-11-07 13:50:31 +0100801 .probe = dw_spi_probe,
Ley Foon Tanfc3382d2018-09-07 14:25:29 +0800802 .remove = dw_spi_remove,
Stefan Roesed987ea62014-11-07 13:50:31 +0100803};