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git01.mediatek.com / filogic / uboot / 28f90047fc6212c44ada81995127febfad493a9d / . / configs / socfpga_sr1500_defconfig
blob: c8239e7afffacc58db6c67acc4c97a6337157d09 [file] [log] [blame]
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_SOCFPGA=y
Masahiro Yamada75794f92016-09-19 21:40:26 +0900[diff] [blame]3CONFIG_SYS_MALLOC_F_LEN=0x2000
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]4CONFIG_TARGET_SOCFPGA_SR1500=y
Simon Glassc08ebf62016-02-22 22:55:40 -0700[diff] [blame]5CONFIG_SPL_STACK_R_ADDR=0x00800000
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]6CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
Simon Glassffe19762016-09-12 23:18:22 -0600[diff] [blame]7CONFIG_FIT=y
Simon Glass9fd2a022016-10-17 20:12:37 -0600[diff] [blame]8CONFIG_SYS_CONSOLE_IS_IN_ENV=y
Simon Glassac3ee422016-10-17 20:12:59 -0600[diff] [blame]9CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
Simon Glass217652f2016-10-17 20:12:58 -0600[diff] [blame]10CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
Simon Glassbd5618d2016-10-17 20:13:00 -0600[diff] [blame]11CONFIG_SYS_CONSOLE_INFO_QUIET=y
Tom Rini79f4eea2017-05-01 11:41:11 -0400[diff] [blame]12CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_sr1500.dtb"
Simon Glassffe19762016-09-12 23:18:22 -0600[diff] [blame]13CONFIG_VERSION_VARIABLE=y
Lokesh Vutla94d95e42016-10-11 21:33:46 -0400[diff] [blame]14# CONFIG_DISPLAY_BOARDINFO is not set
Simon Glass7a99a872017-01-23 13:31:20 -0700[diff] [blame]15CONFIG_BOARD_EARLY_INIT_F=y
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]16CONFIG_SPL=y
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]17CONFIG_SPL_SYS_MALLOC_SIMPLE=y
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]18CONFIG_SPL_STACK_R=y
Tom Rinif852e732016-04-21 21:37:19 -0400[diff] [blame]19CONFIG_HUSH_PARSER=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]20CONFIG_CMD_BOOTZ=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]21CONFIG_CMD_ASKENV=y
22CONFIG_CMD_GREPENV=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]23CONFIG_CMD_MEMTEST=y
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]24# CONFIG_CMD_FLASH is not set
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]25CONFIG_CMD_GPIO=y
26CONFIG_CMD_I2C=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]27CONFIG_CMD_MMC=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]28CONFIG_CMD_SF=y
29CONFIG_CMD_SPI=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]30CONFIG_CMD_DHCP=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]31CONFIG_CMD_MII=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]32CONFIG_CMD_PING=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]33CONFIG_CMD_CACHE=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]34CONFIG_CMD_TIME=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]35CONFIG_CMD_EXT4=y
36CONFIG_CMD_EXT4_WRITE=y
37CONFIG_CMD_FAT=y
38CONFIG_CMD_FS_GENERIC=y
Andrey Zhizhikin86283e82017-12-18 14:04:57 +0100[diff] [blame]39CONFIG_CMD_PART=y
Tom Rini5ad8e112017-10-22 17:55:07 -0400[diff] [blame]40CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
41CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
Heiko Schocher09dbb852016-09-21 07:58:19 +0200[diff] [blame]42CONFIG_CMD_UBI=y
Tom Rini5b0b0402017-08-28 07:16:32 -0400[diff] [blame]43CONFIG_ENV_IS_IN_SPI_FLASH=y
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]44CONFIG_SPL_DM=y
Simon Glassc08ebf62016-02-22 22:55:40 -0700[diff] [blame]45CONFIG_SPL_DM_SEQ_ALIAS=y
Tien Fong Cheecde42192017-07-26 13:05:40 +0800[diff] [blame]46CONFIG_FPGA_SOCFPGA=y
Tom Riniafea41d2016-09-08 16:11:59 -0400[diff] [blame]47CONFIG_DM_GPIO=y
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]48CONFIG_DWAPB_GPIO=y
Stefan Roese78077b62016-04-28 09:47:18 +0200[diff] [blame]49CONFIG_SYS_I2C_DW=y
Simon Glassc08ebf62016-02-22 22:55:40 -0700[diff] [blame]50CONFIG_DM_MMC=y
Masahiro Yamada7942e912017-01-10 13:32:04 +0900[diff] [blame]51CONFIG_MMC_DW=y
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]52CONFIG_SPI_FLASH=y
Tom Rinif852e732016-04-21 21:37:19 -0400[diff] [blame]53CONFIG_SPI_FLASH_BAR=y
Stefan Roese85e84392016-03-03 16:57:39 +0100[diff] [blame]54CONFIG_SPI_FLASH_STMICRO=y
Simon Glassc08ebf62016-02-22 22:55:40 -0700[diff] [blame]55# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]56CONFIG_DM_ETH=y
Tom Rinica22e962017-08-07 22:00:34 -0400[diff] [blame]57CONFIG_PHY_GIGE=y
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]58CONFIG_ETH_DESIGNWARE=y
59CONFIG_SYS_NS16550=y
Stefan Roese85e84392016-03-03 16:57:39 +0100[diff] [blame]60CONFIG_CADENCE_QSPI=y
Heiko Schocher0b368b12016-06-07 08:31:14 +0200[diff] [blame]61CONFIG_USE_TINY_PRINTF=y