| Stefan Roese | bf5ed2e | 2015-11-18 11:06:09 +0100 | [diff] [blame] | 1 | CONFIG_ARM=y |
| 2 | CONFIG_ARCH_SOCFPGA=y |
| 3 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
| 4 | CONFIG_SPL_DM=y |
| 5 | CONFIG_DM_GPIO=y |
| 6 | CONFIG_TARGET_SOCFPGA_SR1500=y |
| Simon Glass | c08ebf6 | 2016-02-22 22:55:40 -0700 | [diff] [blame] | 7 | CONFIG_SPL_STACK_R_ADDR=0x00800000 |
| Stefan Roese | bf5ed2e | 2015-11-18 11:06:09 +0100 | [diff] [blame] | 8 | CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500" |
| 9 | CONFIG_SPL=y |
| 10 | CONFIG_SPL_STACK_R=y |
| Simon Glass | e3ee2fb | 2016-02-22 22:55:43 -0700 | [diff] [blame] | 11 | CONFIG_FIT=y |
| Tom Rini | f852e73 | 2016-04-21 21:37:19 -0400 | [diff] [blame^] | 12 | CONFIG_HUSH_PARSER=y |
| Stefan Roese | bf5ed2e | 2015-11-18 11:06:09 +0100 | [diff] [blame] | 13 | # CONFIG_CMD_IMLS is not set |
| 14 | # CONFIG_CMD_FLASH is not set |
| Simon Glass | c08ebf6 | 2016-02-22 22:55:40 -0700 | [diff] [blame] | 15 | CONFIG_SPL_DM_SEQ_ALIAS=y |
| Stefan Roese | bf5ed2e | 2015-11-18 11:06:09 +0100 | [diff] [blame] | 16 | CONFIG_DWAPB_GPIO=y |
| Simon Glass | c08ebf6 | 2016-02-22 22:55:40 -0700 | [diff] [blame] | 17 | CONFIG_DM_MMC=y |
| Stefan Roese | bf5ed2e | 2015-11-18 11:06:09 +0100 | [diff] [blame] | 18 | CONFIG_SPI_FLASH=y |
| Tom Rini | f852e73 | 2016-04-21 21:37:19 -0400 | [diff] [blame^] | 19 | CONFIG_SPI_FLASH_BAR=y |
| Stefan Roese | 85e8439 | 2016-03-03 16:57:39 +0100 | [diff] [blame] | 20 | CONFIG_SPI_FLASH_STMICRO=y |
| Simon Glass | c08ebf6 | 2016-02-22 22:55:40 -0700 | [diff] [blame] | 21 | # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set |
| Stefan Roese | bf5ed2e | 2015-11-18 11:06:09 +0100 | [diff] [blame] | 22 | CONFIG_DM_ETH=y |
| 23 | CONFIG_ETH_DESIGNWARE=y |
| 24 | CONFIG_SYS_NS16550=y |
| Stefan Roese | 85e8439 | 2016-03-03 16:57:39 +0100 | [diff] [blame] | 25 | CONFIG_CADENCE_QSPI=y |