blob: 7318fb6c5855879612adb9ce6108bb125e560db6 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
David Feng3b5458c2013-12-14 11:47:37 +08002/*
3 * Configuration for Versatile Express. Parts were derived from other ARM
4 * configurations.
David Feng3b5458c2013-12-14 11:47:37 +08005 */
6
7#ifndef __VEXPRESS_AEMV8A_H
8#define __VEXPRESS_AEMV8A_H
9
David Feng3b5458c2013-12-14 11:47:37 +080010#define CONFIG_REMAKE_ELF
11
David Feng3b5458c2013-12-14 11:47:37 +080012/* Link Definitions */
Ryan Harkind700c3a2019-08-27 11:56:49 +010013#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
Darwin Rambod32d4112014-06-09 11:12:59 -070014/* ATF loads u-boot here for BASE_FVP model */
Darwin Rambod32d4112014-06-09 11:12:59 -070015#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
Linus Walleijc5822502015-01-23 14:41:10 +010016#elif CONFIG_TARGET_VEXPRESS64_JUNO
Linus Walleijc5822502015-01-23 14:41:10 +010017#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
Darwin Rambod32d4112014-06-09 11:12:59 -070018#endif
David Feng3b5458c2013-12-14 11:47:37 +080019
Ryan Harkin642aa2c2015-10-09 17:18:01 +010020#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
21
David Feng3b5458c2013-12-14 11:47:37 +080022/* CS register bases for the original memory map. */
23#define V2M_PA_CS0 0x00000000
24#define V2M_PA_CS1 0x14000000
25#define V2M_PA_CS2 0x18000000
26#define V2M_PA_CS3 0x1c000000
27#define V2M_PA_CS4 0x0c000000
28#define V2M_PA_CS5 0x10000000
29
30#define V2M_PERIPH_OFFSET(x) (x << 16)
31#define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
32#define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
33#define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
34
35#define V2M_BASE 0x80000000
36
David Feng3b5458c2013-12-14 11:47:37 +080037/* Common peripherals relative to CS7. */
38#define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
39#define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
40#define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
41#define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
42
Linus Walleijc5822502015-01-23 14:41:10 +010043#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
44#define V2M_UART0 0x7ff80000
45#define V2M_UART1 0x7ff70000
46#else /* Not Juno */
David Feng3b5458c2013-12-14 11:47:37 +080047#define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
48#define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
49#define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
50#define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
Linus Walleijc5822502015-01-23 14:41:10 +010051#endif
David Feng3b5458c2013-12-14 11:47:37 +080052
53#define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
54
55#define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
56#define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))
57
58#define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
59#define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))
60
61#define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))
62
63#define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))
64
65/* System register offsets. */
66#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
67#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
68#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
69
70/* Generic Timer Definitions */
Andre Przywara197b00e2020-06-11 12:03:15 +010071#define COUNTER_FREQUENCY 24000000 /* 24MHz */
David Feng3b5458c2013-12-14 11:47:37 +080072
73/* Generic Interrupt Controller Definitions */
David Feng79bbde02014-03-14 14:26:27 +080074#ifdef CONFIG_GICV3
75#define GICD_BASE (0x2f000000)
76#define GICR_BASE (0x2f100000)
77#else
Darwin Rambod32d4112014-06-09 11:12:59 -070078
Ryan Harkind700c3a2019-08-27 11:56:49 +010079#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
Darwin Rambod32d4112014-06-09 11:12:59 -070080#define GICD_BASE (0x2f000000)
81#define GICC_BASE (0x2c000000)
Linus Walleijc5822502015-01-23 14:41:10 +010082#elif CONFIG_TARGET_VEXPRESS64_JUNO
83#define GICD_BASE (0x2C010000)
84#define GICC_BASE (0x2C02f000)
David Feng79bbde02014-03-14 14:26:27 +080085#endif
Linus Walleija90caa32015-03-23 11:06:14 +010086#endif /* !CONFIG_GICV3 */
David Feng3b5458c2013-12-14 11:47:37 +080087
David Feng3b5458c2013-12-14 11:47:37 +080088/* Size of malloc() pool */
Tom Rini7e76aa42014-08-14 06:42:37 -040089#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20))
David Feng3b5458c2013-12-14 11:47:37 +080090
Adam Ford0a044f82017-09-05 15:20:44 -050091#ifndef CONFIG_TARGET_VEXPRESS64_JUNO
Linus Walleij48b47552015-02-17 11:35:25 +010092/* The Vexpress64 simulators use SMSC91C111 */
Bhupesh Sharmae997f352014-01-16 09:47:40 -060093#define CONFIG_SMC91111 1
94#define CONFIG_SMC91111_BASE (0x01A000000)
Linus Walleij48b47552015-02-17 11:35:25 +010095#endif
David Feng3b5458c2013-12-14 11:47:37 +080096
97/* PL011 Serial Configuration */
Linus Walleijc5822502015-01-23 14:41:10 +010098#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
Andre Przywarad3457182020-04-27 19:18:00 +010099#define CONFIG_PL011_CLOCK 7372800
Linus Walleijc5822502015-01-23 14:41:10 +0100100#else
David Feng3b5458c2013-12-14 11:47:37 +0800101#define CONFIG_PL011_CLOCK 24000000
Linus Walleijc5822502015-01-23 14:41:10 +0100102#endif
David Feng3b5458c2013-12-14 11:47:37 +0800103
David Feng3b5458c2013-12-14 11:47:37 +0800104/* BOOTP options */
105#define CONFIG_BOOTP_BOOTFILESIZE
David Feng3b5458c2013-12-14 11:47:37 +0800106
107/* Miscellaneous configurable options */
108#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000)
109
110/* Physical Memory Map */
David Feng3b5458c2013-12-14 11:47:37 +0800111#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */
Linus Walleij0a38bfe2015-05-11 10:03:57 +0200112/* Top 16MB reserved for secure world use */
113#define DRAM_SEC_SIZE 0x01000000
114#define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE
115#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
116
Ryan Harkin98d2fff2015-11-18 10:39:07 +0000117#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
Ryan Harkin98d2fff2015-11-18 10:39:07 +0000118#define PHYS_SDRAM_2 (0x880000000)
119#define PHYS_SDRAM_2_SIZE 0x180000000
Diego Sueiro7a02a1b2021-02-15 07:27:57 +0000120#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP && CONFIG_NR_DRAM_BANKS == 2
121#define PHYS_SDRAM_2 (0x880000000)
122#define PHYS_SDRAM_2_SIZE 0x80000000
Ryan Harkin98d2fff2015-11-18 10:39:07 +0000123#endif
124
Linus Walleij0a38bfe2015-05-11 10:03:57 +0200125/* Enable memtest */
David Feng3b5458c2013-12-14 11:47:37 +0800126
127/* Initial environment variables */
Linus Walleijc39566a2015-04-05 01:48:32 +0200128#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
129/*
130 * Defines where the kernel and FDT exist in NOR flash and where it will
131 * be copied into DRAM
132 */
133#define CONFIG_EXTRA_ENV_SETTINGS \
Ryan Harkin66fe7ee2015-10-09 17:18:07 +0100134 "kernel_name=norkern\0" \
135 "kernel_alt_name=Image\0" \
Andre Przywara11e56c42020-04-27 19:17:58 +0100136 "kernel_addr_r=0x80080000\0" \
137 "ramdisk_name=ramdisk.img\0" \
138 "ramdisk_addr_r=0x88000000\0" \
Alexander Grafaf684802016-03-04 01:10:11 +0100139 "fdtfile=board.dtb\0" \
Ryan Harkin66fe7ee2015-10-09 17:18:07 +0100140 "fdt_alt_name=juno\0" \
Andre Przywara11e56c42020-04-27 19:17:58 +0100141 "fdt_addr_r=0x80000000\0" \
Linus Walleijc39566a2015-04-05 01:48:32 +0200142
Stanislav Pinchukfb852b42021-01-20 21:54:53 +0300143#ifndef CONFIG_BOOTCOMMAND
Linus Walleijc39566a2015-04-05 01:48:32 +0200144/* Copy the kernel and FDT to DRAM memory and boot */
Andre Przywara11e56c42020-04-27 19:17:58 +0100145#define CONFIG_BOOTCOMMAND "afs load ${kernel_name} ${kernel_addr_r} ;"\
Ryan Harkin66fe7ee2015-10-09 17:18:07 +0100146 "if test $? -eq 1; then "\
147 " echo Loading ${kernel_alt_name} instead of "\
148 "${kernel_name}; "\
Andre Przywara11e56c42020-04-27 19:17:58 +0100149 " afs load ${kernel_alt_name} ${kernel_addr_r};"\
Ryan Harkin66fe7ee2015-10-09 17:18:07 +0100150 "fi ; "\
Andre Przywara11e56c42020-04-27 19:17:58 +0100151 "afs load ${fdtfile} ${fdt_addr_r} ;"\
Ryan Harkin66fe7ee2015-10-09 17:18:07 +0100152 "if test $? -eq 1; then "\
153 " echo Loading ${fdt_alt_name} instead of "\
Alexander Grafaf684802016-03-04 01:10:11 +0100154 "${fdtfile}; "\
Andre Przywara11e56c42020-04-27 19:17:58 +0100155 " afs load ${fdt_alt_name} ${fdt_addr_r}; "\
Ryan Harkin66fe7ee2015-10-09 17:18:07 +0100156 "fi ; "\
Andre Przywara11e56c42020-04-27 19:17:58 +0100157 "fdt addr ${fdt_addr_r}; fdt resize; " \
158 "if afs load ${ramdisk_name} ${ramdisk_addr_r} ; "\
Ryan Harkinf7e1e9e2015-10-09 17:18:06 +0100159 "then "\
Andre Przywara11e56c42020-04-27 19:17:58 +0100160 " setenv ramdisk_param ${ramdisk_addr_r}; "\
161 " else setenv ramdisk_param -; "\
Ryan Harkinf7e1e9e2015-10-09 17:18:06 +0100162 "fi ; " \
Andre Przywara11e56c42020-04-27 19:17:58 +0100163 "booti ${kernel_addr_r} ${ramdisk_param} ${fdt_addr_r}"
Stanislav Pinchukfb852b42021-01-20 21:54:53 +0300164#endif
Linus Walleijc39566a2015-04-05 01:48:32 +0200165
Linus Walleijc39566a2015-04-05 01:48:32 +0200166
167#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP
Darwin Rambod32d4112014-06-09 11:12:59 -0700168#define CONFIG_EXTRA_ENV_SETTINGS \
Linus Walleij4d30c9d2015-05-27 09:45:39 +0200169 "kernel_name=Image\0" \
Andre Przywaraa9415102016-01-04 15:43:36 +0000170 "kernel_addr=0x80080000\0" \
Darwin Rambod32d4112014-06-09 11:12:59 -0700171 "initrd_name=ramdisk.img\0" \
Linus Walleije08177c2015-03-23 11:06:12 +0100172 "initrd_addr=0x88000000\0" \
Alexander Grafaf684802016-03-04 01:10:11 +0100173 "fdtfile=devtree.dtb\0" \
Linus Walleije08177c2015-03-23 11:06:12 +0100174 "fdt_addr=0x83000000\0" \
Peter Collingbourne76254ab2020-04-03 19:58:24 -0700175 "boot_name=boot.img\0" \
176 "boot_addr=0x8007f800\0"
Darwin Rambod32d4112014-06-09 11:12:59 -0700177
Stanislav Pinchukfb852b42021-01-20 21:54:53 +0300178#ifndef CONFIG_BOOTCOMMAND
Peter Collingbourne76254ab2020-04-03 19:58:24 -0700179#define CONFIG_BOOTCOMMAND "if smhload ${boot_name} ${boot_addr}; then " \
180 " set bootargs; " \
181 " abootimg addr ${boot_addr}; " \
182 " abootimg get dtb --index=0 fdt_addr; " \
183 " bootm ${boot_addr} ${boot_addr} " \
184 " ${fdt_addr}; " \
185 "else; " \
186 " set fdt_high 0xffffffffffffffff; " \
187 " set initrd_high 0xffffffffffffffff; " \
188 " smhload ${kernel_name} ${kernel_addr}; " \
189 " smhload ${fdtfile} ${fdt_addr}; " \
190 " smhload ${initrd_name} ${initrd_addr} "\
191 " initrd_end; " \
192 " fdt addr ${fdt_addr}; fdt resize; " \
193 " fdt chosen ${initrd_addr} ${initrd_end}; " \
194 " booti $kernel_addr - $fdt_addr; " \
195 "fi"
Stanislav Pinchukfb852b42021-01-20 21:54:53 +0300196#endif
Darwin Rambod32d4112014-06-09 11:12:59 -0700197#endif
David Feng3b5458c2013-12-14 11:47:37 +0800198
David Feng3b5458c2013-12-14 11:47:37 +0800199/* Monitor Command Prompt */
200#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
David Feng3b5458c2013-12-14 11:47:37 +0800201#define CONFIG_SYS_MAXARGS 64 /* max command args */
202
Ryan Harkinad5b2a22015-11-18 10:39:09 +0000203#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
204#define CONFIG_SYS_FLASH_BASE 0x08000000
205/* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */
206#define CONFIG_SYS_MAX_FLASH_SECT 259
207/* Store environment at top of flash in the same location as blank.img */
208/* in the Juno firmware. */
Linus Walleij6ba4b6a2015-02-19 17:19:37 +0100209#else
Ryan Harkinad5b2a22015-11-18 10:39:09 +0000210#define CONFIG_SYS_FLASH_BASE 0x0C000000
211/* 256 x 256KiB sectors */
212#define CONFIG_SYS_MAX_FLASH_SECT 256
213/* Store environment at top of flash */
Ryan Harkinad5b2a22015-11-18 10:39:09 +0000214#endif
215
Ryan Harkinb1a4a672015-05-08 18:07:52 +0100216#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
Ryan Harkinad5b2a22015-11-18 10:39:09 +0000217#define CONFIG_SYS_MAX_FLASH_BANKS 1
Linus Walleij6ba4b6a2015-02-19 17:19:37 +0100218
Andre Przywarae3e81212020-04-27 19:18:03 +0100219#ifdef CONFIG_USB_EHCI_HCD
220#define CONFIG_USB_OHCI_NEW
221#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
222#endif
223
Linus Walleij6ba4b6a2015-02-19 17:19:37 +0100224#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
Ryan Harkinad5b2a22015-11-18 10:39:09 +0000225#define FLASH_MAX_SECTOR_SIZE 0x00040000
Linus Walleij6ba4b6a2015-02-19 17:19:37 +0100226
David Feng3b5458c2013-12-14 11:47:37 +0800227#endif /* __VEXPRESS_AEMV8A_H */