Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Configuration for Versatile Express. Parts were derived from other ARM |
| 4 | * configurations. |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __VEXPRESS_AEMV8A_H |
| 8 | #define __VEXPRESS_AEMV8A_H |
| 9 | |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 10 | #define CONFIG_REMAKE_ELF |
| 11 | |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 12 | /* Link Definitions */ |
Ryan Harkin | d700c3a | 2019-08-27 11:56:49 +0100 | [diff] [blame] | 13 | #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP |
Darwin Rambo | d32d411 | 2014-06-09 11:12:59 -0700 | [diff] [blame] | 14 | /* ATF loads u-boot here for BASE_FVP model */ |
Darwin Rambo | d32d411 | 2014-06-09 11:12:59 -0700 | [diff] [blame] | 15 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) |
Linus Walleij | c582250 | 2015-01-23 14:41:10 +0100 | [diff] [blame] | 16 | #elif CONFIG_TARGET_VEXPRESS64_JUNO |
Linus Walleij | c582250 | 2015-01-23 14:41:10 +0100 | [diff] [blame] | 17 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) |
Darwin Rambo | d32d411 | 2014-06-09 11:12:59 -0700 | [diff] [blame] | 18 | #endif |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 19 | |
Ryan Harkin | 642aa2c | 2015-10-09 17:18:01 +0100 | [diff] [blame] | 20 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
| 21 | |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 22 | /* CS register bases for the original memory map. */ |
| 23 | #define V2M_PA_CS0 0x00000000 |
| 24 | #define V2M_PA_CS1 0x14000000 |
| 25 | #define V2M_PA_CS2 0x18000000 |
| 26 | #define V2M_PA_CS3 0x1c000000 |
| 27 | #define V2M_PA_CS4 0x0c000000 |
| 28 | #define V2M_PA_CS5 0x10000000 |
| 29 | |
| 30 | #define V2M_PERIPH_OFFSET(x) (x << 16) |
| 31 | #define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1)) |
| 32 | #define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2)) |
| 33 | #define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3)) |
| 34 | |
| 35 | #define V2M_BASE 0x80000000 |
| 36 | |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 37 | /* Common peripherals relative to CS7. */ |
| 38 | #define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4)) |
| 39 | #define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5)) |
| 40 | #define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6)) |
| 41 | #define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7)) |
| 42 | |
Linus Walleij | c582250 | 2015-01-23 14:41:10 +0100 | [diff] [blame] | 43 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO |
| 44 | #define V2M_UART0 0x7ff80000 |
| 45 | #define V2M_UART1 0x7ff70000 |
| 46 | #else /* Not Juno */ |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 47 | #define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9)) |
| 48 | #define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10)) |
| 49 | #define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11)) |
| 50 | #define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12)) |
Linus Walleij | c582250 | 2015-01-23 14:41:10 +0100 | [diff] [blame] | 51 | #endif |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 52 | |
| 53 | #define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15)) |
| 54 | |
| 55 | #define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17)) |
| 56 | #define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18)) |
| 57 | |
| 58 | #define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22)) |
| 59 | #define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23)) |
| 60 | |
| 61 | #define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26)) |
| 62 | |
| 63 | #define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31)) |
| 64 | |
| 65 | /* System register offsets. */ |
| 66 | #define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0) |
| 67 | #define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4) |
| 68 | #define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8) |
| 69 | |
| 70 | /* Generic Timer Definitions */ |
Andre Przywara | 197b00e | 2020-06-11 12:03:15 +0100 | [diff] [blame] | 71 | #define COUNTER_FREQUENCY 24000000 /* 24MHz */ |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 72 | |
| 73 | /* Generic Interrupt Controller Definitions */ |
David Feng | 79bbde0 | 2014-03-14 14:26:27 +0800 | [diff] [blame] | 74 | #ifdef CONFIG_GICV3 |
| 75 | #define GICD_BASE (0x2f000000) |
| 76 | #define GICR_BASE (0x2f100000) |
| 77 | #else |
Darwin Rambo | d32d411 | 2014-06-09 11:12:59 -0700 | [diff] [blame] | 78 | |
Ryan Harkin | d700c3a | 2019-08-27 11:56:49 +0100 | [diff] [blame] | 79 | #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP |
Darwin Rambo | d32d411 | 2014-06-09 11:12:59 -0700 | [diff] [blame] | 80 | #define GICD_BASE (0x2f000000) |
| 81 | #define GICC_BASE (0x2c000000) |
Linus Walleij | c582250 | 2015-01-23 14:41:10 +0100 | [diff] [blame] | 82 | #elif CONFIG_TARGET_VEXPRESS64_JUNO |
| 83 | #define GICD_BASE (0x2C010000) |
| 84 | #define GICC_BASE (0x2C02f000) |
David Feng | 79bbde0 | 2014-03-14 14:26:27 +0800 | [diff] [blame] | 85 | #endif |
Linus Walleij | a90caa3 | 2015-03-23 11:06:14 +0100 | [diff] [blame] | 86 | #endif /* !CONFIG_GICV3 */ |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 87 | |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 88 | /* Size of malloc() pool */ |
Tom Rini | 7e76aa4 | 2014-08-14 06:42:37 -0400 | [diff] [blame] | 89 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 90 | |
Adam Ford | 0a044f8 | 2017-09-05 15:20:44 -0500 | [diff] [blame] | 91 | #ifndef CONFIG_TARGET_VEXPRESS64_JUNO |
Linus Walleij | 48b4755 | 2015-02-17 11:35:25 +0100 | [diff] [blame] | 92 | /* The Vexpress64 simulators use SMSC91C111 */ |
Bhupesh Sharma | e997f35 | 2014-01-16 09:47:40 -0600 | [diff] [blame] | 93 | #define CONFIG_SMC91111 1 |
| 94 | #define CONFIG_SMC91111_BASE (0x01A000000) |
Linus Walleij | 48b4755 | 2015-02-17 11:35:25 +0100 | [diff] [blame] | 95 | #endif |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 96 | |
| 97 | /* PL011 Serial Configuration */ |
Linus Walleij | c582250 | 2015-01-23 14:41:10 +0100 | [diff] [blame] | 98 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO |
Andre Przywara | d345718 | 2020-04-27 19:18:00 +0100 | [diff] [blame] | 99 | #define CONFIG_PL011_CLOCK 7372800 |
Linus Walleij | c582250 | 2015-01-23 14:41:10 +0100 | [diff] [blame] | 100 | #else |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 101 | #define CONFIG_PL011_CLOCK 24000000 |
Linus Walleij | c582250 | 2015-01-23 14:41:10 +0100 | [diff] [blame] | 102 | #endif |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 103 | |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 104 | /* BOOTP options */ |
| 105 | #define CONFIG_BOOTP_BOOTFILESIZE |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 106 | |
| 107 | /* Miscellaneous configurable options */ |
| 108 | #define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000) |
| 109 | |
| 110 | /* Physical Memory Map */ |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 111 | #define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ |
Linus Walleij | 0a38bfe | 2015-05-11 10:03:57 +0200 | [diff] [blame] | 112 | /* Top 16MB reserved for secure world use */ |
| 113 | #define DRAM_SEC_SIZE 0x01000000 |
| 114 | #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE |
| 115 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
| 116 | |
Ryan Harkin | 98d2fff | 2015-11-18 10:39:07 +0000 | [diff] [blame] | 117 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO |
Ryan Harkin | 98d2fff | 2015-11-18 10:39:07 +0000 | [diff] [blame] | 118 | #define PHYS_SDRAM_2 (0x880000000) |
| 119 | #define PHYS_SDRAM_2_SIZE 0x180000000 |
Diego Sueiro | 7a02a1b | 2021-02-15 07:27:57 +0000 | [diff] [blame] | 120 | #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP && CONFIG_NR_DRAM_BANKS == 2 |
| 121 | #define PHYS_SDRAM_2 (0x880000000) |
| 122 | #define PHYS_SDRAM_2_SIZE 0x80000000 |
Ryan Harkin | 98d2fff | 2015-11-18 10:39:07 +0000 | [diff] [blame] | 123 | #endif |
| 124 | |
Linus Walleij | 0a38bfe | 2015-05-11 10:03:57 +0200 | [diff] [blame] | 125 | /* Enable memtest */ |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 126 | |
| 127 | /* Initial environment variables */ |
Linus Walleij | c39566a | 2015-04-05 01:48:32 +0200 | [diff] [blame] | 128 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO |
| 129 | /* |
| 130 | * Defines where the kernel and FDT exist in NOR flash and where it will |
| 131 | * be copied into DRAM |
| 132 | */ |
| 133 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Ryan Harkin | 66fe7ee | 2015-10-09 17:18:07 +0100 | [diff] [blame] | 134 | "kernel_name=norkern\0" \ |
| 135 | "kernel_alt_name=Image\0" \ |
Andre Przywara | 11e56c4 | 2020-04-27 19:17:58 +0100 | [diff] [blame] | 136 | "kernel_addr_r=0x80080000\0" \ |
| 137 | "ramdisk_name=ramdisk.img\0" \ |
| 138 | "ramdisk_addr_r=0x88000000\0" \ |
Alexander Graf | af68480 | 2016-03-04 01:10:11 +0100 | [diff] [blame] | 139 | "fdtfile=board.dtb\0" \ |
Ryan Harkin | 66fe7ee | 2015-10-09 17:18:07 +0100 | [diff] [blame] | 140 | "fdt_alt_name=juno\0" \ |
Andre Przywara | 11e56c4 | 2020-04-27 19:17:58 +0100 | [diff] [blame] | 141 | "fdt_addr_r=0x80000000\0" \ |
Linus Walleij | c39566a | 2015-04-05 01:48:32 +0200 | [diff] [blame] | 142 | |
Stanislav Pinchuk | fb852b4 | 2021-01-20 21:54:53 +0300 | [diff] [blame] | 143 | #ifndef CONFIG_BOOTCOMMAND |
Linus Walleij | c39566a | 2015-04-05 01:48:32 +0200 | [diff] [blame] | 144 | /* Copy the kernel and FDT to DRAM memory and boot */ |
Andre Przywara | 11e56c4 | 2020-04-27 19:17:58 +0100 | [diff] [blame] | 145 | #define CONFIG_BOOTCOMMAND "afs load ${kernel_name} ${kernel_addr_r} ;"\ |
Ryan Harkin | 66fe7ee | 2015-10-09 17:18:07 +0100 | [diff] [blame] | 146 | "if test $? -eq 1; then "\ |
| 147 | " echo Loading ${kernel_alt_name} instead of "\ |
| 148 | "${kernel_name}; "\ |
Andre Przywara | 11e56c4 | 2020-04-27 19:17:58 +0100 | [diff] [blame] | 149 | " afs load ${kernel_alt_name} ${kernel_addr_r};"\ |
Ryan Harkin | 66fe7ee | 2015-10-09 17:18:07 +0100 | [diff] [blame] | 150 | "fi ; "\ |
Andre Przywara | 11e56c4 | 2020-04-27 19:17:58 +0100 | [diff] [blame] | 151 | "afs load ${fdtfile} ${fdt_addr_r} ;"\ |
Ryan Harkin | 66fe7ee | 2015-10-09 17:18:07 +0100 | [diff] [blame] | 152 | "if test $? -eq 1; then "\ |
| 153 | " echo Loading ${fdt_alt_name} instead of "\ |
Alexander Graf | af68480 | 2016-03-04 01:10:11 +0100 | [diff] [blame] | 154 | "${fdtfile}; "\ |
Andre Przywara | 11e56c4 | 2020-04-27 19:17:58 +0100 | [diff] [blame] | 155 | " afs load ${fdt_alt_name} ${fdt_addr_r}; "\ |
Ryan Harkin | 66fe7ee | 2015-10-09 17:18:07 +0100 | [diff] [blame] | 156 | "fi ; "\ |
Andre Przywara | 11e56c4 | 2020-04-27 19:17:58 +0100 | [diff] [blame] | 157 | "fdt addr ${fdt_addr_r}; fdt resize; " \ |
| 158 | "if afs load ${ramdisk_name} ${ramdisk_addr_r} ; "\ |
Ryan Harkin | f7e1e9e | 2015-10-09 17:18:06 +0100 | [diff] [blame] | 159 | "then "\ |
Andre Przywara | 11e56c4 | 2020-04-27 19:17:58 +0100 | [diff] [blame] | 160 | " setenv ramdisk_param ${ramdisk_addr_r}; "\ |
| 161 | " else setenv ramdisk_param -; "\ |
Ryan Harkin | f7e1e9e | 2015-10-09 17:18:06 +0100 | [diff] [blame] | 162 | "fi ; " \ |
Andre Przywara | 11e56c4 | 2020-04-27 19:17:58 +0100 | [diff] [blame] | 163 | "booti ${kernel_addr_r} ${ramdisk_param} ${fdt_addr_r}" |
Stanislav Pinchuk | fb852b4 | 2021-01-20 21:54:53 +0300 | [diff] [blame] | 164 | #endif |
Linus Walleij | c39566a | 2015-04-05 01:48:32 +0200 | [diff] [blame] | 165 | |
Linus Walleij | c39566a | 2015-04-05 01:48:32 +0200 | [diff] [blame] | 166 | |
| 167 | #elif CONFIG_TARGET_VEXPRESS64_BASE_FVP |
Darwin Rambo | d32d411 | 2014-06-09 11:12:59 -0700 | [diff] [blame] | 168 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Linus Walleij | 4d30c9d | 2015-05-27 09:45:39 +0200 | [diff] [blame] | 169 | "kernel_name=Image\0" \ |
Andre Przywara | a941510 | 2016-01-04 15:43:36 +0000 | [diff] [blame] | 170 | "kernel_addr=0x80080000\0" \ |
Darwin Rambo | d32d411 | 2014-06-09 11:12:59 -0700 | [diff] [blame] | 171 | "initrd_name=ramdisk.img\0" \ |
Linus Walleij | e08177c | 2015-03-23 11:06:12 +0100 | [diff] [blame] | 172 | "initrd_addr=0x88000000\0" \ |
Alexander Graf | af68480 | 2016-03-04 01:10:11 +0100 | [diff] [blame] | 173 | "fdtfile=devtree.dtb\0" \ |
Linus Walleij | e08177c | 2015-03-23 11:06:12 +0100 | [diff] [blame] | 174 | "fdt_addr=0x83000000\0" \ |
Peter Collingbourne | 76254ab | 2020-04-03 19:58:24 -0700 | [diff] [blame] | 175 | "boot_name=boot.img\0" \ |
| 176 | "boot_addr=0x8007f800\0" |
Darwin Rambo | d32d411 | 2014-06-09 11:12:59 -0700 | [diff] [blame] | 177 | |
Stanislav Pinchuk | fb852b4 | 2021-01-20 21:54:53 +0300 | [diff] [blame] | 178 | #ifndef CONFIG_BOOTCOMMAND |
Peter Collingbourne | 76254ab | 2020-04-03 19:58:24 -0700 | [diff] [blame] | 179 | #define CONFIG_BOOTCOMMAND "if smhload ${boot_name} ${boot_addr}; then " \ |
| 180 | " set bootargs; " \ |
| 181 | " abootimg addr ${boot_addr}; " \ |
| 182 | " abootimg get dtb --index=0 fdt_addr; " \ |
| 183 | " bootm ${boot_addr} ${boot_addr} " \ |
| 184 | " ${fdt_addr}; " \ |
| 185 | "else; " \ |
| 186 | " set fdt_high 0xffffffffffffffff; " \ |
| 187 | " set initrd_high 0xffffffffffffffff; " \ |
| 188 | " smhload ${kernel_name} ${kernel_addr}; " \ |
| 189 | " smhload ${fdtfile} ${fdt_addr}; " \ |
| 190 | " smhload ${initrd_name} ${initrd_addr} "\ |
| 191 | " initrd_end; " \ |
| 192 | " fdt addr ${fdt_addr}; fdt resize; " \ |
| 193 | " fdt chosen ${initrd_addr} ${initrd_end}; " \ |
| 194 | " booti $kernel_addr - $fdt_addr; " \ |
| 195 | "fi" |
Stanislav Pinchuk | fb852b4 | 2021-01-20 21:54:53 +0300 | [diff] [blame] | 196 | #endif |
Darwin Rambo | d32d411 | 2014-06-09 11:12:59 -0700 | [diff] [blame] | 197 | #endif |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 198 | |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 199 | /* Monitor Command Prompt */ |
| 200 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 201 | #define CONFIG_SYS_MAXARGS 64 /* max command args */ |
| 202 | |
Ryan Harkin | ad5b2a2 | 2015-11-18 10:39:09 +0000 | [diff] [blame] | 203 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO |
| 204 | #define CONFIG_SYS_FLASH_BASE 0x08000000 |
| 205 | /* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */ |
| 206 | #define CONFIG_SYS_MAX_FLASH_SECT 259 |
| 207 | /* Store environment at top of flash in the same location as blank.img */ |
| 208 | /* in the Juno firmware. */ |
Linus Walleij | 6ba4b6a | 2015-02-19 17:19:37 +0100 | [diff] [blame] | 209 | #else |
Ryan Harkin | ad5b2a2 | 2015-11-18 10:39:09 +0000 | [diff] [blame] | 210 | #define CONFIG_SYS_FLASH_BASE 0x0C000000 |
| 211 | /* 256 x 256KiB sectors */ |
| 212 | #define CONFIG_SYS_MAX_FLASH_SECT 256 |
| 213 | /* Store environment at top of flash */ |
Ryan Harkin | ad5b2a2 | 2015-11-18 10:39:09 +0000 | [diff] [blame] | 214 | #endif |
| 215 | |
Ryan Harkin | b1a4a67 | 2015-05-08 18:07:52 +0100 | [diff] [blame] | 216 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT |
Ryan Harkin | ad5b2a2 | 2015-11-18 10:39:09 +0000 | [diff] [blame] | 217 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
Linus Walleij | 6ba4b6a | 2015-02-19 17:19:37 +0100 | [diff] [blame] | 218 | |
Andre Przywara | e3e8121 | 2020-04-27 19:18:03 +0100 | [diff] [blame] | 219 | #ifdef CONFIG_USB_EHCI_HCD |
| 220 | #define CONFIG_USB_OHCI_NEW |
| 221 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 |
| 222 | #endif |
| 223 | |
Linus Walleij | 6ba4b6a | 2015-02-19 17:19:37 +0100 | [diff] [blame] | 224 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ |
Ryan Harkin | ad5b2a2 | 2015-11-18 10:39:09 +0000 | [diff] [blame] | 225 | #define FLASH_MAX_SECTOR_SIZE 0x00040000 |
Linus Walleij | 6ba4b6a | 2015-02-19 17:19:37 +0100 | [diff] [blame] | 226 | |
David Feng | 3b5458c | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 227 | #endif /* __VEXPRESS_AEMV8A_H */ |