blob: 196903e406c38df897e65806e823bac17969c5d4 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Marek Vasutf3b8bf72017-07-21 23:18:03 +02002/*
Marek Vasut3f1a3a12017-10-09 20:52:33 +02003 * Renesas RCar Gen3 CPG MSSR driver
Marek Vasutf3b8bf72017-07-21 23:18:03 +02004 *
5 * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
6 *
7 * Based on the following driver from Linux kernel:
8 * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
9 *
10 * Copyright (C) 2016 Glider bvba
Marek Vasutf3b8bf72017-07-21 23:18:03 +020011 */
12
Marek Vasutf3b8bf72017-07-21 23:18:03 +020013#include <clk-uclass.h>
14#include <dm.h>
Marek Vasutf6b32022023-01-26 21:02:03 +010015#include <dm/device-internal.h>
16#include <dm/lists.h>
Marek Vasutf3b8bf72017-07-21 23:18:03 +020017#include <errno.h>
Simon Glass0f2af882020-05-10 11:40:05 -060018#include <log.h>
Marek Vasutf3b8bf72017-07-21 23:18:03 +020019#include <wait_bit.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060020#include <asm/global_data.h>
Marek Vasutf3b8bf72017-07-21 23:18:03 +020021#include <asm/io.h>
Hai Phame83700a2023-01-26 21:06:03 +010022#include <linux/bitfield.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060023#include <linux/bitops.h>
Marek Vasutb2970fd2023-01-26 21:06:02 +010024#include <linux/clk-provider.h>
Marek Vasutf6b32022023-01-26 21:02:03 +010025#include <reset-uclass.h>
Marek Vasutf3b8bf72017-07-21 23:18:03 +020026
Marek Vasut4eb4e6e2018-01-08 14:01:40 +010027#include <dt-bindings/clock/renesas-cpg-mssr.h>
28
29#include "renesas-cpg-mssr.h"
Marek Vasute11008b2018-01-15 16:44:39 +010030#include "rcar-gen3-cpg.h"
Hai Pham06d8f972023-01-26 21:06:07 +010031#include "rcar-cpg-lib.h"
Marek Vasutf3b8bf72017-07-21 23:18:03 +020032
Marek Vasutf3b8bf72017-07-21 23:18:03 +020033#define CPG_PLL0CR 0x00d8
34#define CPG_PLL2CR 0x002c
35#define CPG_PLL4CR 0x01f4
36
Marek Vasutba2c7d22023-02-28 22:34:38 +010037#define SD0CKCR1 0x08a4
38
39static const struct clk_div_table gen3_cpg_rpcsrc_div_table[] = {
Hai Phame83700a2023-01-26 21:06:03 +010040 { 2, 5 }, { 3, 6 }, { 0, 0 },
41};
42
Marek Vasutba2c7d22023-02-28 22:34:38 +010043static const struct clk_div_table gen4_cpg_rpcsrc_div_table[] = {
44 { 0, 4 }, { 1, 6 }, { 2, 5 }, { 3, 6 }, { 0, 0 },
45};
46
Hai Pham6811b572023-01-26 21:06:06 +010047static const struct clk_div_table r8a77970_cpg_sd0h_div_table[] = {
48 { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
49 { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
50 { 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 },
51};
52
53static const struct clk_div_table r8a77970_cpg_sd0_div_table[] = {
54 { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
55 { 8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 },
56 { 0, 0 },
57};
58
Marek Vasut69459b22018-05-31 19:47:42 +020059static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk,
60 struct cpg_mssr_info *info, struct clk *parent)
61{
62 const struct cpg_core_clk *core;
Marek Vasutea8505e2023-02-28 07:25:11 +010063 u8 shift;
Marek Vasut69459b22018-05-31 19:47:42 +020064 int ret;
65
66 if (!renesas_clk_is_mod(clk)) {
67 ret = renesas_clk_get_core(clk, info, &core);
68 if (ret)
69 return ret;
70
Marek Vasut78414832019-03-04 21:38:10 +010071 if (core->type == CLK_TYPE_GEN3_MDSEL) {
Marek Vasutea8505e2023-02-28 07:25:11 +010072 shift = priv->cpg_mode & BIT(core->offset) ? 16 : 0;
Marek Vasut69459b22018-05-31 19:47:42 +020073 parent->dev = clk->dev;
Marek Vasutea8505e2023-02-28 07:25:11 +010074 parent->id = core->parent >> shift;
Marek Vasut69459b22018-05-31 19:47:42 +020075 parent->id &= 0xffff;
76 return 0;
77 }
78 }
79
80 return renesas_clk_get_parent(clk, info, parent);
81}
82
Hai Pham4dae0762023-01-29 02:50:22 +010083static int gen3_clk_enable(struct clk *clk)
84{
85 struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
86
87 return renesas_clk_endisable(clk, priv->base, priv->info, true);
88}
89
90static int gen3_clk_disable(struct clk *clk)
91{
92 struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
93
94 return renesas_clk_endisable(clk, priv->base, priv->info, false);
95}
96
97static u64 gen3_clk_get_rate64(struct clk *clk);
98
Marek Vasutc26bf892018-10-30 17:54:20 +010099static int gen3_clk_setup_sdif_div(struct clk *clk, ulong rate)
Marek Vasut5a51be52017-09-15 21:10:08 +0200100{
101 struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
Marek Vasute11008b2018-01-15 16:44:39 +0100102 struct cpg_mssr_info *info = priv->info;
Marek Vasut5a51be52017-09-15 21:10:08 +0200103 const struct cpg_core_clk *core;
Hai Pham4dae0762023-01-29 02:50:22 +0100104 struct clk parent, grandparent;
Marek Vasut5a51be52017-09-15 21:10:08 +0200105 int ret;
106
Hai Pham4dae0762023-01-29 02:50:22 +0100107 /*
108 * The clk may be either CPG_MOD or core clock, in case this is MOD
109 * clock, use core clock one level up, otherwise use the clock as-is.
110 * Note that parent clock here always represents core clock. Also note
111 * that grandparent clock are the parent clock of the core clock here.
112 */
113 if (renesas_clk_is_mod(clk)) {
114 ret = gen3_clk_get_parent(priv, clk, info, &parent);
115 if (ret) {
116 printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
117 return ret;
118 }
119 } else {
120 parent = *clk;
Marek Vasut5a51be52017-09-15 21:10:08 +0200121 }
122
Marek Vasute11008b2018-01-15 16:44:39 +0100123 if (renesas_clk_is_mod(&parent))
Marek Vasut5a51be52017-09-15 21:10:08 +0200124 return 0;
125
Marek Vasute11008b2018-01-15 16:44:39 +0100126 ret = renesas_clk_get_core(&parent, info, &core);
Marek Vasut5a51be52017-09-15 21:10:08 +0200127 if (ret)
128 return ret;
129
Hai Pham4dae0762023-01-29 02:50:22 +0100130 ret = renesas_clk_get_parent(&parent, info, &grandparent);
131 if (ret) {
132 printf("%s[%i] grandparent fail, ret=%i\n", __func__, __LINE__, ret);
133 return ret;
134 }
Marek Vasut5a51be52017-09-15 21:10:08 +0200135
Hai Pham4dae0762023-01-29 02:50:22 +0100136 switch (core->type) {
137 case CLK_TYPE_GEN3_SDH:
138 fallthrough;
139 case CLK_TYPE_GEN4_SDH:
Hai Pham06d8f972023-01-26 21:06:07 +0100140 return rcar_clk_set_rate64_sdh(core->parent,
141 gen3_clk_get_rate64(&grandparent),
142 rate, priv->base + core->offset);
Marek Vasut5a51be52017-09-15 21:10:08 +0200143
Hai Pham4dae0762023-01-29 02:50:22 +0100144 case CLK_TYPE_GEN3_SD:
145 fallthrough;
146 case CLK_TYPE_GEN4_SD:
Hai Pham06d8f972023-01-26 21:06:07 +0100147 return rcar_clk_set_rate64_sd(core->parent,
148 gen3_clk_get_rate64(&grandparent),
149 rate, priv->base + core->offset);
Hai Pham6811b572023-01-26 21:06:06 +0100150
151 case CLK_TYPE_R8A77970_SD0:
Hai Pham06d8f972023-01-26 21:06:07 +0100152 return rcar_clk_set_rate64_div_table(core->parent,
153 gen3_clk_get_rate64(&grandparent),
154 rate, priv->base + core->offset,
155 CPG_SDCKCR_SD0FC_MASK,
156 r8a77970_cpg_sd0_div_table, "SD");
Hai Pham4dae0762023-01-29 02:50:22 +0100157 }
Marek Vasute11008b2018-01-15 16:44:39 +0100158
Hai Pham4dae0762023-01-29 02:50:22 +0100159 return 0;
Marek Vasutf3b8bf72017-07-21 23:18:03 +0200160}
161
Marek Vasut8f567862021-04-27 19:36:39 +0200162static u64 gen3_clk_get_rate64_pll_mul_reg(struct gen3_clk_priv *priv,
163 struct clk *parent,
Marek Vasut8f567862021-04-27 19:36:39 +0200164 u32 mul_reg, u32 mult, u32 div,
165 char *name)
166{
167 u32 value;
168 u64 rate;
169
170 if (mul_reg) {
171 value = readl(priv->base + mul_reg);
172 mult = (((value >> 24) & 0x7f) + 1) * 2;
173 div = 1;
174 }
175
176 rate = (gen3_clk_get_rate64(parent) * mult) / div;
177
Marek Vasut1bd25212023-01-26 21:02:05 +0100178 debug("%s[%i] %s clk: mult=%u div=%u => rate=%llu\n",
179 __func__, __LINE__, name, mult, div, rate);
Marek Vasut8f567862021-04-27 19:36:39 +0200180 return rate;
181}
182
Marek Vasut7571ac42018-05-31 19:06:02 +0200183static u64 gen3_clk_get_rate64(struct clk *clk)
Marek Vasutf3b8bf72017-07-21 23:18:03 +0200184{
185 struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
Marek Vasutb9234192018-01-08 16:05:28 +0100186 struct cpg_mssr_info *info = priv->info;
Marek Vasutf3b8bf72017-07-21 23:18:03 +0200187 struct clk parent;
188 const struct cpg_core_clk *core;
Marek Vasutba2c7d22023-02-28 22:34:38 +0100189 const struct rcar_gen3_cpg_pll_config *gen3_pll_config =
190 priv->gen3_cpg_pll_config;
191 const struct rcar_gen4_cpg_pll_config *gen4_pll_config =
192 priv->gen4_cpg_pll_config;
Hai Phame83700a2023-01-26 21:06:03 +0100193 u32 value, div;
Marek Vasut7571ac42018-05-31 19:06:02 +0200194 u64 rate = 0;
Marek Vasutea8505e2023-02-28 07:25:11 +0100195 u8 shift;
Hai Pham4dae0762023-01-29 02:50:22 +0100196 int ret;
Marek Vasutf3b8bf72017-07-21 23:18:03 +0200197
198 debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
199
Marek Vasut69459b22018-05-31 19:47:42 +0200200 ret = gen3_clk_get_parent(priv, clk, info, &parent);
Marek Vasutf3b8bf72017-07-21 23:18:03 +0200201 if (ret) {
202 printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
203 return ret;
204 }
205
Marek Vasute11008b2018-01-15 16:44:39 +0100206 if (renesas_clk_is_mod(clk)) {
Marek Vasut7571ac42018-05-31 19:06:02 +0200207 rate = gen3_clk_get_rate64(&parent);
208 debug("%s[%i] MOD clk: parent=%lu => rate=%llu\n",
Marek Vasutf3b8bf72017-07-21 23:18:03 +0200209 __func__, __LINE__, parent.id, rate);
210 return rate;
211 }
212
Marek Vasute11008b2018-01-15 16:44:39 +0100213 ret = renesas_clk_get_core(clk, info, &core);
Marek Vasutf3b8bf72017-07-21 23:18:03 +0200214 if (ret)
215 return ret;
216
217 switch (core->type) {
218 case CLK_TYPE_IN:
Marek Vasutb9234192018-01-08 16:05:28 +0100219 if (core->id == info->clk_extal_id) {
Marek Vasutf3b8bf72017-07-21 23:18:03 +0200220 rate = clk_get_rate(&priv->clk_extal);
Marek Vasut7571ac42018-05-31 19:06:02 +0200221 debug("%s[%i] EXTAL clk: rate=%llu\n",
Marek Vasutf3b8bf72017-07-21 23:18:03 +0200222 __func__, __LINE__, rate);
223 return rate;
224 }
225
Marek Vasutb9234192018-01-08 16:05:28 +0100226 if (core->id == info->clk_extalr_id) {
Marek Vasutf3b8bf72017-07-21 23:18:03 +0200227 rate = clk_get_rate(&priv->clk_extalr);
Marek Vasut7571ac42018-05-31 19:06:02 +0200228 debug("%s[%i] EXTALR clk: rate=%llu\n",
Marek Vasutf3b8bf72017-07-21 23:18:03 +0200229 __func__, __LINE__, rate);
230 return rate;
231 }
232
233 return -EINVAL;
234
235 case CLK_TYPE_GEN3_MAIN:
Marek Vasut1bd25212023-01-26 21:02:05 +0100236 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
Marek Vasutba2c7d22023-02-28 22:34:38 +0100237 0, 1, gen3_pll_config->extal_div,
Marek Vasut8f567862021-04-27 19:36:39 +0200238 "MAIN");
Marek Vasutf3b8bf72017-07-21 23:18:03 +0200239
240 case CLK_TYPE_GEN3_PLL0:
Marek Vasut1bd25212023-01-26 21:02:05 +0100241 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
Marek Vasut8f567862021-04-27 19:36:39 +0200242 CPG_PLL0CR, 0, 0, "PLL0");
Marek Vasutf3b8bf72017-07-21 23:18:03 +0200243
244 case CLK_TYPE_GEN3_PLL1:
Marek Vasut1bd25212023-01-26 21:02:05 +0100245 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
Marek Vasutba2c7d22023-02-28 22:34:38 +0100246 0, gen3_pll_config->pll1_mult,
247 gen3_pll_config->pll1_div,
248 "PLL1");
Marek Vasutf3b8bf72017-07-21 23:18:03 +0200249
250 case CLK_TYPE_GEN3_PLL2:
Marek Vasut1bd25212023-01-26 21:02:05 +0100251 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
Marek Vasut8f567862021-04-27 19:36:39 +0200252 CPG_PLL2CR, 0, 0, "PLL2");
Marek Vasutf3b8bf72017-07-21 23:18:03 +0200253
254 case CLK_TYPE_GEN3_PLL3:
Marek Vasut1bd25212023-01-26 21:02:05 +0100255 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
Marek Vasutba2c7d22023-02-28 22:34:38 +0100256 0, gen3_pll_config->pll3_mult,
257 gen3_pll_config->pll3_div,
258 "PLL3");
Marek Vasutf3b8bf72017-07-21 23:18:03 +0200259
260 case CLK_TYPE_GEN3_PLL4:
Marek Vasut1bd25212023-01-26 21:02:05 +0100261 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
Marek Vasut8f567862021-04-27 19:36:39 +0200262 CPG_PLL4CR, 0, 0, "PLL4");
Marek Vasutf3b8bf72017-07-21 23:18:03 +0200263
Marek Vasut569acef2023-01-26 21:01:56 +0100264 case CLK_TYPE_GEN4_MAIN:
Marek Vasut1bd25212023-01-26 21:02:05 +0100265 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
Marek Vasutba2c7d22023-02-28 22:34:38 +0100266 0, 1, gen4_pll_config->extal_div,
267 "MAIN");
Marek Vasut0fbb8a72021-04-27 19:52:53 +0200268
Marek Vasut569acef2023-01-26 21:01:56 +0100269 case CLK_TYPE_GEN4_PLL1:
Marek Vasut1bd25212023-01-26 21:02:05 +0100270 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
Marek Vasutba2c7d22023-02-28 22:34:38 +0100271 0, gen4_pll_config->pll1_mult,
272 gen4_pll_config->pll1_div,
273 "PLL1");
274
275 case CLK_TYPE_GEN4_PLL2:
276 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
277 0, gen4_pll_config->pll2_mult,
278 gen4_pll_config->pll2_div,
279 "PLL2");
Marek Vasut0fbb8a72021-04-27 19:52:53 +0200280
Marek Vasut569acef2023-01-26 21:01:56 +0100281 case CLK_TYPE_GEN4_PLL2X_3X:
Marek Vasut1bd25212023-01-26 21:02:05 +0100282 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
Marek Vasutba2c7d22023-02-28 22:34:38 +0100283 core->offset, 0, 0, "PLL2X_3X");
284
285 case CLK_TYPE_GEN4_PLL3:
286 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
287 0, gen4_pll_config->pll3_mult,
288 gen4_pll_config->pll3_div,
289 "PLL3");
290
291 case CLK_TYPE_GEN4_PLL4:
292 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
293 0, gen4_pll_config->pll4_mult,
294 gen4_pll_config->pll4_div,
295 "PLL4");
Marek Vasut0fbb8a72021-04-27 19:52:53 +0200296
Marek Vasut569acef2023-01-26 21:01:56 +0100297 case CLK_TYPE_GEN4_PLL5:
Marek Vasut1bd25212023-01-26 21:02:05 +0100298 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
Marek Vasutba2c7d22023-02-28 22:34:38 +0100299 0, gen4_pll_config->pll5_mult,
300 gen4_pll_config->pll5_div,
301 "PLL5");
302
303 case CLK_TYPE_GEN4_PLL6:
304 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
305 0, gen4_pll_config->pll6_mult,
306 gen4_pll_config->pll6_div,
307 "PLL6");
Marek Vasut0fbb8a72021-04-27 19:52:53 +0200308
Marek Vasutf3b8bf72017-07-21 23:18:03 +0200309 case CLK_TYPE_FF:
Marek Vasut1bd25212023-01-26 21:02:05 +0100310 return gen3_clk_get_rate64_pll_mul_reg(priv, &parent,
Marek Vasut8f567862021-04-27 19:36:39 +0200311 0, core->mult, core->div,
312 "FIXED");
Marek Vasutf3b8bf72017-07-21 23:18:03 +0200313
Marek Vasut78414832019-03-04 21:38:10 +0100314 case CLK_TYPE_GEN3_MDSEL:
Marek Vasutea8505e2023-02-28 07:25:11 +0100315 shift = priv->cpg_mode & BIT(core->offset) ? 16 : 0;
316 div = (core->div >> shift) & 0xffff;
Marek Vasut69459b22018-05-31 19:47:42 +0200317 rate = gen3_clk_get_rate64(&parent) / div;
318 debug("%s[%i] PE clk: parent=%i div=%u => rate=%llu\n",
Marek Vasutea8505e2023-02-28 07:25:11 +0100319 __func__, __LINE__, (core->parent >> shift) & 0xffff,
Marek Vasut69459b22018-05-31 19:47:42 +0200320 div, rate);
321 return rate;
322
Marek Vasutba2c7d22023-02-28 22:34:38 +0100323 case CLK_TYPE_GEN4_SDSRC:
324 div = ((readl(priv->base + SD0CKCR1) >> 29) & 0x03) + 4;
325 rate = gen3_clk_get_rate64(&parent) / div;
326 debug("%s[%i] SDSRC clk: parent=%i div=%u => rate=%llu\n",
327 __func__, __LINE__, core->parent, div, rate);
328 return rate;
329
Hai Pham0985e0e2023-01-26 21:01:49 +0100330 case CLK_TYPE_GEN3_SDH: /* Fixed factor 1:1 */
Marek Vasut569acef2023-01-26 21:01:56 +0100331 fallthrough;
332 case CLK_TYPE_GEN4_SDH: /* Fixed factor 1:1 */
Hai Pham06d8f972023-01-26 21:06:07 +0100333 return rcar_clk_get_rate64_sdh(core->parent,
334 gen3_clk_get_rate64(&parent),
335 priv->base + core->offset);
Hai Pham0985e0e2023-01-26 21:01:49 +0100336
Hai Pham6811b572023-01-26 21:06:06 +0100337 case CLK_TYPE_R8A77970_SD0H:
338 return rcar_clk_get_rate64_div_table(core->parent,
339 gen3_clk_get_rate64(&parent),
340 priv->base + core->offset,
341 CPG_SDCKCR_SDHFC_MASK,
342 r8a77970_cpg_sd0h_div_table, "SDH");
343
Hai Pham4dae0762023-01-29 02:50:22 +0100344 case CLK_TYPE_GEN3_SD:
Marek Vasut0fbb8a72021-04-27 19:52:53 +0200345 fallthrough;
Marek Vasut569acef2023-01-26 21:01:56 +0100346 case CLK_TYPE_GEN4_SD:
Hai Pham06d8f972023-01-26 21:06:07 +0100347 return rcar_clk_get_rate64_sd(core->parent,
348 gen3_clk_get_rate64(&parent),
349 priv->base + core->offset);
Marek Vasutc1aee322017-09-15 21:10:29 +0200350
Hai Pham6811b572023-01-26 21:06:06 +0100351 case CLK_TYPE_R8A77970_SD0:
352 return rcar_clk_get_rate64_div_table(core->parent,
353 gen3_clk_get_rate64(&parent),
354 priv->base + core->offset,
355 CPG_SDCKCR_SD0FC_MASK,
356 r8a77970_cpg_sd0_div_table, "SD");
357
Hai Phame83700a2023-01-26 21:06:03 +0100358 case CLK_TYPE_GEN3_RPCSRC:
359 return rcar_clk_get_rate64_div_table(core->parent,
360 gen3_clk_get_rate64(&parent),
361 priv->base + CPG_RPCCKCR,
362 CPG_RPCCKCR_DIV_POST_MASK,
Marek Vasutba2c7d22023-02-28 22:34:38 +0100363 gen3_cpg_rpcsrc_div_table,
364 "RPCSRC");
365
366 case CLK_TYPE_GEN4_RPCSRC:
367 return rcar_clk_get_rate64_div_table(core->parent,
368 gen3_clk_get_rate64(&parent),
369 priv->base + CPG_RPCCKCR,
370 CPG_RPCCKCR_DIV_POST_MASK,
371 gen4_cpg_rpcsrc_div_table,
372 "RPCSRC");
Hai Phame83700a2023-01-26 21:06:03 +0100373
Hai Pham85e691e2023-01-26 21:06:04 +0100374 case CLK_TYPE_GEN3_D3_RPCSRC:
375 case CLK_TYPE_GEN3_E3_RPCSRC:
376 /*
377 * Register RPCSRC as fixed factor clock based on the
378 * MD[4:1] pins and CPG_RPCCKCR[4:3] register value for
379 * which has been set prior to booting the kernel.
380 */
381 value = (readl(priv->base + CPG_RPCCKCR) & GENMASK(4, 3)) >> 3;
382
383 switch (value) {
384 case 0:
385 div = 5;
386 break;
387 case 1:
388 div = 3;
389 break;
390 case 2:
391 div = core->div;
392 break;
393 case 3:
394 default:
395 div = 2;
396 break;
397 }
398
399 rate = gen3_clk_get_rate64(&parent) / div;
400 debug("%s[%i] E3/D3 RPCSRC clk: parent=%i div=%u => rate=%llu\n",
401 __func__, __LINE__, (core->parent >> 16) & 0xffff, div, rate);
402
403 return rate;
404
Marek Vasutc1aee322017-09-15 21:10:29 +0200405 case CLK_TYPE_GEN3_RPC:
Marek Vasut569acef2023-01-26 21:01:56 +0100406 case CLK_TYPE_GEN4_RPC:
Hai Pham06d8f972023-01-26 21:06:07 +0100407 return rcar_clk_get_rate64_rpc(core->parent,
408 gen3_clk_get_rate64(&parent),
409 priv->base + CPG_RPCCKCR);
Marek Vasutc1aee322017-09-15 21:10:29 +0200410
Hai Phame83700a2023-01-26 21:06:03 +0100411 case CLK_TYPE_GEN3_RPCD2:
412 case CLK_TYPE_GEN4_RPCD2:
Hai Pham06d8f972023-01-26 21:06:07 +0100413 return rcar_clk_get_rate64_rpcd2(core->parent,
414 gen3_clk_get_rate64(&parent));
Marek Vasutc1aee322017-09-15 21:10:29 +0200415
Marek Vasutf3b8bf72017-07-21 23:18:03 +0200416 }
417
418 printf("%s[%i] unknown fail\n", __func__, __LINE__);
419
420 return -ENOENT;
421}
422
Marek Vasut7571ac42018-05-31 19:06:02 +0200423static ulong gen3_clk_get_rate(struct clk *clk)
424{
425 return gen3_clk_get_rate64(clk);
426}
427
Marek Vasutf3b8bf72017-07-21 23:18:03 +0200428static ulong gen3_clk_set_rate(struct clk *clk, ulong rate)
429{
Marek Vasut414dbbe2018-01-11 16:28:31 +0100430 /* Force correct SD-IF divider configuration if applicable */
Marek Vasutc26bf892018-10-30 17:54:20 +0100431 gen3_clk_setup_sdif_div(clk, rate);
Marek Vasut7571ac42018-05-31 19:06:02 +0200432 return gen3_clk_get_rate64(clk);
Marek Vasutf3b8bf72017-07-21 23:18:03 +0200433}
434
435static int gen3_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
436{
437 if (args->args_count != 2) {
Sean Andersona1b654b2021-12-01 14:26:53 -0500438 debug("Invalid args_count: %d\n", args->args_count);
Marek Vasutf3b8bf72017-07-21 23:18:03 +0200439 return -EINVAL;
440 }
441
442 clk->id = (args->args[0] << 16) | args->args[1];
443
444 return 0;
445}
446
Marek Vasut4eb4e6e2018-01-08 14:01:40 +0100447const struct clk_ops gen3_clk_ops = {
Marek Vasutf3b8bf72017-07-21 23:18:03 +0200448 .enable = gen3_clk_enable,
449 .disable = gen3_clk_disable,
450 .get_rate = gen3_clk_get_rate,
451 .set_rate = gen3_clk_set_rate,
452 .of_xlate = gen3_clk_of_xlate,
453};
454
Marek Vasutf6b32022023-01-26 21:02:03 +0100455static int gen3_clk_probe(struct udevice *dev)
Marek Vasutf3b8bf72017-07-21 23:18:03 +0200456{
457 struct gen3_clk_priv *priv = dev_get_priv(dev);
Marek Vasut4eb4e6e2018-01-08 14:01:40 +0100458 struct cpg_mssr_info *info =
459 (struct cpg_mssr_info *)dev_get_driver_data(dev);
Marek Vasutba2c7d22023-02-28 22:34:38 +0100460 const void *pll_config;
Marek Vasutf3b8bf72017-07-21 23:18:03 +0200461 fdt_addr_t rst_base;
Marek Vasutf3b8bf72017-07-21 23:18:03 +0200462 int ret;
463
Masahiro Yamada1096ae12020-07-17 14:36:46 +0900464 priv->base = dev_read_addr_ptr(dev);
Marek Vasutf3b8bf72017-07-21 23:18:03 +0200465 if (!priv->base)
466 return -EINVAL;
467
Marek Vasut4eb4e6e2018-01-08 14:01:40 +0100468 priv->info = info;
469 ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, info->reset_node);
470 if (ret < 0)
471 return ret;
Marek Vasutf3b8bf72017-07-21 23:18:03 +0200472
473 rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg");
474 if (rst_base == FDT_ADDR_T_NONE)
475 return -EINVAL;
476
Marek Vasutea8505e2023-02-28 07:25:11 +0100477 priv->cpg_mode = readl(rst_base + info->reset_modemr_offset);
Marek Vasutf3b8bf72017-07-21 23:18:03 +0200478
Marek Vasutba2c7d22023-02-28 22:34:38 +0100479 pll_config = info->get_pll_config(priv->cpg_mode);
Marek Vasutf3b8bf72017-07-21 23:18:03 +0200480
Hai Pham94803462020-11-05 22:30:37 +0700481 if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {
482 priv->info->status_regs = mstpsr;
483 priv->info->control_regs = smstpcr;
484 priv->info->reset_regs = srcr;
485 priv->info->reset_clear_regs = srstclr;
Marek Vasutba2c7d22023-02-28 22:34:38 +0100486 priv->gen3_cpg_pll_config = pll_config;
487 if (!priv->gen3_cpg_pll_config->extal_div)
488 return -EINVAL;
489 } else if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN4) {
490 priv->info->status_regs = mstpsr_for_gen4;
491 priv->info->control_regs = mstpcr_for_gen4;
492 priv->info->reset_regs = srcr_for_gen4;
493 priv->info->reset_clear_regs = srstclr_for_gen4;
494 priv->gen4_cpg_pll_config = pll_config;
495 if (!priv->gen4_cpg_pll_config->extal_div)
496 return -EINVAL;
Hai Pham94803462020-11-05 22:30:37 +0700497 } else {
498 return -EINVAL;
499 }
500
Marek Vasutf3b8bf72017-07-21 23:18:03 +0200501 ret = clk_get_by_name(dev, "extal", &priv->clk_extal);
502 if (ret < 0)
503 return ret;
504
Marek Vasut4eb4e6e2018-01-08 14:01:40 +0100505 if (info->extalr_node) {
506 ret = clk_get_by_name(dev, info->extalr_node, &priv->clk_extalr);
Marek Vasutfb0aa292017-10-08 21:09:15 +0200507 if (ret < 0)
508 return ret;
509 }
Marek Vasutf3b8bf72017-07-21 23:18:03 +0200510
511 return 0;
512}
513
Marek Vasutf6b32022023-01-26 21:02:03 +0100514static int gen3_clk_remove(struct udevice *dev)
Marek Vasutdf6a1142017-11-25 22:08:55 +0100515{
516 struct gen3_clk_priv *priv = dev_get_priv(dev);
Marek Vasutdf6a1142017-11-25 22:08:55 +0100517
Marek Vasute11008b2018-01-15 16:44:39 +0100518 return renesas_clk_remove(priv->base, priv->info);
Marek Vasutdf6a1142017-11-25 22:08:55 +0100519}
Marek Vasutf6b32022023-01-26 21:02:03 +0100520
521U_BOOT_DRIVER(clk_gen3) = {
522 .name = "clk_gen3",
523 .id = UCLASS_CLK,
524 .priv_auto = sizeof(struct gen3_clk_priv),
525 .ops = &gen3_clk_ops,
526 .probe = gen3_clk_probe,
527 .remove = gen3_clk_remove,
Marek Vasut5ab7ef02020-04-25 14:57:55 +0200528 .flags = DM_FLAG_OS_PREPARE | DM_FLAG_VITAL,
Marek Vasutf6b32022023-01-26 21:02:03 +0100529};
530
531static int gen3_reset_assert(struct reset_ctl *reset_ctl)
532{
533 struct udevice *cdev = (struct udevice *)dev_get_driver_data(reset_ctl->dev);
534 struct gen3_clk_priv *priv = dev_get_priv(cdev);
Marek Vasutef5c0b12023-03-18 12:30:53 +0100535 unsigned int packed_id = MOD_CLK_PACK(reset_ctl->id);
536 unsigned int reg = packed_id / 32;
537 unsigned int bit = packed_id % 32;
Marek Vasutf6b32022023-01-26 21:02:03 +0100538 u32 bitmask = BIT(bit);
539
540 writel(bitmask, priv->base + priv->info->reset_regs[reg]);
541
542 return 0;
543}
544
545static int gen3_reset_deassert(struct reset_ctl *reset_ctl)
546{
547 struct udevice *cdev = (struct udevice *)dev_get_driver_data(reset_ctl->dev);
548 struct gen3_clk_priv *priv = dev_get_priv(cdev);
Marek Vasutef5c0b12023-03-18 12:30:53 +0100549 unsigned int packed_id = MOD_CLK_PACK(reset_ctl->id);
550 unsigned int reg = packed_id / 32;
551 unsigned int bit = packed_id % 32;
Marek Vasutf6b32022023-01-26 21:02:03 +0100552 u32 bitmask = BIT(bit);
553
554 writel(bitmask, priv->base + priv->info->reset_clear_regs[reg]);
555
556 return 0;
557}
558
559static const struct reset_ops rst_gen3_ops = {
560 .rst_assert = gen3_reset_assert,
561 .rst_deassert = gen3_reset_deassert,
562};
563
564U_BOOT_DRIVER(rst_gen3) = {
565 .name = "rst_gen3",
566 .id = UCLASS_RESET,
567 .ops = &rst_gen3_ops,
Marek Vasut5ab7ef02020-04-25 14:57:55 +0200568 .flags = DM_FLAG_OS_PREPARE | DM_FLAG_VITAL,
Marek Vasutf6b32022023-01-26 21:02:03 +0100569};
570
571int gen3_cpg_bind(struct udevice *parent)
572{
573 struct cpg_mssr_info *info =
574 (struct cpg_mssr_info *)dev_get_driver_data(parent);
575 struct udevice *cdev, *rdev;
576 struct driver *drv;
577 int ret;
578
579 drv = lists_driver_lookup_name("clk_gen3");
580 if (!drv)
581 return -ENOENT;
582
583 ret = device_bind_with_driver_data(parent, drv, "clk_gen3", (ulong)info,
584 dev_ofnode(parent), &cdev);
585 if (ret)
586 return ret;
587
588 drv = lists_driver_lookup_name("rst_gen3");
589 if (!drv)
590 return -ENOENT;
591
592 ret = device_bind_with_driver_data(parent, drv, "rst_gen3", (ulong)cdev,
593 dev_ofnode(parent), &rdev);
594 if (ret)
595 device_unbind(cdev);
596
597 return ret;
598}