clk: renesas: Synchronize R8A779A0 V3U clock tables with Linux 6.1.7
Synchronize R-Car R8A779A0 V3U clock tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
Rename CLK_TYPE_R8A779A0_ to CLK_TYPE_GEN4_ to match the new
clock tables. Add CLK_TYPE_GEN4_SD, CLK_TYPE_GEN4_RPC and
CLK_TYPE_GEN4_RPCD2 macros and handling into Gen3 CPG core.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c
index 84cf072..94715bb 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -253,23 +253,23 @@
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
CPG_PLL4CR, 0, 0, "PLL4");
- case CLK_TYPE_R8A779A0_MAIN:
+ case CLK_TYPE_GEN4_MAIN:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
0, 1, pll_config->extal_div,
"V3U_MAIN");
- case CLK_TYPE_R8A779A0_PLL1:
+ case CLK_TYPE_GEN4_PLL1:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
0, pll_config->pll1_mult,
pll_config->pll1_div,
"V3U_PLL1");
- case CLK_TYPE_R8A779A0_PLL2X_3X:
+ case CLK_TYPE_GEN4_PLL2X_3X:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
core->offset, 0, 0,
"V3U_PLL2X_3X");
- case CLK_TYPE_R8A779A0_PLL5:
+ case CLK_TYPE_GEN4_PLL5:
return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
0, pll_config->pll5_mult,
pll_config->pll5_div,
@@ -290,11 +290,13 @@
return rate;
case CLK_TYPE_GEN3_SDH: /* Fixed factor 1:1 */
+ fallthrough;
+ case CLK_TYPE_GEN4_SDH: /* Fixed factor 1:1 */
return gen3_clk_get_rate64(&parent);
case CLK_TYPE_GEN3_SD: /* FIXME */
fallthrough;
- case CLK_TYPE_R8A779A0_SD:
+ case CLK_TYPE_GEN4_SD:
value = readl(priv->base + core->offset);
value &= CPG_SD_STP_MASK | CPG_SD_FC_MASK;
@@ -315,6 +317,8 @@
case CLK_TYPE_GEN3_RPC:
case CLK_TYPE_GEN3_RPCD2:
+ case CLK_TYPE_GEN4_RPC:
+ case CLK_TYPE_GEN4_RPCD2:
rate = gen3_clk_get_rate64(&parent);
value = readl(priv->base + core->offset);