clk: renesas: Add dummy SDnH clock
Currently, SDnH is handled together with SDn. This caused lots of
problems, so we want SDnH as a separate clock. Introduce a dummy SDnH
type here which creates a fixed-factor clock with factor 1. That allows
us to convert the per-SoC CPG drivers while keeping the old behaviour
for now. A later patch then will add the proper functionality.
Based on Linux series by Wolfram Sang:
commit a31cf51bf6b4b ("clk: renesas: rcar-gen3: Add dummy SDnH clock"),
commit 1abd04480866c ("clk: renesas: rcar-gen3: Add SDnH clock"),
commit 63494b6f98f26 ("clk: renesas: r8a779a0: Add SDnH clock to V3U")
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Switch to gen3_clk_get_rate64
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c
index bcf5865..84cf072 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -289,6 +289,9 @@
div, rate);
return rate;
+ case CLK_TYPE_GEN3_SDH: /* Fixed factor 1:1 */
+ return gen3_clk_get_rate64(&parent);
+
case CLK_TYPE_GEN3_SD: /* FIXME */
fallthrough;
case CLK_TYPE_R8A779A0_SD: