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git01.mediatek.com / filogic / uboot / 21e27f00010c694761033e1a7afdcaf0199ecec6 / . / arch / arm / cpu / armv7 / Kconfig
blob: 4eb34b7b449aace3ccef80d1bc04c45571bfc919 [file] [log] [blame]
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530[diff] [blame]1if CPU_V7A
Hans de Goede85437352014-11-14 09:34:30 +0100[diff] [blame]2
3config CPU_V7_HAS_NONSEC
4 bool
5
6config CPU_V7_HAS_VIRT
7 bool
8
Masahiro Yamadad5415b22016-08-30 16:22:22 +0900[diff] [blame]9config ARCH_SUPPORT_PSCI
10 bool
11
Hans de Goede85437352014-11-14 09:34:30 +0100[diff] [blame]12config ARMV7_NONSEC
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900[diff] [blame]13 bool "Enable support for booting in non-secure mode" if EXPERT
Hans de Goede85437352014-11-14 09:34:30 +0100[diff] [blame]14 depends on CPU_V7_HAS_NONSEC
15 default y
16 ---help---
17 Say Y here to enable support for booting in non-secure / SVC mode.
18
Hans de Goede63fb5482014-11-14 09:34:31 +0100[diff] [blame]19config ARMV7_BOOT_SEC_DEFAULT
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900[diff] [blame]20 bool "Boot in secure mode by default" if EXPERT
Hans de Goede63fb5482014-11-14 09:34:31 +0100[diff] [blame]21 depends on ARMV7_NONSEC
Trevor Woerner513f6402020-05-06 08:02:41 -0400[diff] [blame]22 default y if ARCH_TEGRA
Hans de Goede63fb5482014-11-14 09:34:31 +0100[diff] [blame]23 ---help---
24 Say Y here to boot in secure mode by default even if non-secure mode
25 is supported. This option is useful to boot kernels which do not
26 suppport booting in non-secure mode. Only set this if you need it.
Robert P. J. Day8d56db92016-07-15 13:44:45 -0400[diff] [blame]27 This can be overridden at run-time by setting the bootm_boot_mode env.
Hans de Goede63fb5482014-11-14 09:34:31 +0100[diff] [blame]28 variable to "sec" or "nonsec".
29
Tom Rini9df9fb12022-03-11 09:11:56 -0500[diff] [blame]30config HAS_ARMV7_SECURE_BASE
31 bool "Enable support for a ahardware secure memory area"
32 default y if ARCH_LS1021A || ARCH_MX7 || ARCH_MX7ULP || ARCH_STM32MP \
33 || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || TEGRA124
34
35config ARMV7_SECURE_BASE
36 hex "Base address for secure mode memory"
37 depends on HAS_ARMV7_SECURE_BASE
38 default 0xfff00000 if TEGRA124
39 default 0x2ffc0000 if ARCH_STM32MP
40 default 0x2f000000 if ARCH_MX7ULP
41 default 0x10010000 if ARCH_LS1021A
42 default 0x00900000 if ARCH_MX7
43 default 0x00044000 if MACH_SUN8I
44 default 0x00020000 if MACH_SUN6I || MACH_SUN7I
45
46config ARMV7_SECURE_RESERVE_SIZE
47 hex
48 depends on TEGRA124 && HAS_ARMV7_SECURE_BASE
49 default 0x100000
50 help
51 Reserve top 1M for secure RAM
52
53config ARMV7_SECURE_MAX_SIZE
54 hex
55 depends on ARMV7_SECURE_BASE && ARCH_STM32MP || MACH_SUN6I \
56 || MACH_SUN7I || MACH_SUN8I
57 default 0xbc00 if MACH_SUN8I && !MACH_SUN8I_H3
58 default 0x3c00 if MACH_SUN8I && MACH_SUN8I_H3
59 default 0x10000
60
Andre Przywara99f46872023-10-01 23:52:12 +0100[diff] [blame]61config ARM_GIC_BASE_ADDRESS
62 hex
63 depends on ARMV7_NONSEC
Sam Edwards21e27f02023-10-11 19:47:56 -0600[diff] [blame^]64 depends on ARCH_EXYNOS5 || MACH_SUN8I_R528
Andre Przywara99f46872023-10-01 23:52:12 +0100[diff] [blame]65 default 0x10480000 if ARCH_EXYNOS5
Sam Edwards21e27f02023-10-11 19:47:56 -0600[diff] [blame^]66 default 0x03020000 if MACH_SUN8I_R528
Andre Przywara99f46872023-10-01 23:52:12 +0100[diff] [blame]67 help
68 Override the GIC base address if the Arm Cortex defined
69 CBAR/PERIPHBASE system register holds the wrong value.
70 Used by the PSCI code to configure the secure side of the GIC.
71
Hans de Goede85437352014-11-14 09:34:30 +0100[diff] [blame]72config ARMV7_VIRT
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900[diff] [blame]73 bool "Enable support for hardware virtualization" if EXPERT
Hans de Goede85437352014-11-14 09:34:30 +0100[diff] [blame]74 depends on CPU_V7_HAS_VIRT && ARMV7_NONSEC
75 default y
76 ---help---
77 Say Y here to boot in hypervisor (HYP) mode when booting non-secure.
78
Masahiro Yamadad5415b22016-08-30 16:22:22 +0900[diff] [blame]79config ARMV7_PSCI
80 bool "Enable PSCI support" if EXPERT
81 depends on ARMV7_NONSEC && ARCH_SUPPORT_PSCI
82 default y
83 help
84 Say Y here to enable PSCI support.
85
Patrick Delaunayf8a4df82020-06-17 18:19:18 +0200[diff] [blame]86choice
87 prompt "Supported PSCI version"
88 depends on ARMV7_PSCI
Icenowy Zheng70548102020-08-01 02:56:45 +0800[diff] [blame]89 default ARMV7_PSCI_0_1 if ARCH_SUNXI
Patrick Delaunayf8a4df82020-06-17 18:19:18 +0200[diff] [blame]90 default ARMV7_PSCI_1_0
91 help
92 Select the supported PSCI version.
93
94config ARMV7_PSCI_1_0
95 bool "PSCI V1.0"
96
97config ARMV7_PSCI_0_2
98 bool "PSCI V0.2"
Icenowy Zheng70548102020-08-01 02:56:45 +0800[diff] [blame]99
100config ARMV7_PSCI_0_1
101 bool "PSCI V0.1"
Patrick Delaunayf8a4df82020-06-17 18:19:18 +0200[diff] [blame]102endchoice
103
Masahiro Yamada6abecc32016-08-30 16:22:23 +0900[diff] [blame]104config ARMV7_PSCI_NR_CPUS
105 int "Maximum supported CPUs for PSCI"
106 depends on ARMV7_NONSEC
107 default 4
108 help
109 The maximum number of CPUs supported in the PSCI firmware.
110 It is no problem to set a larger value than the number of
111 CPUs in the actual hardware implementation.
112
Alexander Grafae6c2bc2016-03-16 15:41:21 +0100[diff] [blame]113config ARMV7_LPAE
Masahiro Yamada78cd22a2016-08-12 10:26:50 +0900[diff] [blame]114 bool "Use LPAE page table format" if EXPERT
Lokesh Vutla81b1a672018-04-26 18:21:26 +0530[diff] [blame]115 depends on CPU_V7A
Mark Kettenis0a7a0742018-06-15 23:47:14 +0200[diff] [blame]116 default y if ARMV7_VIRT
Alexander Grafae6c2bc2016-03-16 15:41:21 +0100[diff] [blame]117 ---help---
118 Say Y here to use the long descriptor page table format. This is
119 required if U-Boot runs in HYP mode.
120
Ralph Siemsen82890802023-05-12 21:36:49 -0400[diff] [blame]121config ARMV7_SET_CORTEX_SMPEN
122 bool
123 help
Michal Simek50fa1182023-05-17 09:17:16 +0200[diff] [blame]124 Enable the ARM Cortex ACTLR.SMP enable bit in U-Boot.
Ralph Siemsen82890802023-05-12 21:36:49 -0400[diff] [blame]125
Andre Przywara5fc25562022-01-23 00:27:19 +0000[diff] [blame]126config SPL_ARMV7_SET_CORTEX_SMPEN
127 bool
128 help
129 Enable the ARM Cortex ACTLR.SMP enable bit on SPL startup.
130
Hans de Goede85437352014-11-14 09:34:30 +0100[diff] [blame]131endif