Blame - arch/arm/cpu/armv7/Kconfig - filogic/uboot

blob: e33e53636a0187670cbf4987a539c71a7d3249c1 [file] [log] [blame]

Lokesh Vutla	81b1a67	2018-04-26 18:21:26 +0530	[diff] [blame]	1	if CPU_V7A
Hans de Goede	8543735	2014-11-14 09:34:30 +0100	[diff] [blame]	2
				3	config CPU_V7_HAS_NONSEC
				4	bool
				5
				6	config CPU_V7_HAS_VIRT
				7	bool
				8
Masahiro Yamada	d5415b2	2016-08-30 16:22:22 +0900	[diff] [blame]	9	config ARCH_SUPPORT_PSCI
				10	bool
				11
Hans de Goede	8543735	2014-11-14 09:34:30 +0100	[diff] [blame]	12	config ARMV7_NONSEC
Masahiro Yamada	78cd22a	2016-08-12 10:26:50 +0900	[diff] [blame]	13	bool "Enable support for booting in non-secure mode" if EXPERT
Hans de Goede	8543735	2014-11-14 09:34:30 +0100	[diff] [blame]	14	depends on CPU_V7_HAS_NONSEC
				15	default y
				16	---help---
				17	Say Y here to enable support for booting in non-secure / SVC mode.
				18
Hans de Goede	63fb548	2014-11-14 09:34:31 +0100	[diff] [blame]	19	config ARMV7_BOOT_SEC_DEFAULT
Masahiro Yamada	78cd22a	2016-08-12 10:26:50 +0900	[diff] [blame]	20	bool "Boot in secure mode by default" if EXPERT
Hans de Goede	63fb548	2014-11-14 09:34:31 +0100	[diff] [blame]	21	depends on ARMV7_NONSEC
Trevor Woerner	513f640	2020-05-06 08:02:41 -0400	[diff] [blame]	22	default y if ARCH_TEGRA
Hans de Goede	63fb548	2014-11-14 09:34:31 +0100	[diff] [blame]	23	---help---
				24	Say Y here to boot in secure mode by default even if non-secure mode
				25	is supported. This option is useful to boot kernels which do not
				26	suppport booting in non-secure mode. Only set this if you need it.
Robert P. J. Day	8d56db9	2016-07-15 13:44:45 -0400	[diff] [blame]	27	This can be overridden at run-time by setting the bootm_boot_mode env.
Hans de Goede	63fb548	2014-11-14 09:34:31 +0100	[diff] [blame]	28	variable to "sec" or "nonsec".
				29
Tom Rini	9df9fb1	2022-03-11 09:11:56 -0500	[diff] [blame]	30	config HAS_ARMV7_SECURE_BASE
				31	bool "Enable support for a ahardware secure memory area"
				32	default y if ARCH_LS1021A \|\| ARCH_MX7 \|\| ARCH_MX7ULP \|\| ARCH_STM32MP \
				33	\|\| MACH_SUN6I \|\| MACH_SUN7I \|\| MACH_SUN8I \|\| TEGRA124
				34
				35	config ARMV7_SECURE_BASE
				36	hex "Base address for secure mode memory"
				37	depends on HAS_ARMV7_SECURE_BASE
				38	default 0xfff00000 if TEGRA124
				39	default 0x2ffc0000 if ARCH_STM32MP
				40	default 0x2f000000 if ARCH_MX7ULP
				41	default 0x10010000 if ARCH_LS1021A
				42	default 0x00900000 if ARCH_MX7
				43	default 0x00044000 if MACH_SUN8I
				44	default 0x00020000 if MACH_SUN6I \|\| MACH_SUN7I
				45
				46	config ARMV7_SECURE_RESERVE_SIZE
				47	hex
				48	depends on TEGRA124 && HAS_ARMV7_SECURE_BASE
				49	default 0x100000
				50	help
				51	Reserve top 1M for secure RAM
				52
				53	config ARMV7_SECURE_MAX_SIZE
				54	hex
				55	depends on ARMV7_SECURE_BASE && ARCH_STM32MP \|\| MACH_SUN6I \
				56	\|\| MACH_SUN7I \|\| MACH_SUN8I
				57	default 0xbc00 if MACH_SUN8I && !MACH_SUN8I_H3
				58	default 0x3c00 if MACH_SUN8I && MACH_SUN8I_H3
				59	default 0x10000
				60
Hans de Goede	8543735	2014-11-14 09:34:30 +0100	[diff] [blame]	61	config ARMV7_VIRT
Masahiro Yamada	78cd22a	2016-08-12 10:26:50 +0900	[diff] [blame]	62	bool "Enable support for hardware virtualization" if EXPERT
Hans de Goede	8543735	2014-11-14 09:34:30 +0100	[diff] [blame]	63	depends on CPU_V7_HAS_VIRT && ARMV7_NONSEC
				64	default y
				65	---help---
				66	Say Y here to boot in hypervisor (HYP) mode when booting non-secure.
				67
Masahiro Yamada	d5415b2	2016-08-30 16:22:22 +0900	[diff] [blame]	68	config ARMV7_PSCI
				69	bool "Enable PSCI support" if EXPERT
				70	depends on ARMV7_NONSEC && ARCH_SUPPORT_PSCI
				71	default y
				72	help
				73	Say Y here to enable PSCI support.
				74
Patrick Delaunay	f8a4df8	2020-06-17 18:19:18 +0200	[diff] [blame]	75	choice
				76	prompt "Supported PSCI version"
				77	depends on ARMV7_PSCI
Icenowy Zheng	7054810	2020-08-01 02:56:45 +0800	[diff] [blame]	78	default ARMV7_PSCI_0_1 if ARCH_SUNXI
Patrick Delaunay	f8a4df8	2020-06-17 18:19:18 +0200	[diff] [blame]	79	default ARMV7_PSCI_1_0
				80	help
				81	Select the supported PSCI version.
				82
				83	config ARMV7_PSCI_1_0
				84	bool "PSCI V1.0"
				85
				86	config ARMV7_PSCI_0_2
				87	bool "PSCI V0.2"
Icenowy Zheng	7054810	2020-08-01 02:56:45 +0800	[diff] [blame]	88
				89	config ARMV7_PSCI_0_1
				90	bool "PSCI V0.1"
Patrick Delaunay	f8a4df8	2020-06-17 18:19:18 +0200	[diff] [blame]	91	endchoice
				92
Masahiro Yamada	6abecc3	2016-08-30 16:22:23 +0900	[diff] [blame]	93	config ARMV7_PSCI_NR_CPUS
				94	int "Maximum supported CPUs for PSCI"
				95	depends on ARMV7_NONSEC
				96	default 4
				97	help
				98	The maximum number of CPUs supported in the PSCI firmware.
				99	It is no problem to set a larger value than the number of
				100	CPUs in the actual hardware implementation.
				101
Alexander Graf	ae6c2bc	2016-03-16 15:41:21 +0100	[diff] [blame]	102	config ARMV7_LPAE
Masahiro Yamada	78cd22a	2016-08-12 10:26:50 +0900	[diff] [blame]	103	bool "Use LPAE page table format" if EXPERT
Lokesh Vutla	81b1a67	2018-04-26 18:21:26 +0530	[diff] [blame]	104	depends on CPU_V7A
Mark Kettenis	0a7a074	2018-06-15 23:47:14 +0200	[diff] [blame]	105	default y if ARMV7_VIRT
Alexander Graf	ae6c2bc	2016-03-16 15:41:21 +0100	[diff] [blame]	106	---help---
				107	Say Y here to use the long descriptor page table format. This is
				108	required if U-Boot runs in HYP mode.
				109
Ralph Siemsen	8289080	2023-05-12 21:36:49 -0400	[diff] [blame^]	110	config ARMV7_SET_CORTEX_SMPEN
				111	bool
				112	help
				113	Enable the ARM Cortex ACTLR.SMP enable bit in U-boot.
				114
Andre Przywara	5fc2556	2022-01-23 00:27:19 +0000	[diff] [blame]	115	config SPL_ARMV7_SET_CORTEX_SMPEN
				116	bool
				117	help
				118	Enable the ARM Cortex ACTLR.SMP enable bit on SPL startup.
				119
Hans de Goede	8543735	2014-11-14 09:34:30 +0100	[diff] [blame]	120	endif