blob: a4f6dd5a0f5ed5877f9f348eb8a0b8821ded2f23 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Kever Yang1cfd5502017-02-23 15:37:52 +08002/*
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
Kever Yang1cfd5502017-02-23 15:37:52 +08004 */
5
David Wua9422232017-09-20 14:35:44 +08006#include <bitfield.h>
Kever Yang1cfd5502017-02-23 15:37:52 +08007#include <clk-uclass.h>
8#include <dm.h>
9#include <errno.h>
Simon Glass0f2af882020-05-10 11:40:05 -060010#include <log.h>
Simon Glass9bc15642020-02-03 07:36:16 -070011#include <malloc.h>
Kever Yang1cfd5502017-02-23 15:37:52 +080012#include <syscon.h>
Kever Yang9fbe17c2019-03-28 11:01:23 +080013#include <asm/arch-rockchip/clock.h>
14#include <asm/arch-rockchip/cru_rk3328.h>
15#include <asm/arch-rockchip/hardware.h>
16#include <asm/arch-rockchip/grf_rk3328.h>
Simon Glass95588622020-12-22 19:30:28 -070017#include <dm/device-internal.h>
Kever Yang1cfd5502017-02-23 15:37:52 +080018#include <dm/lists.h>
19#include <dt-bindings/clock/rk3328-cru.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060020#include <linux/bitops.h>
Simon Glassdbd79542020-05-10 11:40:11 -060021#include <linux/delay.h>
Kever Yang1cfd5502017-02-23 15:37:52 +080022
Kever Yang1cfd5502017-02-23 15:37:52 +080023struct pll_div {
24 u32 refdiv;
25 u32 fbdiv;
26 u32 postdiv1;
27 u32 postdiv2;
28 u32 frac;
29};
30
31#define RATE_TO_DIV(input_rate, output_rate) \
32 ((input_rate) / (output_rate) - 1);
33#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
34
35#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
36 .refdiv = _refdiv,\
37 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
38 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
39
40static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 4, 1);
41static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 2, 1);
42
43static const struct pll_div apll_816_cfg = PLL_DIVISORS(816 * MHz, 1, 2, 1);
44static const struct pll_div apll_600_cfg = PLL_DIVISORS(600 * MHz, 1, 3, 1);
45
46static const struct pll_div *apll_cfgs[] = {
47 [APLL_816_MHZ] = &apll_816_cfg,
48 [APLL_600_MHZ] = &apll_600_cfg,
49};
50
51enum {
52 /* PLL_CON0 */
53 PLL_POSTDIV1_SHIFT = 12,
54 PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT,
55 PLL_FBDIV_SHIFT = 0,
56 PLL_FBDIV_MASK = 0xfff,
57
58 /* PLL_CON1 */
59 PLL_DSMPD_SHIFT = 12,
60 PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
61 PLL_INTEGER_MODE = 1,
62 PLL_LOCK_STATUS_SHIFT = 10,
63 PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
64 PLL_POSTDIV2_SHIFT = 6,
65 PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT,
66 PLL_REFDIV_SHIFT = 0,
67 PLL_REFDIV_MASK = 0x3f,
68
69 /* PLL_CON2 */
70 PLL_FRACDIV_SHIFT = 0,
71 PLL_FRACDIV_MASK = 0xffffff,
72
73 /* MODE_CON */
74 APLL_MODE_SHIFT = 0,
75 NPLL_MODE_SHIFT = 1,
76 DPLL_MODE_SHIFT = 4,
77 CPLL_MODE_SHIFT = 8,
78 GPLL_MODE_SHIFT = 12,
79 PLL_MODE_SLOW = 0,
80 PLL_MODE_NORM,
81
82 /* CLKSEL_CON0 */
83 CLK_CORE_PLL_SEL_APLL = 0,
84 CLK_CORE_PLL_SEL_GPLL,
85 CLK_CORE_PLL_SEL_DPLL,
86 CLK_CORE_PLL_SEL_NPLL,
87 CLK_CORE_PLL_SEL_SHIFT = 6,
88 CLK_CORE_PLL_SEL_MASK = 3 << CLK_CORE_PLL_SEL_SHIFT,
89 CLK_CORE_DIV_SHIFT = 0,
90 CLK_CORE_DIV_MASK = 0x1f,
91
92 /* CLKSEL_CON1 */
93 ACLKM_CORE_DIV_SHIFT = 4,
94 ACLKM_CORE_DIV_MASK = 0x7 << ACLKM_CORE_DIV_SHIFT,
95 PCLK_DBG_DIV_SHIFT = 0,
96 PCLK_DBG_DIV_MASK = 0xF << PCLK_DBG_DIV_SHIFT,
97
David Wuf01c5812018-01-13 14:02:36 +080098 /* CLKSEL_CON27 */
99 GMAC2IO_PLL_SEL_SHIFT = 7,
100 GMAC2IO_PLL_SEL_MASK = 1 << GMAC2IO_PLL_SEL_SHIFT,
101 GMAC2IO_PLL_SEL_CPLL = 0,
102 GMAC2IO_PLL_SEL_GPLL = 1,
103 GMAC2IO_CLK_DIV_MASK = 0x1f,
104 GMAC2IO_CLK_DIV_SHIFT = 0,
105
Kever Yang1cfd5502017-02-23 15:37:52 +0800106 /* CLKSEL_CON28 */
107 ACLK_PERIHP_PLL_SEL_CPLL = 0,
108 ACLK_PERIHP_PLL_SEL_GPLL,
109 ACLK_PERIHP_PLL_SEL_HDMIPHY,
110 ACLK_PERIHP_PLL_SEL_SHIFT = 6,
111 ACLK_PERIHP_PLL_SEL_MASK = 3 << ACLK_PERIHP_PLL_SEL_SHIFT,
112 ACLK_PERIHP_DIV_CON_SHIFT = 0,
113 ACLK_PERIHP_DIV_CON_MASK = 0x1f,
114
115 /* CLKSEL_CON29 */
116 PCLK_PERIHP_DIV_CON_SHIFT = 4,
117 PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT,
118 HCLK_PERIHP_DIV_CON_SHIFT = 0,
119 HCLK_PERIHP_DIV_CON_MASK = 3 << HCLK_PERIHP_DIV_CON_SHIFT,
120
121 /* CLKSEL_CON22 */
122 CLK_TSADC_DIV_CON_SHIFT = 0,
123 CLK_TSADC_DIV_CON_MASK = 0x3ff,
124
125 /* CLKSEL_CON23 */
126 CLK_SARADC_DIV_CON_SHIFT = 0,
David Wua9422232017-09-20 14:35:44 +0800127 CLK_SARADC_DIV_CON_MASK = GENMASK(9, 0),
128 CLK_SARADC_DIV_CON_WIDTH = 10,
Kever Yang1cfd5502017-02-23 15:37:52 +0800129
130 /* CLKSEL_CON24 */
131 CLK_PWM_PLL_SEL_CPLL = 0,
132 CLK_PWM_PLL_SEL_GPLL,
133 CLK_PWM_PLL_SEL_SHIFT = 15,
134 CLK_PWM_PLL_SEL_MASK = 1 << CLK_PWM_PLL_SEL_SHIFT,
135 CLK_PWM_DIV_CON_SHIFT = 8,
136 CLK_PWM_DIV_CON_MASK = 0x7f << CLK_PWM_DIV_CON_SHIFT,
137
138 CLK_SPI_PLL_SEL_CPLL = 0,
139 CLK_SPI_PLL_SEL_GPLL,
140 CLK_SPI_PLL_SEL_SHIFT = 7,
141 CLK_SPI_PLL_SEL_MASK = 1 << CLK_SPI_PLL_SEL_SHIFT,
142 CLK_SPI_DIV_CON_SHIFT = 0,
143 CLK_SPI_DIV_CON_MASK = 0x7f << CLK_SPI_DIV_CON_SHIFT,
144
145 /* CLKSEL_CON30 */
146 CLK_SDMMC_PLL_SEL_CPLL = 0,
147 CLK_SDMMC_PLL_SEL_GPLL,
148 CLK_SDMMC_PLL_SEL_24M,
149 CLK_SDMMC_PLL_SEL_USBPHY,
150 CLK_SDMMC_PLL_SHIFT = 8,
151 CLK_SDMMC_PLL_MASK = 0x3 << CLK_SDMMC_PLL_SHIFT,
152 CLK_SDMMC_DIV_CON_SHIFT = 0,
153 CLK_SDMMC_DIV_CON_MASK = 0xff << CLK_SDMMC_DIV_CON_SHIFT,
154
155 /* CLKSEL_CON32 */
156 CLK_EMMC_PLL_SEL_CPLL = 0,
157 CLK_EMMC_PLL_SEL_GPLL,
158 CLK_EMMC_PLL_SEL_24M,
159 CLK_EMMC_PLL_SEL_USBPHY,
160 CLK_EMMC_PLL_SHIFT = 8,
161 CLK_EMMC_PLL_MASK = 0x3 << CLK_EMMC_PLL_SHIFT,
162 CLK_EMMC_DIV_CON_SHIFT = 0,
163 CLK_EMMC_DIV_CON_MASK = 0xff << CLK_EMMC_DIV_CON_SHIFT,
164
165 /* CLKSEL_CON34 */
166 CLK_I2C_PLL_SEL_CPLL = 0,
167 CLK_I2C_PLL_SEL_GPLL,
168 CLK_I2C_DIV_CON_MASK = 0x7f,
169 CLK_I2C_PLL_SEL_MASK = 1,
170 CLK_I2C1_PLL_SEL_SHIFT = 15,
171 CLK_I2C1_DIV_CON_SHIFT = 8,
172 CLK_I2C0_PLL_SEL_SHIFT = 7,
173 CLK_I2C0_DIV_CON_SHIFT = 0,
174
175 /* CLKSEL_CON35 */
176 CLK_I2C3_PLL_SEL_SHIFT = 15,
177 CLK_I2C3_DIV_CON_SHIFT = 8,
178 CLK_I2C2_PLL_SEL_SHIFT = 7,
179 CLK_I2C2_DIV_CON_SHIFT = 0,
Jagan Teki350ab5d2024-01-17 13:21:47 +0530180
181 /* CLKSEL_CON40 */
182 CLK_HDMIPHY_DIV_CON_SHIFT = 3,
183 CLK_HDMIPHY_DIV_CON_MASK = 0x7 << CLK_HDMIPHY_DIV_CON_SHIFT,
Kever Yang1cfd5502017-02-23 15:37:52 +0800184};
185
186#define VCO_MAX_KHZ (3200 * (MHz / KHz))
187#define VCO_MIN_KHZ (800 * (MHz / KHz))
188#define OUTPUT_MAX_KHZ (3200 * (MHz / KHz))
189#define OUTPUT_MIN_KHZ (16 * (MHz / KHz))
190
191/*
192 * the div restructions of pll in integer mode, these are defined in
193 * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0
194 */
195#define PLL_DIV_MIN 16
196#define PLL_DIV_MAX 3200
197
198/*
199 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
200 * Formulas also embedded within the Fractional PLL Verilog model:
201 * If DSMPD = 1 (DSM is disabled, "integer mode")
202 * FOUTVCO = FREF / REFDIV * FBDIV
203 * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
204 * Where:
205 * FOUTVCO = Fractional PLL non-divided output frequency
206 * FOUTPOSTDIV = Fractional PLL divided output frequency
207 * (output of second post divider)
208 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
209 * REFDIV = Fractional PLL input reference clock divider
210 * FBDIV = Integer value programmed into feedback divide
211 *
212 */
213static void rkclk_set_pll(struct rk3328_cru *cru, enum rk_clk_id clk_id,
214 const struct pll_div *div)
215{
216 u32 *pll_con;
217 u32 mode_shift, mode_mask;
218
219 pll_con = NULL;
220 mode_shift = 0;
221 switch (clk_id) {
222 case CLK_ARM:
223 pll_con = cru->apll_con;
224 mode_shift = APLL_MODE_SHIFT;
225 break;
226 case CLK_DDR:
227 pll_con = cru->dpll_con;
228 mode_shift = DPLL_MODE_SHIFT;
229 break;
230 case CLK_CODEC:
231 pll_con = cru->cpll_con;
232 mode_shift = CPLL_MODE_SHIFT;
233 break;
234 case CLK_GENERAL:
235 pll_con = cru->gpll_con;
236 mode_shift = GPLL_MODE_SHIFT;
237 break;
238 case CLK_NEW:
239 pll_con = cru->npll_con;
240 mode_shift = NPLL_MODE_SHIFT;
241 break;
242 default:
243 break;
244 }
245 mode_mask = 1 << mode_shift;
246
247 /* All 8 PLLs have same VCO and output frequency range restrictions. */
248 u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv;
249 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
250
251 debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, \
252 postdiv2=%d, vco=%u khz, output=%u khz\n",
253 pll_con, div->fbdiv, div->refdiv, div->postdiv1,
254 div->postdiv2, vco_khz, output_khz);
255 assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
256 output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ &&
257 div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX);
258
259 /*
260 * When power on or changing PLL setting,
261 * we must force PLL into slow mode to ensure output stable clock.
262 */
263 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_SLOW << mode_shift);
264
265 /* use integer mode */
266 rk_clrsetreg(&pll_con[1], PLL_DSMPD_MASK,
267 PLL_INTEGER_MODE << PLL_DSMPD_SHIFT);
268
269 rk_clrsetreg(&pll_con[0],
270 PLL_FBDIV_MASK | PLL_POSTDIV1_MASK,
271 (div->fbdiv << PLL_FBDIV_SHIFT) |
272 (div->postdiv1 << PLL_POSTDIV1_SHIFT));
273 rk_clrsetreg(&pll_con[1],
274 PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
275 (div->postdiv2 << PLL_POSTDIV2_SHIFT) |
276 (div->refdiv << PLL_REFDIV_SHIFT));
277
278 /* waiting for pll lock */
279 while (!(readl(&pll_con[1]) & (1 << PLL_LOCK_STATUS_SHIFT)))
280 udelay(1);
281
282 /* pll enter normal mode */
283 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift);
284}
285
286static void rkclk_init(struct rk3328_cru *cru)
287{
288 u32 aclk_div;
289 u32 hclk_div;
290 u32 pclk_div;
291
Simon South93c44852019-10-10 15:28:36 -0400292 rk3328_configure_cpu(cru, APLL_600_MHZ);
293
Kever Yang1cfd5502017-02-23 15:37:52 +0800294 /* configure gpll cpll */
295 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
296 rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
297
298 /* configure perihp aclk, hclk, pclk */
299 aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
300 hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
301 pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
302
303 rk_clrsetreg(&cru->clksel_con[28],
304 ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK,
305 ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT |
306 aclk_div << ACLK_PERIHP_DIV_CON_SHIFT);
307 rk_clrsetreg(&cru->clksel_con[29],
308 PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK,
309 pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
310 hclk_div << HCLK_PERIHP_DIV_CON_SHIFT);
311}
312
313void rk3328_configure_cpu(struct rk3328_cru *cru,
314 enum apll_frequencies apll_freq)
315{
316 u32 clk_core_div;
317 u32 aclkm_div;
318 u32 pclk_dbg_div;
319
320 rkclk_set_pll(cru, CLK_ARM, apll_cfgs[apll_freq]);
321
322 clk_core_div = APLL_HZ / CLK_CORE_HZ - 1;
323 aclkm_div = APLL_HZ / ACLKM_CORE_HZ / (clk_core_div + 1) - 1;
324 pclk_dbg_div = APLL_HZ / PCLK_DBG_HZ / (clk_core_div + 1) - 1;
325
326 rk_clrsetreg(&cru->clksel_con[0],
327 CLK_CORE_PLL_SEL_MASK | CLK_CORE_DIV_MASK,
328 CLK_CORE_PLL_SEL_APLL << CLK_CORE_PLL_SEL_SHIFT |
329 clk_core_div << CLK_CORE_DIV_SHIFT);
330
331 rk_clrsetreg(&cru->clksel_con[1],
332 PCLK_DBG_DIV_MASK | ACLKM_CORE_DIV_MASK,
333 pclk_dbg_div << PCLK_DBG_DIV_SHIFT |
334 aclkm_div << ACLKM_CORE_DIV_SHIFT);
335}
336
337
338static ulong rk3328_i2c_get_clk(struct rk3328_cru *cru, ulong clk_id)
339{
340 u32 div, con;
341
342 switch (clk_id) {
343 case SCLK_I2C0:
344 con = readl(&cru->clksel_con[34]);
345 div = con >> CLK_I2C0_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
346 break;
347 case SCLK_I2C1:
348 con = readl(&cru->clksel_con[34]);
349 div = con >> CLK_I2C1_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
350 break;
351 case SCLK_I2C2:
352 con = readl(&cru->clksel_con[35]);
353 div = con >> CLK_I2C2_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
354 break;
355 case SCLK_I2C3:
356 con = readl(&cru->clksel_con[35]);
357 div = con >> CLK_I2C3_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
358 break;
359 default:
360 printf("do not support this i2c bus\n");
361 return -EINVAL;
362 }
363
364 return DIV_TO_RATE(GPLL_HZ, div);
365}
366
367static ulong rk3328_i2c_set_clk(struct rk3328_cru *cru, ulong clk_id, uint hz)
368{
369 int src_clk_div;
370
371 src_clk_div = GPLL_HZ / hz;
372 assert(src_clk_div - 1 < 127);
373
374 switch (clk_id) {
375 case SCLK_I2C0:
376 rk_clrsetreg(&cru->clksel_con[34],
377 CLK_I2C_DIV_CON_MASK << CLK_I2C0_DIV_CON_SHIFT |
378 CLK_I2C_PLL_SEL_MASK << CLK_I2C0_PLL_SEL_SHIFT,
379 (src_clk_div - 1) << CLK_I2C0_DIV_CON_SHIFT |
380 CLK_I2C_PLL_SEL_GPLL << CLK_I2C0_PLL_SEL_SHIFT);
381 break;
382 case SCLK_I2C1:
383 rk_clrsetreg(&cru->clksel_con[34],
384 CLK_I2C_DIV_CON_MASK << CLK_I2C1_DIV_CON_SHIFT |
385 CLK_I2C_PLL_SEL_MASK << CLK_I2C1_PLL_SEL_SHIFT,
386 (src_clk_div - 1) << CLK_I2C1_DIV_CON_SHIFT |
387 CLK_I2C_PLL_SEL_GPLL << CLK_I2C1_PLL_SEL_SHIFT);
388 break;
389 case SCLK_I2C2:
390 rk_clrsetreg(&cru->clksel_con[35],
391 CLK_I2C_DIV_CON_MASK << CLK_I2C2_DIV_CON_SHIFT |
392 CLK_I2C_PLL_SEL_MASK << CLK_I2C2_PLL_SEL_SHIFT,
393 (src_clk_div - 1) << CLK_I2C2_DIV_CON_SHIFT |
394 CLK_I2C_PLL_SEL_GPLL << CLK_I2C2_PLL_SEL_SHIFT);
395 break;
396 case SCLK_I2C3:
397 rk_clrsetreg(&cru->clksel_con[35],
398 CLK_I2C_DIV_CON_MASK << CLK_I2C3_DIV_CON_SHIFT |
399 CLK_I2C_PLL_SEL_MASK << CLK_I2C3_PLL_SEL_SHIFT,
400 (src_clk_div - 1) << CLK_I2C3_DIV_CON_SHIFT |
401 CLK_I2C_PLL_SEL_GPLL << CLK_I2C3_PLL_SEL_SHIFT);
402 break;
403 default:
404 printf("do not support this i2c bus\n");
405 return -EINVAL;
406 }
407
408 return DIV_TO_RATE(GPLL_HZ, src_clk_div);
409}
410
David Wuf01c5812018-01-13 14:02:36 +0800411static ulong rk3328_gmac2io_set_clk(struct rk3328_cru *cru, ulong rate)
412{
413 struct rk3328_grf_regs *grf;
414 ulong ret;
415
416 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
417
418 /*
419 * The RGMII CLK can be derived either from an external "clkin"
420 * or can be generated from internally by a divider from SCLK_MAC.
421 */
422 if (readl(&grf->mac_con[1]) & BIT(10) &&
423 readl(&grf->soc_con[4]) & BIT(14)) {
424 /* An external clock will always generate the right rate... */
425 ret = rate;
426 } else {
427 u32 con = readl(&cru->clksel_con[27]);
428 ulong pll_rate;
429 u8 div;
430
431 if ((con >> GMAC2IO_PLL_SEL_SHIFT) & GMAC2IO_PLL_SEL_GPLL)
432 pll_rate = GPLL_HZ;
433 else
434 pll_rate = CPLL_HZ;
435
436 div = DIV_ROUND_UP(pll_rate, rate) - 1;
437 if (div <= 0x1f)
438 rk_clrsetreg(&cru->clksel_con[27], GMAC2IO_CLK_DIV_MASK,
439 div << GMAC2IO_CLK_DIV_SHIFT);
440 else
441 debug("Unsupported div for gmac:%d\n", div);
442
443 return DIV_TO_RATE(pll_rate, div);
444 }
445
446 return ret;
447}
448
Kever Yang1cfd5502017-02-23 15:37:52 +0800449static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id)
450{
451 u32 div, con, con_id;
452
453 switch (clk_id) {
454 case HCLK_SDMMC:
Xu Ziyuan5a027632017-04-16 17:44:46 +0800455 case SCLK_SDMMC:
Kever Yang1cfd5502017-02-23 15:37:52 +0800456 con_id = 30;
457 break;
458 case HCLK_EMMC:
Xu Ziyuan5a027632017-04-16 17:44:46 +0800459 case SCLK_EMMC:
Kever Yang1cfd5502017-02-23 15:37:52 +0800460 con_id = 32;
461 break;
462 default:
463 return -EINVAL;
464 }
465 con = readl(&cru->clksel_con[con_id]);
466 div = (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
467
468 if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
469 == CLK_EMMC_PLL_SEL_24M)
Kever Yang99b546d2017-07-27 12:54:01 +0800470 return DIV_TO_RATE(OSC_HZ, div) / 2;
Kever Yang1cfd5502017-02-23 15:37:52 +0800471 else
Kever Yang99b546d2017-07-27 12:54:01 +0800472 return DIV_TO_RATE(GPLL_HZ, div) / 2;
Kever Yang1cfd5502017-02-23 15:37:52 +0800473}
474
475static ulong rk3328_mmc_set_clk(struct rk3328_cru *cru,
476 ulong clk_id, ulong set_rate)
477{
478 int src_clk_div;
479 u32 con_id;
480
481 switch (clk_id) {
482 case HCLK_SDMMC:
Xu Ziyuan5a027632017-04-16 17:44:46 +0800483 case SCLK_SDMMC:
Kever Yang1cfd5502017-02-23 15:37:52 +0800484 con_id = 30;
485 break;
486 case HCLK_EMMC:
Xu Ziyuan5a027632017-04-16 17:44:46 +0800487 case SCLK_EMMC:
Kever Yang1cfd5502017-02-23 15:37:52 +0800488 con_id = 32;
489 break;
490 default:
491 return -EINVAL;
492 }
493 /* Select clk_sdmmc/emmc source from GPLL by default */
Kever Yang99b546d2017-07-27 12:54:01 +0800494 /* mmc clock defaulg div 2 internal, need provide double in cru */
495 src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);
Kever Yang1cfd5502017-02-23 15:37:52 +0800496
497 if (src_clk_div > 127) {
498 /* use 24MHz source for 400KHz clock */
Kever Yang99b546d2017-07-27 12:54:01 +0800499 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
Kever Yang1cfd5502017-02-23 15:37:52 +0800500 rk_clrsetreg(&cru->clksel_con[con_id],
501 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
502 CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
503 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
504 } else {
505 rk_clrsetreg(&cru->clksel_con[con_id],
506 CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
507 CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
508 (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
509 }
510
511 return rk3328_mmc_get_clk(cru, clk_id);
512}
513
514static ulong rk3328_pwm_get_clk(struct rk3328_cru *cru)
515{
516 u32 div, con;
517
518 con = readl(&cru->clksel_con[24]);
519 div = (con & CLK_PWM_DIV_CON_MASK) >> CLK_PWM_DIV_CON_SHIFT;
520
521 return DIV_TO_RATE(GPLL_HZ, div);
522}
523
524static ulong rk3328_pwm_set_clk(struct rk3328_cru *cru, uint hz)
525{
526 u32 div = GPLL_HZ / hz;
527
528 rk_clrsetreg(&cru->clksel_con[24],
529 CLK_PWM_PLL_SEL_MASK | CLK_PWM_DIV_CON_MASK,
530 CLK_PWM_PLL_SEL_GPLL << CLK_PWM_PLL_SEL_SHIFT |
531 (div - 1) << CLK_PWM_DIV_CON_SHIFT);
532
533 return DIV_TO_RATE(GPLL_HZ, div);
534}
535
David Wua9422232017-09-20 14:35:44 +0800536static ulong rk3328_saradc_get_clk(struct rk3328_cru *cru)
537{
538 u32 div, val;
539
540 val = readl(&cru->clksel_con[23]);
541 div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
542 CLK_SARADC_DIV_CON_WIDTH);
543
544 return DIV_TO_RATE(OSC_HZ, div);
545}
546
547static ulong rk3328_saradc_set_clk(struct rk3328_cru *cru, uint hz)
548{
549 int src_clk_div;
550
551 src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
552 assert(src_clk_div < 128);
553
554 rk_clrsetreg(&cru->clksel_con[23],
555 CLK_SARADC_DIV_CON_MASK,
556 src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
557
558 return rk3328_saradc_get_clk(cru);
559}
560
Johannes Krottmayer0f0237d2020-07-08 23:57:38 +0200561static ulong rk3328_spi_get_clk(struct rk3328_cru *cru)
562{
563 u32 div, val;
564
565 val = readl(&cru->clksel_con[24]);
566 div = (val & CLK_SPI_DIV_CON_MASK) >> CLK_SPI_DIV_CON_SHIFT;
567
568 return DIV_TO_RATE(OSC_HZ, div);
569}
570
571static ulong rk3328_spi_set_clk(struct rk3328_cru *cru, uint hz)
572{
573 u32 src_clk_div;
574
575 src_clk_div = GPLL_HZ / hz;
576 assert(src_clk_div < 128);
577
578 rk_clrsetreg(&cru->clksel_con[24],
579 CLK_PWM_PLL_SEL_MASK | CLK_PWM_DIV_CON_MASK,
580 CLK_PWM_PLL_SEL_GPLL << CLK_PWM_PLL_SEL_SHIFT |
581 (src_clk_div - 1) << CLK_PWM_DIV_CON_SHIFT);
582
583 return rk3328_spi_get_clk(cru);
584}
585
Jagan Teki175ee822024-01-17 13:21:46 +0530586#ifndef CONFIG_SPL_BUILD
587static ulong rk3328_vop_get_clk(struct rk3328_clk_priv *priv, ulong clk_id)
588{
589 struct rk3328_cru *cru = priv->cru;
590 u32 div, con, parent;
591
592 switch (clk_id) {
593 case ACLK_VOP_PRE:
594 con = readl(&cru->clksel_con[39]);
595 div = (con & ACLK_VOP_DIV_CON_MASK) >> ACLK_VOP_DIV_CON_SHIFT;
596 parent = GPLL_HZ;
597 break;
598 case ACLK_VIO_PRE:
599 con = readl(&cru->clksel_con[37]);
600 div = (con & ACLK_VIO_DIV_CON_MASK) >> ACLK_VIO_DIV_CON_SHIFT;
601 parent = GPLL_HZ;
602 break;
603 case DCLK_LCDC:
604 con = readl(&cru->clksel_con[40]);
605 div = (con & DCLK_LCDC_DIV_CON_MASK) >> DCLK_LCDC_DIV_CON_SHIFT;
606 parent = GPLL_HZ;
607 break;
608 default:
609 printf("%s: Unsupported vop get clk#%ld\n", __func__, clk_id);
610 return -ENOENT;
611 }
612
613 return DIV_TO_RATE(parent, div);
614}
615
616static ulong rk3328_vop_set_clk(struct rk3328_clk_priv *priv,
617 ulong clk_id, uint hz)
618{
619 struct rk3328_cru *cru = priv->cru;
620 int src_clk_div;
621 u32 con, parent;
622
623 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz);
624 assert(src_clk_div - 1 < 31);
625
626 switch (clk_id) {
627 case ACLK_VOP_PRE:
628 rk_clrsetreg(&cru->clksel_con[39],
629 ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK,
630 ACLK_VOP_PLL_SEL_CPLL << ACLK_VOP_PLL_SEL_SHIFT |
631 (src_clk_div - 1) << ACLK_VOP_DIV_CON_SHIFT);
632 break;
633 case ACLK_VIO_PRE:
634 rk_clrsetreg(&cru->clksel_con[37],
635 ACLK_VIO_PLL_SEL_MASK | ACLK_VIO_DIV_CON_MASK,
636 ACLK_VIO_PLL_SEL_CPLL << ACLK_VIO_PLL_SEL_SHIFT |
637 (src_clk_div - 1) << ACLK_VIO_DIV_CON_SHIFT);
638 break;
639 case DCLK_LCDC:
640 con = readl(&cru->clksel_con[40]);
641 con = (con & DCLK_LCDC_SEL_MASK) >> DCLK_LCDC_SEL_SHIFT;
642 if (con) {
643 parent = readl(&cru->clksel_con[40]);
644 parent = (parent & DCLK_LCDC_PLL_SEL_MASK) >>
645 DCLK_LCDC_PLL_SEL_SHIFT;
646 if (parent)
647 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz);
648 else
649 src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz);
650
651 rk_clrsetreg(&cru->clksel_con[40],
652 DCLK_LCDC_DIV_CON_MASK,
653 (src_clk_div - 1) <<
654 DCLK_LCDC_DIV_CON_SHIFT);
655 }
656 break;
657 default:
658 printf("%s: Unable to set vop clk#%ld\n", __func__, clk_id);
659 return -EINVAL;
660 }
661
662 return rk3328_vop_get_clk(priv, clk_id);
663}
664#endif
665
Jagan Teki350ab5d2024-01-17 13:21:47 +0530666static ulong rk3328_hdmiphy_get_clk(struct rk3328_cru *cru)
667{
668 u32 div, con;
669
670 con = readl(&cru->clksel_con[40]);
671 div = (con & CLK_HDMIPHY_DIV_CON_MASK) >> CLK_HDMIPHY_DIV_CON_SHIFT;
672
673 return DIV_TO_RATE(GPLL_HZ, div);
674}
675
Kever Yang1cfd5502017-02-23 15:37:52 +0800676static ulong rk3328_clk_get_rate(struct clk *clk)
677{
678 struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
679 ulong rate = 0;
680
681 switch (clk->id) {
682 case 0 ... 29:
683 return 0;
684 case HCLK_SDMMC:
685 case HCLK_EMMC:
Xu Ziyuan5a027632017-04-16 17:44:46 +0800686 case SCLK_SDMMC:
687 case SCLK_EMMC:
Kever Yang1cfd5502017-02-23 15:37:52 +0800688 rate = rk3328_mmc_get_clk(priv->cru, clk->id);
689 break;
690 case SCLK_I2C0:
691 case SCLK_I2C1:
692 case SCLK_I2C2:
693 case SCLK_I2C3:
694 rate = rk3328_i2c_get_clk(priv->cru, clk->id);
695 break;
696 case SCLK_PWM:
697 rate = rk3328_pwm_get_clk(priv->cru);
698 break;
David Wua9422232017-09-20 14:35:44 +0800699 case SCLK_SARADC:
700 rate = rk3328_saradc_get_clk(priv->cru);
701 break;
Johannes Krottmayer0f0237d2020-07-08 23:57:38 +0200702 case SCLK_SPI:
703 rate = rk3328_spi_get_clk(priv->cru);
704 break;
Jagan Teki350ab5d2024-01-17 13:21:47 +0530705 case PCLK_HDMIPHY:
706 rate = rk3328_hdmiphy_get_clk(priv->cru);
707 break;
Jonas Karlmanbe201322024-05-01 19:23:50 +0000708 case SCLK_USB3OTG_REF:
709 rate = OSC_HZ;
710 break;
Kever Yang1cfd5502017-02-23 15:37:52 +0800711 default:
712 return -ENOENT;
713 }
714
715 return rate;
716}
717
718static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
719{
720 struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
721 ulong ret = 0;
722
723 switch (clk->id) {
724 case 0 ... 29:
725 return 0;
726 case HCLK_SDMMC:
727 case HCLK_EMMC:
Xu Ziyuan5a027632017-04-16 17:44:46 +0800728 case SCLK_SDMMC:
729 case SCLK_EMMC:
Kever Yang1cfd5502017-02-23 15:37:52 +0800730 ret = rk3328_mmc_set_clk(priv->cru, clk->id, rate);
731 break;
732 case SCLK_I2C0:
733 case SCLK_I2C1:
734 case SCLK_I2C2:
735 case SCLK_I2C3:
736 ret = rk3328_i2c_set_clk(priv->cru, clk->id, rate);
737 break;
David Wuf01c5812018-01-13 14:02:36 +0800738 case SCLK_MAC2IO:
739 ret = rk3328_gmac2io_set_clk(priv->cru, rate);
740 break;
Kever Yang1cfd5502017-02-23 15:37:52 +0800741 case SCLK_PWM:
742 ret = rk3328_pwm_set_clk(priv->cru, rate);
743 break;
David Wua9422232017-09-20 14:35:44 +0800744 case SCLK_SARADC:
745 ret = rk3328_saradc_set_clk(priv->cru, rate);
746 break;
Johannes Krottmayer0f0237d2020-07-08 23:57:38 +0200747 case SCLK_SPI:
748 ret = rk3328_spi_set_clk(priv->cru, rate);
749 break;
Jagan Teki175ee822024-01-17 13:21:46 +0530750#ifndef CONFIG_SPL_BUILD
David Wuf01c5812018-01-13 14:02:36 +0800751 case DCLK_LCDC:
Jagan Teki175ee822024-01-17 13:21:46 +0530752 case ACLK_VOP_PRE:
753 case ACLK_VIO_PRE:
754 rate = rk3328_vop_set_clk(priv, clk->id, rate);
755 break;
756#endif
David Wuf01c5812018-01-13 14:02:36 +0800757 case SCLK_PDM:
758 case SCLK_RTC32K:
759 case SCLK_UART0:
760 case SCLK_UART1:
761 case SCLK_UART2:
762 case SCLK_SDIO:
763 case SCLK_TSP:
764 case SCLK_WIFI:
765 case ACLK_BUS_PRE:
766 case HCLK_BUS_PRE:
767 case PCLK_BUS_PRE:
768 case ACLK_PERI_PRE:
769 case HCLK_PERI:
770 case PCLK_PERI:
David Wuf01c5812018-01-13 14:02:36 +0800771 case HCLK_VIO_PRE:
772 case ACLK_RGA_PRE:
773 case SCLK_RGA:
David Wuf01c5812018-01-13 14:02:36 +0800774 case ACLK_RKVDEC_PRE:
775 case ACLK_RKVENC:
776 case ACLK_VPU_PRE:
777 case SCLK_VDEC_CABAC:
778 case SCLK_VDEC_CORE:
779 case SCLK_VENC_CORE:
780 case SCLK_VENC_DSP:
781 case SCLK_EFUSE:
782 case PCLK_DDR:
783 case ACLK_GMAC:
784 case PCLK_GMAC:
Jonas Karlmanbe201322024-05-01 19:23:50 +0000785 case SCLK_USB3OTG_REF:
David Wuf01c5812018-01-13 14:02:36 +0800786 case SCLK_USB3OTG_SUSPEND:
Jagan Tekic46620f2023-06-06 22:39:17 +0530787 case USB480M:
David Wuf01c5812018-01-13 14:02:36 +0800788 return 0;
Kever Yang1cfd5502017-02-23 15:37:52 +0800789 default:
790 return -ENOENT;
791 }
792
793 return ret;
794}
795
David Wuf01c5812018-01-13 14:02:36 +0800796static int rk3328_gmac2io_set_parent(struct clk *clk, struct clk *parent)
797{
798 struct rk3328_grf_regs *grf;
799 const char *clock_output_name;
800 int ret;
801
802 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
803
804 /*
805 * If the requested parent is in the same clock-controller and the id
806 * is SCLK_MAC2IO_SRC ("clk_mac2io_src"), switch to the internal clock.
807 */
808 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC2IO_SRC)) {
809 debug("%s: switching RGMII to SCLK_MAC2IO_SRC\n", __func__);
810 rk_clrreg(&grf->mac_con[1], BIT(10));
811 return 0;
812 }
813
814 /*
815 * Otherwise, we need to check the clock-output-names of the
816 * requested parent to see if the requested id is "gmac_clkin".
817 */
818 ret = dev_read_string_index(parent->dev, "clock-output-names",
819 parent->id, &clock_output_name);
820 if (ret < 0)
821 return -ENODATA;
822
823 /* If this is "gmac_clkin", switch to the external clock input */
824 if (!strcmp(clock_output_name, "gmac_clkin")) {
825 debug("%s: switching RGMII to CLKIN\n", __func__);
826 rk_setreg(&grf->mac_con[1], BIT(10));
827 return 0;
828 }
829
830 return -EINVAL;
831}
832
833static int rk3328_gmac2io_ext_set_parent(struct clk *clk, struct clk *parent)
834{
835 struct rk3328_grf_regs *grf;
836 const char *clock_output_name;
837 int ret;
838
839 grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
840
841 /*
842 * If the requested parent is in the same clock-controller and the id
843 * is SCLK_MAC2IO ("clk_mac2io"), switch to the internal clock.
844 */
845 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC2IO)) {
846 debug("%s: switching RGMII to SCLK_MAC2IO\n", __func__);
847 rk_clrreg(&grf->soc_con[4], BIT(14));
848 return 0;
849 }
850
851 /*
852 * Otherwise, we need to check the clock-output-names of the
853 * requested parent to see if the requested id is "gmac_clkin".
854 */
855 ret = dev_read_string_index(parent->dev, "clock-output-names",
856 parent->id, &clock_output_name);
857 if (ret < 0)
858 return -ENODATA;
859
860 /* If this is "gmac_clkin", switch to the external clock input */
861 if (!strcmp(clock_output_name, "gmac_clkin")) {
862 debug("%s: switching RGMII to CLKIN\n", __func__);
863 rk_setreg(&grf->soc_con[4], BIT(14));
864 return 0;
865 }
866
867 return -EINVAL;
868}
869
870static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent)
871{
872 switch (clk->id) {
873 case SCLK_MAC2IO:
874 return rk3328_gmac2io_set_parent(clk, parent);
875 case SCLK_MAC2IO_EXT:
876 return rk3328_gmac2io_ext_set_parent(clk, parent);
877 case DCLK_LCDC:
Jagan Tekic46620f2023-06-06 22:39:17 +0530878 case USB480M:
David Wuf01c5812018-01-13 14:02:36 +0800879 case SCLK_PDM:
880 case SCLK_RTC32K:
881 case SCLK_UART0:
882 case SCLK_UART1:
883 case SCLK_UART2:
884 return 0;
885 }
886
887 debug("%s: unsupported clk %ld\n", __func__, clk->id);
888 return -ENOENT;
889}
890
Kever Yang1cfd5502017-02-23 15:37:52 +0800891static struct clk_ops rk3328_clk_ops = {
892 .get_rate = rk3328_clk_get_rate,
893 .set_rate = rk3328_clk_set_rate,
David Wuf01c5812018-01-13 14:02:36 +0800894 .set_parent = rk3328_clk_set_parent,
Kever Yang1cfd5502017-02-23 15:37:52 +0800895};
896
897static int rk3328_clk_probe(struct udevice *dev)
898{
899 struct rk3328_clk_priv *priv = dev_get_priv(dev);
900
901 rkclk_init(priv->cru);
902
903 return 0;
904}
905
Simon Glassaad29ae2020-12-03 16:55:21 -0700906static int rk3328_clk_of_to_plat(struct udevice *dev)
Kever Yang1cfd5502017-02-23 15:37:52 +0800907{
908 struct rk3328_clk_priv *priv = dev_get_priv(dev);
909
Kever Yangbb870a52018-02-11 11:53:09 +0800910 priv->cru = dev_read_addr_ptr(dev);
Kever Yang1cfd5502017-02-23 15:37:52 +0800911
912 return 0;
913}
914
915static int rk3328_clk_bind(struct udevice *dev)
916{
917 int ret;
Kever Yang4fbb6c22017-11-03 15:16:13 +0800918 struct udevice *sys_child;
919 struct sysreset_reg *priv;
Kever Yang1cfd5502017-02-23 15:37:52 +0800920
921 /* The reset driver does not have a device node, so bind it here */
Kever Yang4fbb6c22017-11-03 15:16:13 +0800922 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
923 &sys_child);
924 if (ret) {
925 debug("Warning: No sysreset driver: ret=%d\n", ret);
926 } else {
927 priv = malloc(sizeof(struct sysreset_reg));
928 priv->glb_srst_fst_value = offsetof(struct rk3328_cru,
929 glb_srst_fst_value);
930 priv->glb_srst_snd_value = offsetof(struct rk3328_cru,
931 glb_srst_snd_value);
Simon Glass95588622020-12-22 19:30:28 -0700932 dev_set_priv(sys_child, priv);
Kever Yang4fbb6c22017-11-03 15:16:13 +0800933 }
Kever Yang1cfd5502017-02-23 15:37:52 +0800934
Heiko Stuebner416f8d32019-11-09 00:06:30 +0100935#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
Elaine Zhang432976f2017-12-19 18:22:38 +0800936 ret = offsetof(struct rk3328_cru, softrst_con[0]);
937 ret = rockchip_reset_bind(dev, ret, 12);
938 if (ret)
Eugen Hristevf1798262023-04-11 10:17:56 +0300939 debug("Warning: software reset driver bind failed\n");
Elaine Zhang432976f2017-12-19 18:22:38 +0800940#endif
941
Kever Yang1cfd5502017-02-23 15:37:52 +0800942 return ret;
943}
944
945static const struct udevice_id rk3328_clk_ids[] = {
946 { .compatible = "rockchip,rk3328-cru" },
947 { }
948};
949
950U_BOOT_DRIVER(rockchip_rk3328_cru) = {
951 .name = "rockchip_rk3328_cru",
952 .id = UCLASS_CLK,
953 .of_match = rk3328_clk_ids,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700954 .priv_auto = sizeof(struct rk3328_clk_priv),
Simon Glassaad29ae2020-12-03 16:55:21 -0700955 .of_to_plat = rk3328_clk_of_to_plat,
Kever Yang1cfd5502017-02-23 15:37:52 +0800956 .ops = &rk3328_clk_ops,
957 .bind = rk3328_clk_bind,
958 .probe = rk3328_clk_probe,
959};