| commit | a9422235a4bacd1847613a279a1f2eecd21d0c68 | [log] [tgz] |
|---|---|---|
| author | David Wu <david.wu@rock-chips.com> | Wed Sep 20 14:35:44 2017 +0800 |
| committer | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | Sun Oct 01 00:33:30 2017 +0200 |
| tree | db6f8ccbfbd9a202615b86275432e782d3e16fb1 | |
| parent | 3c248b274c163b6ca65e816c02d22b0c7458fc2e [diff] |
rockchip: clk: Add rk3328 SARADC clock support The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). SARADC integer divider control register is 10-bits width. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>