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Rafal Jaworowskid3a02c32007-07-27 14:43:59 +02001/*
Detlev Zundel00c27162010-01-21 17:55:58 +01002 * (C) Copyright 2007-2010 DENX Software Engineering
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +02003 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +02004 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +02006 */
7
8/*
9 * CPU specific code for the MPC512x family.
10 *
11 * Derived from the MPC83xx code.
12 */
13
14#include <common.h>
15#include <command.h>
Heiko Schocher50219e62009-03-26 07:33:59 +010016#include <net.h>
Ben Warrenb664dea2008-08-31 10:36:38 -070017#include <netdev.h>
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +020018#include <asm/processor.h>
Detlev Zundel00c27162010-01-21 17:55:58 +010019#include <asm/io.h>
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +020020
Grzegorz Bernackiaf554d82008-01-08 17:16:15 +010021#if defined(CONFIG_OF_LIBFDT)
22#include <fdt_support.h>
23#endif
24
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +020025DECLARE_GLOBAL_DATA_PTR;
26
27int checkcpu (void)
28{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020029 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +020030 ulong clock = gd->cpu_clk;
31 u32 pvr = get_pvr ();
Detlev Zundel00c27162010-01-21 17:55:58 +010032 u32 spridr = in_be32(&immr->sysconf.spridr);
Wolfgang Denk20591042008-10-19 02:35:49 +020033 char buf1[32], buf2[32];
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +020034
Wolfgang Denke4a56a52007-08-12 21:34:34 +020035 puts ("CPU: ");
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +020036
37 switch (spridr & 0xffff0000) {
38 case SPR_5121E:
39 puts ("MPC5121e ");
40 break;
41 default:
42 printf ("Unknown part ID %08x ", spridr & 0xffff0000);
43 }
44 printf ("rev. %d.%d, Core ", SVR_MJREV (spridr), SVR_MNREV (spridr));
45
46 switch (pvr & 0xffff0000) {
47 case PVR_E300C4:
48 puts ("e300c4 ");
49 break;
50 default:
51 puts ("unknown ");
52 }
Detlev Zundela2ea2762010-01-22 14:47:59 +010053 printf ("at %s MHz, CSB at %s MHz (RSR=0x%04lx)\n",
Wolfgang Denk20591042008-10-19 02:35:49 +020054 strmhz(buf1, clock),
Simon Glass6c6cbd12012-12-13 20:48:54 +000055 strmhz(buf2, gd->arch.csb_clk),
Simon Glass4d6eaa32012-12-13 20:48:56 +000056 gd->arch.reset_status & 0xffff);
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +020057 return 0;
58}
59
60
61int
Wolfgang Denk6262d0212010-06-28 22:00:46 +020062do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +020063{
64 ulong msr;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020065 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +020066
67 /* Interrupts and MMU off */
68 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
69
70 msr &= ~( MSR_EE | MSR_IR | MSR_DR);
71 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
72
73 /*
74 * Enable Reset Control Reg - "RSTE" is the magic word that let us go
75 */
Detlev Zundel00c27162010-01-21 17:55:58 +010076 out_be32(&immap->reset.rpr, 0x52535445);
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +020077
78 /* Verify Reset Control Reg is enabled */
Detlev Zundel00c27162010-01-21 17:55:58 +010079 while (!(in_be32(&immap->reset.rcer) & RCER_CRE))
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +020080 ;
81
82 printf ("Resetting the board.\n");
83 udelay(200);
84
85 /* Perform reset */
Detlev Zundel00c27162010-01-21 17:55:58 +010086 out_be32(&immap->reset.rcr, RCR_SWHR);
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +020087
88 /* Unreached... */
89 return 1;
90}
91
92
93/*
94 * Get timebase clock frequency (like cpu_clk in Hz)
95 */
96unsigned long get_tbclk (void)
97{
Masahiro Yamada04cfea52016-09-06 22:17:38 +090098 return (gd->bus_clk + 3L) / 4L;
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +020099}
100
101
102#if defined(CONFIG_WATCHDOG)
103void watchdog_reset (void)
104{
105 int re_enable = disable_interrupts ();
106
107 /* Reset watchdog */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200108 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
Detlev Zundel00c27162010-01-21 17:55:58 +0100109 out_be32(&immr->wdt.swsrr, 0x556c);
110 out_be32(&immr->wdt.swsrr, 0xaa39);
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200111
112 if (re_enable)
113 enable_interrupts ();
114}
115#endif
Grzegorz Bernackiaf554d82008-01-08 17:16:15 +0100116
117#ifdef CONFIG_OF_LIBFDT
John Rigbyd096f622008-08-05 17:38:57 -0600118
119#ifdef CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
120/*
121 * fdt setup for old device trees
122 * fix up
123 * cpu clocks
124 * soc clocks
125 * ethernet addresses
126 */
127static void old_ft_cpu_setup(void *blob, bd_t *bd)
Grzegorz Bernackiaf554d82008-01-08 17:16:15 +0100128{
John Rigbyd096f622008-08-05 17:38:57 -0600129 /*
130 * avoid fixing up by path because that
131 * produces scary error messages
132 */
Mike Frysingerf4aa4362009-02-11 19:18:41 -0500133 uchar enetaddr[6];
John Rigbyd096f622008-08-05 17:38:57 -0600134
135 /*
136 * old device trees have ethernet nodes with
137 * device_type = "network"
138 */
Mike Frysingerf4aa4362009-02-11 19:18:41 -0500139 eth_getenv_enetaddr("ethaddr", enetaddr);
John Rigbyd096f622008-08-05 17:38:57 -0600140 do_fixup_by_prop(blob, "device_type", "network", 8,
Mike Frysingerf4aa4362009-02-11 19:18:41 -0500141 "local-mac-address", enetaddr, 6, 0);
John Rigbyd096f622008-08-05 17:38:57 -0600142 do_fixup_by_prop(blob, "device_type", "network", 8,
Mike Frysingerf4aa4362009-02-11 19:18:41 -0500143 "address", enetaddr, 6, 0);
John Rigbyd096f622008-08-05 17:38:57 -0600144 /*
145 * old device trees have soc nodes with
146 * device_type = "soc"
147 */
148 do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
149 "bus-frequency", bd->bi_ipsfreq, 0);
150}
151#endif
152
153static void ft_clock_setup(void *blob, bd_t *bd)
154{
Martha Marxfd449ab2008-05-29 14:23:25 -0400155 char *cpu_path = "/cpus/" OF_CPU;
Grzegorz Bernackiaf554d82008-01-08 17:16:15 +0100156
John Rigbyd096f622008-08-05 17:38:57 -0600157 /*
158 * fixup cpu clocks using path
159 */
160 do_fixup_by_path_u32(blob, cpu_path,
161 "timebase-frequency", OF_TBCLK, 1);
162 do_fixup_by_path_u32(blob, cpu_path,
163 "bus-frequency", bd->bi_busfreq, 1);
164 do_fixup_by_path_u32(blob, cpu_path,
165 "clock-frequency", bd->bi_intfreq, 1);
166 /*
167 * fixup soc clocks using compatible
168 */
169 do_fixup_by_compat_u32(blob, OF_SOC_COMPAT,
170 "bus-frequency", bd->bi_ipsfreq, 1);
171}
John Rigbyfc807c52008-01-30 13:36:57 -0700172
John Rigbyd096f622008-08-05 17:38:57 -0600173void ft_cpu_setup(void *blob, bd_t *bd)
174{
175#ifdef CONFIG_OF_SUPPORT_OLD_DEVICE_TREES
176 old_ft_cpu_setup(blob, bd);
177#endif
178 ft_clock_setup(blob, bd);
Heiko Schocher733b48d2009-12-03 11:20:06 +0100179 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
Grzegorz Bernackiaf554d82008-01-08 17:16:15 +0100180}
181#endif
Ben Warrenb664dea2008-08-31 10:36:38 -0700182
183#ifdef CONFIG_MPC512x_FEC
184/* Default initializations for FEC controllers. To override,
185 * create a board-specific function called:
186 * int board_eth_init(bd_t *bis)
187 */
188
189int cpu_eth_init(bd_t *bis)
190{
191 return mpc512x_fec_initialize(bis);
192}
193#endif