| Rafal Jaworowski | d3a02c3 | 2007-07-27 14:43:59 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. |
| 3 | * (C) Copyright 2007 DENX Software Engineering |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | /* |
| 25 | * CPU specific code for the MPC512x family. |
| 26 | * |
| 27 | * Derived from the MPC83xx code. |
| 28 | */ |
| 29 | |
| 30 | #include <common.h> |
| 31 | #include <command.h> |
| 32 | #include <mpc512x.h> |
| 33 | #include <asm/processor.h> |
| 34 | |
| 35 | DECLARE_GLOBAL_DATA_PTR; |
| 36 | |
| 37 | int checkcpu (void) |
| 38 | { |
| 39 | volatile immap_t *immr = (immap_t *) CFG_IMMR; |
| 40 | ulong clock = gd->cpu_clk; |
| 41 | u32 pvr = get_pvr (); |
| 42 | u32 spridr = immr->sysconf.spridr; |
| 43 | char buf[32]; |
| 44 | |
| 45 | puts("CPU: "); |
| 46 | |
| 47 | switch (spridr & 0xffff0000) { |
| 48 | case SPR_5121E: |
| 49 | puts ("MPC5121e "); |
| 50 | break; |
| 51 | default: |
| 52 | printf ("Unknown part ID %08x ", spridr & 0xffff0000); |
| 53 | } |
| 54 | printf ("rev. %d.%d, Core ", SVR_MJREV (spridr), SVR_MNREV (spridr)); |
| 55 | |
| 56 | switch (pvr & 0xffff0000) { |
| 57 | case PVR_E300C4: |
| 58 | puts ("e300c4 "); |
| 59 | break; |
| 60 | default: |
| 61 | puts ("unknown "); |
| 62 | } |
| 63 | printf ("at %s MHz, CSB at %3d MHz\n", strmhz(buf, clock), |
| 64 | gd->csb_clk / 1000000); |
| 65 | return 0; |
| 66 | } |
| 67 | |
| 68 | |
| 69 | int |
| 70 | do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) |
| 71 | { |
| 72 | ulong msr; |
| 73 | volatile immap_t *immap = (immap_t *) CFG_IMMR; |
| 74 | |
| 75 | /* Interrupts and MMU off */ |
| 76 | __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); |
| 77 | |
| 78 | msr &= ~( MSR_EE | MSR_IR | MSR_DR); |
| 79 | __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); |
| 80 | |
| 81 | /* |
| 82 | * Enable Reset Control Reg - "RSTE" is the magic word that let us go |
| 83 | */ |
| 84 | immap->reset.rpr = 0x52535445; |
| 85 | |
| 86 | /* Verify Reset Control Reg is enabled */ |
| 87 | while (!((immap->reset.rcer) & RCER_CRE)) |
| 88 | ; |
| 89 | |
| 90 | printf ("Resetting the board.\n"); |
| 91 | udelay(200); |
| 92 | |
| 93 | /* Perform reset */ |
| 94 | immap->reset.rcr = RCR_SWHR; |
| 95 | |
| 96 | /* Unreached... */ |
| 97 | return 1; |
| 98 | } |
| 99 | |
| 100 | |
| 101 | /* |
| 102 | * Get timebase clock frequency (like cpu_clk in Hz) |
| 103 | */ |
| 104 | unsigned long get_tbclk (void) |
| 105 | { |
| 106 | ulong tbclk; |
| 107 | |
| 108 | tbclk = (gd->bus_clk + 3L) / 4L; |
| 109 | |
| 110 | return tbclk; |
| 111 | } |
| 112 | |
| 113 | |
| 114 | #if defined(CONFIG_WATCHDOG) |
| 115 | void watchdog_reset (void) |
| 116 | { |
| 117 | int re_enable = disable_interrupts (); |
| 118 | |
| 119 | /* Reset watchdog */ |
| 120 | volatile immap_t *immr = (immap_t *) CFG_IMMR; |
| 121 | immr->wdt.swsrr = 0x556c; |
| 122 | immr->wdt.swsrr = 0xaa39; |
| 123 | |
| 124 | if (re_enable) |
| 125 | enable_interrupts (); |
| 126 | } |
| 127 | #endif |