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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk4a9cbbe2002-08-27 09:48:53 +00002/*
3 * (C) Copyright 2002
4 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
5 * Marius Groeger <mgroeger@sysgo.de>
6 *
7 * (C) Copyright 2002
8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
9 * Alex Zuepke <azu@sysgo.de>
wdenk4a9cbbe2002-08-27 09:48:53 +000010 */
11
12/*
13 * CPU specific code
14 */
15
16#include <common.h>
17#include <command.h>
Simon Glass1d91ba72019-11-14 12:57:37 -070018#include <cpu_func.h>
Jean-Christophe PLAGNIOL-VILLARD9053b5a2009-04-05 13:02:43 +020019#include <asm/system.h>
Albert ARIBAUD21505f92014-04-15 16:13:48 +020020#include <asm/io.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000021
Jean-Christophe PLAGNIOL-VILLARDe6b5f1b2009-04-05 13:06:31 +020022static void cache_flush(void);
23
wdenk4a9cbbe2002-08-27 09:48:53 +000024int cleanup_before_linux (void)
25{
26 /*
27 * this function is called just before we call linux
28 * it prepares the processor for linux
29 *
30 * just disable everything that can disturb booting linux
31 */
32
wdenk4a9cbbe2002-08-27 09:48:53 +000033 disable_interrupts ();
34
35 /* turn off I-cache */
Jean-Christophe PLAGNIOL-VILLARDe6b5f1b2009-04-05 13:06:31 +020036 icache_disable();
37 dcache_disable();
wdenk4a9cbbe2002-08-27 09:48:53 +000038
39 /* flush I-cache */
Jean-Christophe PLAGNIOL-VILLARDe6b5f1b2009-04-05 13:06:31 +020040 cache_flush();
wdenk4a9cbbe2002-08-27 09:48:53 +000041
42 return (0);
43}
44
Jean-Christophe PLAGNIOL-VILLARDe6b5f1b2009-04-05 13:06:31 +020045/* flush I/D-cache */
46static void cache_flush (void)
wdenk4a9cbbe2002-08-27 09:48:53 +000047{
Jean-Christophe PLAGNIOL-VILLARDe6b5f1b2009-04-05 13:06:31 +020048 unsigned long i = 0;
wdenk4a9cbbe2002-08-27 09:48:53 +000049
Jean-Christophe PLAGNIOL-VILLARDe6b5f1b2009-04-05 13:06:31 +020050 asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
wdenk4a9cbbe2002-08-27 09:48:53 +000051}
Albert ARIBAUD21505f92014-04-15 16:13:48 +020052
53#define RST_BASE 0x90030000
54#define RSRR 0x00
55#define RCSR 0x04
56
57__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused)))
58{
59 /* repeat endlessly */
60 while (1) {
61 writel(0, RST_BASE + RCSR);
62 writel(1, RST_BASE + RSRR);
63 }
64}