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git01.mediatek.com / filogic / uboot / 1d8bbff36546baffa5062a7090a465448e527adf / . / arch / arm / dts / k3-j7200-common-proc-board-u-boot.dtsi
blob: f25c7136c98de41a0971283f6226774f99223aff [file] [log] [blame]
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
Neha Malcom Francis30dcda22023-07-22 00:14:30 +0530[diff] [blame]6#include "k3-j7200-binman.dtsi"
7
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]8/ {
9 chosen {
10 stdout-path = "serial2:115200n8";
11 tick-timer = &timer1;
12 };
13
Vignesh Raghavendraf4ee7d52020-08-07 00:27:01 +0530[diff] [blame]14 aliases {
15 ethernet0 = &cpsw_port1;
Lokesh Vutla195eb682021-02-01 11:26:41 +0530[diff] [blame]16 i2c0 = &wkup_i2c0;
17 i2c1 = &mcu_i2c0;
18 i2c2 = &mcu_i2c1;
19 i2c3 = &main_i2c0;
Vignesh Raghavendraf4ee7d52020-08-07 00:27:01 +0530[diff] [blame]20 };
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]21};
22
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]23&cbass_main {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]24 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]25};
26
27&main_navss {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]28 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]29};
30
31&cbass_mcu_wakeup {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]32 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]33
34 timer1: timer@40400000 {
35 compatible = "ti,omap5430-timer";
36 reg = <0x0 0x40400000 0x0 0x80>;
37 ti,timer-alwon;
Tero Kristo94388c82021-06-11 11:45:27 +0300[diff] [blame]38 clock-frequency = <250000000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]39 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]40 };
Lokesh Vutla195eb682021-02-01 11:26:41 +0530[diff] [blame]41
42 chipid@43000014 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]43 bootph-pre-ram;
Lokesh Vutla195eb682021-02-01 11:26:41 +0530[diff] [blame]44 };
Vignesh Raghavendra7bd02882021-06-07 19:47:51 +0530[diff] [blame]45
Tom Rinif8276452021-09-10 17:37:43 -0400[diff] [blame]46 mcu_navss: bus@28380000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]47 bootph-pre-ram;
Vignesh Raghavendraa9b32692021-06-14 14:12:39 +0530[diff] [blame]48 #address-cells = <2>;
49 #size-cells = <2>;
Vignesh Raghavendra7bd02882021-06-07 19:47:51 +0530[diff] [blame]50
51 ringacc@2b800000 {
52 reg = <0x0 0x2b800000 0x0 0x400000>,
53 <0x0 0x2b000000 0x0 0x400000>,
54 <0x0 0x28590000 0x0 0x100>,
55 <0x0 0x2a500000 0x0 0x40000>,
56 <0x0 0x28440000 0x0 0x40000>;
57 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]58 bootph-pre-ram;
Vignesh Raghavendra7bd02882021-06-07 19:47:51 +0530[diff] [blame]59 };
60
61 dma-controller@285c0000 {
62 reg = <0x0 0x285c0000 0x0 0x100>,
63 <0x0 0x284c0000 0x0 0x4000>,
64 <0x0 0x2a800000 0x0 0x40000>,
65 <0x0 0x284a0000 0x0 0x4000>,
66 <0x0 0x2aa00000 0x0 0x40000>,
67 <0x0 0x28400000 0x0 0x2000>;
68 reg-names = "gcfg", "rchan", "rchanrt", "tchan",
69 "tchanrt", "rflow";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]70 bootph-pre-ram;
Vignesh Raghavendra7bd02882021-06-07 19:47:51 +0530[diff] [blame]71 };
72 };
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]73};
74
75&secure_proxy_main {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]76 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]77};
78
79&dmsc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]80 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]81 k3_sysreset: sysreset-controller {
82 compatible = "ti,sci-sysreset";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]83 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]84 };
85};
86
87&k3_pds {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]88 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]89};
90
91&k3_clks {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]92 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]93};
94
95&k3_reset {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]96 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]97};
98
99&wkup_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]100 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]101};
102
103&main_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]104 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]105};
106
107&main_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]108 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]109};
110
111&mcu_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]112 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]113};
114
115&main_sdhci0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]116 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]117};
118
119&main_sdhci1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]120 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]121};
122
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]123&wkup_i2c0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]124 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]125};
126
127&main_i2c0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]128 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]129};
130
131&main_i2c0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]132 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]133};
134
135&exp2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]136 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]137};
Vignesh Raghavendra9bbc49f2020-08-07 00:26:56 +0530[diff] [blame]138
Vignesh Raghavendraf4ee7d52020-08-07 00:27:01 +0530[diff] [blame]139&mcu_cpsw {
140 reg = <0x0 0x46000000 0x0 0x200000>,
141 <0x0 0x40f00200 0x0 0x8>;
142 reg-names = "cpsw_nuss", "mac_efuse";
Vignesh Raghavendra68a44a72021-02-09 13:38:48 +0530[diff] [blame]143 /delete-property/ ranges;
Vignesh Raghavendraf4ee7d52020-08-07 00:27:01 +0530[diff] [blame]144
145 cpsw-phy-sel@40f04040 {
146 compatible = "ti,am654-cpsw-phy-sel";
147 reg= <0x0 0x40f04040 0x0 0x4>;
148 reg-names = "gmii-sel";
149 };
150};
151
Vignesh Raghavendra9bbc49f2020-08-07 00:26:56 +0530[diff] [blame]152&main_usbss0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]153 bootph-pre-ram;
Vignesh Raghavendra9bbc49f2020-08-07 00:26:56 +0530[diff] [blame]154};
155
156&usbss0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]157 bootph-pre-ram;
Vignesh Raghavendra9bbc49f2020-08-07 00:26:56 +0530[diff] [blame]158 ti,usb2-only;
159};
160
161&usb0 {
162 dr_mode = "peripheral";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]163 bootph-pre-ram;
Vignesh Raghavendra9bbc49f2020-08-07 00:26:56 +0530[diff] [blame]164};
Vignesh Raghavendra962f95f2020-08-13 14:56:17 +0530[diff] [blame]165
Vignesh Raghavendra962f95f2020-08-13 14:56:17 +0530[diff] [blame]166&mcu_fss0_hpb0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]167 bootph-pre-ram;
Vignesh Raghavendra962f95f2020-08-13 14:56:17 +0530[diff] [blame]168};
169
170&fss {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]171 bootph-pre-ram;
Vignesh Raghavendra962f95f2020-08-13 14:56:17 +0530[diff] [blame]172};
173
174&hbmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]175 bootph-pre-ram;
Vignesh Raghavendra962f95f2020-08-13 14:56:17 +0530[diff] [blame]176
177 flash@0,0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]178 bootph-pre-ram;
Vignesh Raghavendra962f95f2020-08-13 14:56:17 +0530[diff] [blame]179 };
180};
181
182&hbmc_mux {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]183 bootph-pre-ram;
Vignesh Raghavendra962f95f2020-08-13 14:56:17 +0530[diff] [blame]184};
Aswath Govindraju154e8372021-07-21 21:28:43 +0530[diff] [blame]185
186&serdes_ln_ctrl {
187 u-boot,mux-autoprobe;
188};
189
190&usb_serdes_mux {
191 u-boot,mux-autoprobe;
192};
193
194&serdes0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]195 bootph-pre-ram;
Aswath Govindraju154e8372021-07-21 21:28:43 +0530[diff] [blame]196};
Suman Anna3e97b1c2022-02-13 12:48:48 -0600[diff] [blame]197
198&main_r5fss0 {
199 ti,cluster-mode = <0>;
200};