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git01.mediatek.com / filogic / uboot / d3a98cb671f08af821b3b046564783d649736c18 / . / arch / arm / dts / k3-j7200-common-proc-board-u-boot.dtsi
blob: f57c2306ba1ac9c01c1a1bad656ac9a61f26ff29 [file] [log] [blame]
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/ {
7 chosen {
8 stdout-path = "serial2:115200n8";
9 tick-timer = &timer1;
10 };
11
Vignesh Raghavendraf4ee7d52020-08-07 00:27:01 +0530[diff] [blame]12 aliases {
13 ethernet0 = &cpsw_port1;
Lokesh Vutla195eb682021-02-01 11:26:41 +0530[diff] [blame]14 i2c0 = &wkup_i2c0;
15 i2c1 = &mcu_i2c0;
16 i2c2 = &mcu_i2c1;
17 i2c3 = &main_i2c0;
Vignesh Raghavendraf4ee7d52020-08-07 00:27:01 +0530[diff] [blame]18 };
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]19};
20
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]21&cbass_main {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]22 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]23};
24
25&main_navss {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]26 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]27};
28
29&cbass_mcu_wakeup {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]30 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]31
32 timer1: timer@40400000 {
33 compatible = "ti,omap5430-timer";
34 reg = <0x0 0x40400000 0x0 0x80>;
35 ti,timer-alwon;
Tero Kristo94388c82021-06-11 11:45:27 +0300[diff] [blame]36 clock-frequency = <250000000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]37 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]38 };
Lokesh Vutla195eb682021-02-01 11:26:41 +0530[diff] [blame]39
40 chipid@43000014 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]41 bootph-pre-ram;
Lokesh Vutla195eb682021-02-01 11:26:41 +0530[diff] [blame]42 };
Vignesh Raghavendra7bd02882021-06-07 19:47:51 +0530[diff] [blame]43
Tom Rinif8276452021-09-10 17:37:43 -0400[diff] [blame]44 mcu_navss: bus@28380000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]45 bootph-pre-ram;
Vignesh Raghavendraa9b32692021-06-14 14:12:39 +0530[diff] [blame]46 #address-cells = <2>;
47 #size-cells = <2>;
Vignesh Raghavendra7bd02882021-06-07 19:47:51 +0530[diff] [blame]48
49 ringacc@2b800000 {
50 reg = <0x0 0x2b800000 0x0 0x400000>,
51 <0x0 0x2b000000 0x0 0x400000>,
52 <0x0 0x28590000 0x0 0x100>,
53 <0x0 0x2a500000 0x0 0x40000>,
54 <0x0 0x28440000 0x0 0x40000>;
55 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]56 bootph-pre-ram;
Vignesh Raghavendra7bd02882021-06-07 19:47:51 +0530[diff] [blame]57 };
58
59 dma-controller@285c0000 {
60 reg = <0x0 0x285c0000 0x0 0x100>,
61 <0x0 0x284c0000 0x0 0x4000>,
62 <0x0 0x2a800000 0x0 0x40000>,
63 <0x0 0x284a0000 0x0 0x4000>,
64 <0x0 0x2aa00000 0x0 0x40000>,
65 <0x0 0x28400000 0x0 0x2000>;
66 reg-names = "gcfg", "rchan", "rchanrt", "tchan",
67 "tchanrt", "rflow";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]68 bootph-pre-ram;
Vignesh Raghavendra7bd02882021-06-07 19:47:51 +0530[diff] [blame]69 };
70 };
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]71};
72
73&secure_proxy_main {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]74 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]75};
76
77&dmsc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]78 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]79 k3_sysreset: sysreset-controller {
80 compatible = "ti,sci-sysreset";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]81 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]82 };
83};
84
85&k3_pds {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]86 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]87};
88
89&k3_clks {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]90 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]91};
92
93&k3_reset {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]94 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]95};
96
97&wkup_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]98 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]99};
100
101&main_pmx0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]102 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]103};
104
105&main_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]106 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]107};
108
109&mcu_uart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]110 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]111};
112
113&main_sdhci0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]114 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]115};
116
117&main_sdhci1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]118 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]119};
120
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]121&wkup_i2c0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]122 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]123};
124
125&main_i2c0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]126 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]127};
128
129&main_i2c0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]130 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]131};
132
133&exp2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]134 bootph-pre-ram;
Lokesh Vutlac8339702020-08-05 22:44:28 +0530[diff] [blame]135};
Vignesh Raghavendra9bbc49f2020-08-07 00:26:56 +0530[diff] [blame]136
Vignesh Raghavendraf4ee7d52020-08-07 00:27:01 +0530[diff] [blame]137&mcu_cpsw {
138 reg = <0x0 0x46000000 0x0 0x200000>,
139 <0x0 0x40f00200 0x0 0x8>;
140 reg-names = "cpsw_nuss", "mac_efuse";
Vignesh Raghavendra68a44a72021-02-09 13:38:48 +0530[diff] [blame]141 /delete-property/ ranges;
Vignesh Raghavendraf4ee7d52020-08-07 00:27:01 +0530[diff] [blame]142
143 cpsw-phy-sel@40f04040 {
144 compatible = "ti,am654-cpsw-phy-sel";
145 reg= <0x0 0x40f04040 0x0 0x4>;
146 reg-names = "gmii-sel";
147 };
148};
149
Vignesh Raghavendra9bbc49f2020-08-07 00:26:56 +0530[diff] [blame]150&main_usbss0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]151 bootph-pre-ram;
Vignesh Raghavendra9bbc49f2020-08-07 00:26:56 +0530[diff] [blame]152};
153
154&usbss0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]155 bootph-pre-ram;
Vignesh Raghavendra9bbc49f2020-08-07 00:26:56 +0530[diff] [blame]156 ti,usb2-only;
157};
158
159&usb0 {
160 dr_mode = "peripheral";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]161 bootph-pre-ram;
Vignesh Raghavendra9bbc49f2020-08-07 00:26:56 +0530[diff] [blame]162};
Vignesh Raghavendra962f95f2020-08-13 14:56:17 +0530[diff] [blame]163
Vignesh Raghavendra962f95f2020-08-13 14:56:17 +0530[diff] [blame]164&mcu_fss0_hpb0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]165 bootph-pre-ram;
Vignesh Raghavendra962f95f2020-08-13 14:56:17 +0530[diff] [blame]166};
167
168&fss {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]169 bootph-pre-ram;
Vignesh Raghavendra962f95f2020-08-13 14:56:17 +0530[diff] [blame]170};
171
172&hbmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]173 bootph-pre-ram;
Vignesh Raghavendra962f95f2020-08-13 14:56:17 +0530[diff] [blame]174
175 flash@0,0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]176 bootph-pre-ram;
Vignesh Raghavendra962f95f2020-08-13 14:56:17 +0530[diff] [blame]177 };
178};
179
180&hbmc_mux {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]181 bootph-pre-ram;
Vignesh Raghavendra962f95f2020-08-13 14:56:17 +0530[diff] [blame]182};
Aswath Govindraju154e8372021-07-21 21:28:43 +0530[diff] [blame]183
184&serdes_ln_ctrl {
185 u-boot,mux-autoprobe;
186};
187
188&usb_serdes_mux {
189 u-boot,mux-autoprobe;
190};
191
192&serdes0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame^]193 bootph-pre-ram;
Aswath Govindraju154e8372021-07-21 21:28:43 +0530[diff] [blame]194};
Suman Anna3e97b1c2022-02-13 12:48:48 -0600[diff] [blame]195
196&main_r5fss0 {
197 ti,cluster-mode = <0>;
198};