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git01.mediatek.com / filogic / uboot / 1d52512b2e81dbfae2cf11f6ef886bc22a7cd4d8 / . / arch / arm / mach-omap2 / am33xx / emif4.c
blob: f19c66822d209bad38c6c8b829f2f621ec9ff2b5 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]2/*
3 * emif4.c
4 *
5 * AM33XX emif4 configuration file
6 *
Nishanth Menoneaa39c62023-11-01 15:56:03 -0500[diff] [blame]7 * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]8 */
9
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]10#include <asm/arch/cpu.h>
11#include <asm/arch/ddr_defs.h>
12#include <asm/arch/hardware.h>
13#include <asm/arch/clock.h>
Tom Rini034aba72012-07-03 09:20:06 -0700[diff] [blame]14#include <asm/arch/sys_proto.h>
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]15#include <asm/io.h>
Tom Rini3fd44562012-07-03 08:51:34 -0700[diff] [blame]16#include <asm/emif.h>
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]17
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]18static struct vtp_reg *vtpreg[2] = {
19 (struct vtp_reg *)VTP0_CTRL_ADDR,
20 (struct vtp_reg *)VTP1_CTRL_ADDR};
21#ifdef CONFIG_AM33XX
Tom Rini4d451122012-07-30 14:13:16 -0700[diff] [blame]22static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]23#endif
Lokesh Vutlaa82d4e12013-12-10 15:02:22 +0530[diff] [blame]24#ifdef CONFIG_AM43XX
25static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
26static struct cm_device_inst *cm_device =
27 (struct cm_device_inst *)CM_DEVICE_INST;
28#endif
Tom Rini4d451122012-07-30 14:13:16 -0700[diff] [blame]29
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]30static void config_vtp(int nr)
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]31{
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]32 writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
33 &vtpreg[nr]->vtp0ctrlreg);
34 writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
35 &vtpreg[nr]->vtp0ctrlreg);
36 writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN,
37 &vtpreg[nr]->vtp0ctrlreg);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]38
39 /* Poll for READY */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]40 while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) !=
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]41 VTP_CTRL_READY)
42 ;
43}
44
Lokesh Vutla89a83bf2013-07-30 10:48:52 +0530[diff] [blame]45void __weak ddr_pll_config(unsigned int ddrpll_m)
46{
47}
48
Lokesh Vutla303b2672013-12-10 15:02:21 +0530[diff] [blame]49void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000[diff] [blame]50 const struct ddr_data *data, const struct cmd_control *ctrl,
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]51 const struct emif_regs *regs, int nr)
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]52{
Peter Korsgaardeb6cf7b2012-10-18 01:21:12 +0000[diff] [blame]53 ddr_pll_config(pll);
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]54 config_vtp(nr);
55 config_cmd_ctrl(ctrl, nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]56
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]57 config_ddr_data(data, nr);
58#ifdef CONFIG_AM33XX
Lokesh Vutla303b2672013-12-10 15:02:21 +0530[diff] [blame]59 config_io_ctrl(ioregs);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]60
Tom Rini4b020fe2012-07-30 14:13:56 -0700[diff] [blame]61 /* Set CKE to be controlled by EMIF/DDR PHY */
62 writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
James Doublesin53c723b2014-12-22 16:26:11 -0600[diff] [blame]63
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]64#endif
Lokesh Vutlaa82d4e12013-12-10 15:02:22 +0530[diff] [blame]65#ifdef CONFIG_AM43XX
66 writel(readl(&cm_device->cm_dll_ctrl) & ~0x1, &cm_device->cm_dll_ctrl);
Jeroen Hofstee47c02952014-06-18 21:22:35 +0200[diff] [blame]67 while ((readl(&cm_device->cm_dll_ctrl) & CM_DLL_READYST) == 0)
Lokesh Vutlaa82d4e12013-12-10 15:02:22 +0530[diff] [blame]68 ;
Lokesh Vutlaa82d4e12013-12-10 15:02:22 +0530[diff] [blame]69
70 config_io_ctrl(ioregs);
71
72 /* Set CKE to be controlled by EMIF/DDR PHY */
73 writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
James Doublesin53c723b2014-12-22 16:26:11 -0600[diff] [blame]74
Tom Rinibe8d6352015-06-05 15:51:11 +0530[diff] [blame]75 if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
Dave Gerlach382867f2018-03-17 13:24:30 +0530[diff] [blame]76#ifndef CONFIG_SPL_RTC_DDR_SUPPORT
Tom Rinibe8d6352015-06-05 15:51:11 +0530[diff] [blame]77 /* Allow EMIF to control DDR_RESET */
78 writel(0x00000000, &ddrctrl->ddrioctrl);
Dave Gerlach382867f2018-03-17 13:24:30 +0530[diff] [blame]79#else
80 /* Override EMIF DDR_RESET control */
81 writel(0x80000000, &ddrctrl->ddrioctrl);
82#endif /* CONFIG_SPL_RTC_DDR_SUPPORT */
Lokesh Vutlaa82d4e12013-12-10 15:02:22 +0530[diff] [blame]83#endif
84
Tom Rini4b020fe2012-07-30 14:13:56 -0700[diff] [blame]85 /* Program EMIF instance */
Matt Porter65991ec2013-03-15 10:07:03 +0000[diff] [blame]86 config_ddr_phy(regs, nr);
87 set_sdram_timings(regs, nr);
Lokesh Vutlaa82d4e12013-12-10 15:02:22 +0530[diff] [blame]88 if (get_emif_rev(EMIF1_BASE) == EMIF_4D5)
89 config_sdram_emif4d5(regs, nr);
90 else
91 config_sdram(regs, nr);
Chandan Nath98b036e2011-10-14 02:58:24 +0000[diff] [blame]92}