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git01.mediatek.com / filogic / uboot / 1d0b09b33ea6829203f51cdb23770cc39ccd3cf0 / . / board / dhelectronics / dh_imx6 / dh_imx6_spl.c
blob: bb98f39f0250eb33ddcad2ce20180c3232526001 [file] [log] [blame]
Marek Vasut00671d92017-10-09 21:51:10 +0200[diff] [blame]1/*
2 * DHCOM DH-iMX6 PDK SPL support
3 *
4 * Copyright (C) 2017 Marek Vasut <marex@denx.de>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#include <common.h>
10#include <asm/arch/clock.h>
11#include <asm/arch/crm_regs.h>
12#include <asm/arch/imx-regs.h>
13#include <asm/arch/iomux.h>
14#include <asm/arch/mx6-ddr.h>
15#include <asm/arch/mx6-pins.h>
16#include <asm/arch/sys_proto.h>
17#include <asm/gpio.h>
18#include <asm/mach-imx/boot_mode.h>
19#include <asm/mach-imx/iomux-v3.h>
20#include <asm/mach-imx/mxc_i2c.h>
21#include <asm/io.h>
22#include <errno.h>
23#include <fuse.h>
24#include <fsl_esdhc.h>
25#include <i2c.h>
26#include <mmc.h>
27#include <spl.h>
28
29#define ENET_PAD_CTRL \
30 (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
31 PAD_CTL_HYS)
32
33#define GPIO_PAD_CTRL \
34 (PAD_CTL_HYS | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
35
36#define SPI_PAD_CTRL \
37 (PAD_CTL_HYS | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
38 PAD_CTL_SRE_FAST)
39
40#define UART_PAD_CTRL \
41 (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
42 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
43
44#define USDHC_PAD_CTRL \
45 (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
46 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
47
48DECLARE_GLOBAL_DATA_PTR;
49
50static const struct mx6dq_iomux_ddr_regs dhcom6dq_ddr_ioregs = {
51 .dram_sdclk_0 = 0x00020030,
52 .dram_sdclk_1 = 0x00020030,
53 .dram_cas = 0x00020030,
54 .dram_ras = 0x00020030,
55 .dram_reset = 0x00020030,
56 .dram_sdcke0 = 0x00003000,
57 .dram_sdcke1 = 0x00003000,
58 .dram_sdba2 = 0x00000000,
59 .dram_sdodt0 = 0x00003030,
60 .dram_sdodt1 = 0x00003030,
61 .dram_sdqs0 = 0x00000030,
62 .dram_sdqs1 = 0x00000030,
63 .dram_sdqs2 = 0x00000030,
64 .dram_sdqs3 = 0x00000030,
65 .dram_sdqs4 = 0x00000030,
66 .dram_sdqs5 = 0x00000030,
67 .dram_sdqs6 = 0x00000030,
68 .dram_sdqs7 = 0x00000030,
69 .dram_dqm0 = 0x00020030,
70 .dram_dqm1 = 0x00020030,
71 .dram_dqm2 = 0x00020030,
72 .dram_dqm3 = 0x00020030,
73 .dram_dqm4 = 0x00020030,
74 .dram_dqm5 = 0x00020030,
75 .dram_dqm6 = 0x00020030,
76 .dram_dqm7 = 0x00020030,
77};
78
79static const struct mx6dq_iomux_grp_regs dhcom6dq_grp_ioregs = {
80 .grp_ddr_type = 0x000C0000,
81 .grp_ddrmode_ctl = 0x00020000,
82 .grp_ddrpke = 0x00000000,
83 .grp_addds = 0x00000030,
84 .grp_ctlds = 0x00000030,
85 .grp_ddrmode = 0x00020000,
86 .grp_b0ds = 0x00000030,
87 .grp_b1ds = 0x00000030,
88 .grp_b2ds = 0x00000030,
89 .grp_b3ds = 0x00000030,
90 .grp_b4ds = 0x00000030,
91 .grp_b5ds = 0x00000030,
92 .grp_b6ds = 0x00000030,
93 .grp_b7ds = 0x00000030,
94};
95
96static const struct mx6sdl_iomux_ddr_regs dhcom6sdl_ddr_ioregs = {
97 .dram_sdclk_0 = 0x00020030,
98 .dram_sdclk_1 = 0x00020030,
99 .dram_cas = 0x00020030,
100 .dram_ras = 0x00020030,
101 .dram_reset = 0x00020030,
102 .dram_sdcke0 = 0x00003000,
103 .dram_sdcke1 = 0x00003000,
104 .dram_sdba2 = 0x00000000,
105 .dram_sdodt0 = 0x00003030,
106 .dram_sdodt1 = 0x00003030,
107 .dram_sdqs0 = 0x00000030,
108 .dram_sdqs1 = 0x00000030,
109 .dram_sdqs2 = 0x00000030,
110 .dram_sdqs3 = 0x00000030,
111 .dram_sdqs4 = 0x00000030,
112 .dram_sdqs5 = 0x00000030,
113 .dram_sdqs6 = 0x00000030,
114 .dram_sdqs7 = 0x00000030,
115 .dram_dqm0 = 0x00020030,
116 .dram_dqm1 = 0x00020030,
117 .dram_dqm2 = 0x00020030,
118 .dram_dqm3 = 0x00020030,
119 .dram_dqm4 = 0x00020030,
120 .dram_dqm5 = 0x00020030,
121 .dram_dqm6 = 0x00020030,
122 .dram_dqm7 = 0x00020030,
123};
124
125static const struct mx6sdl_iomux_grp_regs dhcom6sdl_grp_ioregs = {
126 .grp_ddr_type = 0x000C0000,
127 .grp_ddrmode_ctl = 0x00020000,
128 .grp_ddrpke = 0x00000000,
129 .grp_addds = 0x00000030,
130 .grp_ctlds = 0x00000030,
131 .grp_ddrmode = 0x00020000,
132 .grp_b0ds = 0x00000030,
133 .grp_b1ds = 0x00000030,
134 .grp_b2ds = 0x00000030,
135 .grp_b3ds = 0x00000030,
136 .grp_b4ds = 0x00000030,
137 .grp_b5ds = 0x00000030,
138 .grp_b6ds = 0x00000030,
139 .grp_b7ds = 0x00000030,
140};
141
142static const struct mx6_mmdc_calibration dhcom_mmdc_calib = {
Marek Vasut1d0b09b2017-11-09 11:50:13 +0100[diff] [blame^]143 .p0_mpwldectrl0 = 0x0011000E,
144 .p0_mpwldectrl1 = 0x000E001B,
145 .p1_mpwldectrl0 = 0x00190015,
146 .p1_mpwldectrl1 = 0x00070018,
147 .p0_mpdgctrl0 = 0x42720306,
148 .p0_mpdgctrl1 = 0x026F0266,
149 .p1_mpdgctrl0 = 0x4273030A,
150 .p1_mpdgctrl1 = 0x02740240,
151 .p0_mprddlctl = 0x45393B3E,
152 .p1_mprddlctl = 0x403A3747,
153 .p0_mpwrdlctl = 0x40434541,
154 .p1_mpwrdlctl = 0x473E4A3B,
Marek Vasut00671d92017-10-09 21:51:10 +0200[diff] [blame]155};
156
157static const struct mx6_ddr3_cfg dhcom_mem_ddr = {
158 .mem_speed = 1600,
Marek Vasut1d0b09b2017-11-09 11:50:13 +0100[diff] [blame^]159 .density = 2,
Marek Vasut00671d92017-10-09 21:51:10 +0200[diff] [blame]160 .width = 64,
161 .banks = 8,
162 .rowaddr = 14,
163 .coladdr = 10,
164 .pagesz = 2,
Marek Vasut1d0b09b2017-11-09 11:50:13 +0100[diff] [blame^]165 .trcd = 1312,
166 .trcmin = 5863,
167 .trasmin = 3750,
Marek Vasut00671d92017-10-09 21:51:10 +0200[diff] [blame]168};
169
170static const struct mx6_ddr_sysinfo dhcom_ddr_info = {
171 /* width of data bus:0=16,1=32,2=64 */
172 .dsize = 2,
Marek Vasut1d0b09b2017-11-09 11:50:13 +0100[diff] [blame^]173 .cs_density = 16,
Marek Vasut00671d92017-10-09 21:51:10 +0200[diff] [blame]174 .ncs = 1, /* single chip select */
Marek Vasut1d0b09b2017-11-09 11:50:13 +0100[diff] [blame^]175 .cs1_mirror = 1,
Marek Vasut00671d92017-10-09 21:51:10 +0200[diff] [blame]176 .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */
177 .rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */
178 .walat = 1, /* Write additional latency */
179 .ralat = 5, /* Read additional latency */
180 .mif3_mode = 3, /* Command prediction working mode */
181 .bi_on = 1, /* Bank interleaving enabled */
182 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
183 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
Marek Vasut1d0b09b2017-11-09 11:50:13 +0100[diff] [blame^]184 .refsel = 1, /* Refresh cycles at 32KHz */
185 .refr = 3, /* 4 refresh commands per refresh cycle */
Marek Vasut00671d92017-10-09 21:51:10 +0200[diff] [blame]186};
187
188static void ccgr_init(void)
189{
190 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
191
192 writel(0x00C03F3F, &ccm->CCGR0);
193 writel(0x0030FC03, &ccm->CCGR1);
194 writel(0x0FFFC000, &ccm->CCGR2);
195 writel(0x3FF00000, &ccm->CCGR3);
196 writel(0x00FFF300, &ccm->CCGR4);
197 writel(0x0F0000C3, &ccm->CCGR5);
198 writel(0x000003FF, &ccm->CCGR6);
199}
200
201/* Board ID */
202static iomux_v3_cfg_t const hwcode_pads[] = {
203 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
204 IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
205 IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
206};
207
208static void setup_iomux_boardid(void)
209{
210 /* HW code pins: Setup alternate function and configure pads */
211 SETUP_IOMUX_PADS(hwcode_pads);
212}
213
214/* GPIO */
215static iomux_v3_cfg_t const gpio_pads[] = {
216 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
217 IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
218 IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
219 IOMUX_PADS(PAD_CSI0_DAT17__GPIO6_IO03 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
220 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
221 IOMUX_PADS(PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
222 IOMUX_PADS(PAD_EIM_D27__GPIO3_IO27 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
223 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
224 IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
225 IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
226 IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
227 IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
228 IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
229 IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
230 IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
231 IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
232 IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
233 IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
234 IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
235 IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
236 IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
237 IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
238 IOMUX_PADS(PAD_CSI0_MCLK__GPIO5_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL)),
239};
240
241static void setup_iomux_gpio(void)
242{
243 SETUP_IOMUX_PADS(gpio_pads);
244}
245
246/* Ethernet */
247static iomux_v3_cfg_t const enet_pads[] = {
248 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
249 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
250 IOMUX_PADS(PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)),
251 IOMUX_PADS(PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
252 IOMUX_PADS(PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
253 IOMUX_PADS(PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
254 IOMUX_PADS(PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL)),
255 IOMUX_PADS(PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
256 IOMUX_PADS(PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
257 IOMUX_PADS(PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL)),
258 /* SMSC PHY Reset */
259 IOMUX_PADS(PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
260 /* ENET_VIO_GPIO */
261 IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
262 /* ENET_Interrupt - (not used) */
263 IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
264};
265
266static void setup_iomux_enet(void)
267{
268 SETUP_IOMUX_PADS(enet_pads);
269}
270
271/* SD interface */
272static iomux_v3_cfg_t const usdhc2_pads[] = {
273 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
274 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
275 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
276 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
277 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
278 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
279 IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
280};
281
282/* onboard microSD */
283static iomux_v3_cfg_t const usdhc3_pads[] = {
284 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
285 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
286 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
287 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
288 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
289 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
290 IOMUX_PADS(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
291};
292
293/* eMMC */
294static iomux_v3_cfg_t const usdhc4_pads[] = {
295 IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
296 IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
297 IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
298 IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
299 IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
300 IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
301 IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
302 IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
303 IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
304 IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
305};
306
307/* SD */
308static void setup_iomux_sd(void)
309{
310 SETUP_IOMUX_PADS(usdhc2_pads);
311 SETUP_IOMUX_PADS(usdhc3_pads);
312 SETUP_IOMUX_PADS(usdhc4_pads);
313}
314
315/* SPI */
316static iomux_v3_cfg_t const ecspi1_pads[] = {
317 /* SS0 */
318 IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(SPI_PAD_CTRL)),
319 IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
320 IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
321 IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
322};
323
324static void setup_iomux_spi(void)
325{
326 SETUP_IOMUX_PADS(ecspi1_pads);
327}
328
329int board_spi_cs_gpio(unsigned bus, unsigned cs)
330{
331 if (bus == 0 && cs == 0)
332 return IMX_GPIO_NR(2, 30);
333 else
334 return -1;
335}
336
337/* UART */
338static iomux_v3_cfg_t const uart1_pads[] = {
339 IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
340 IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
341};
342
343static void setup_iomux_uart(void)
344{
345 SETUP_IOMUX_PADS(uart1_pads);
346}
347
348/* USB */
349static iomux_v3_cfg_t const usb_pads[] = {
350 IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
351 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
352};
353
354static void setup_iomux_usb(void)
355{
356 SETUP_IOMUX_PADS(usb_pads);
357}
358
359void board_init_f(ulong dummy)
360{
361 /* setup AIPS and disable watchdog */
362 arch_cpu_init();
363
364 ccgr_init();
365 gpr_init();
366
367 /* setup GP timer */
368 timer_init();
369
370 setup_iomux_boardid();
371 setup_iomux_gpio();
372 setup_iomux_enet();
373 setup_iomux_sd();
374 setup_iomux_spi();
375 setup_iomux_uart();
376 setup_iomux_usb();
377
378 /* UART clocks enabled and gd valid - init serial console */
379 preloader_console_init();
380
381 /* Start the DDR DRAM */
382 if (is_mx6dq())
383 mx6dq_dram_iocfg(dhcom_mem_ddr.width, &dhcom6dq_ddr_ioregs,
384 &dhcom6dq_grp_ioregs);
385 else
386 mx6sdl_dram_iocfg(dhcom_mem_ddr.width, &dhcom6sdl_ddr_ioregs,
387 &dhcom6sdl_grp_ioregs);
388 mx6_dram_cfg(&dhcom_ddr_info, &dhcom_mmdc_calib, &dhcom_mem_ddr);
389
390 /* Perform DDR DRAM calibration */
391 udelay(100);
Marek Vasut00671d92017-10-09 21:51:10 +0200[diff] [blame]392 mmdc_do_dqs_calibration(&dhcom_ddr_info);
393
394 /* Clear the BSS. */
395 memset(__bss_start, 0, __bss_end - __bss_start);
396
397 /* load/boot image from boot device */
398 board_init_r(NULL, 0);
399}