| commit | 1d0b09b33ea6829203f51cdb23770cc39ccd3cf0 | [log] [tgz] |
|---|---|---|
| author | Marek Vasut <marex@denx.de> | Thu Nov 09 11:50:13 2017 +0100 |
| committer | Stefano Babic <sbabic@denx.de> | Thu Nov 16 10:43:22 2017 +0100 |
| tree | 5efda1c4b05b5273352f2d9ba8b201711241d880 | |
| parent | 7c6d277056d0fd64c3bee5a399665f83c037414f [diff] |
ARM: imx6: Adjust DDR DRAM settings on DHCOM i.MX6 PDK The board uses T-topology for the four x16 DRAM chips, so remove the write-leveling from the SPL as that is only usefly on fly-by topology and can be harmful on T-topology. Also update the DRAM timing with values from calibration on multiple boards. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>